From cd4cc31b21413090173abeb4528602663e0c2b3c Mon Sep 17 00:00:00 2001
From: Yingyi Huang <yingyihuang2000@outlook.com>
Date: Wed, 8 Jul 2026 16:30:14 -0700
Subject: [PATCH 1/2] Export Cake KMeans plan-runtime suite from Cake main
 a03428fc8

Plan-based launch runtime (per-signature LaunchPlan cache, prepacked
argument buffers, TMA variant-bank pointer rebinding) exported and
validated on 4x NVIDIA GB200: 124/124 correctness and ordered route
parity, hot public synchronized-E2E speedup vs the exact-07cf raw Triton
adapter min 1.0386 / geomean 1.6917 across all 124 contract records with
0 rows below the 1.0x publication floor.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
---
 cake_exports/kmeans/.gitignore                |     8 +
 cake_exports/kmeans/BENCHMARK_RESULTS.json    | 76007 ++++++++++++++++
 cake_exports/kmeans/EXPORT_TIMING.json        |    11 +
 cake_exports/kmeans/README.md                 |   567 +
 cake_exports/kmeans/RESULTS.md                |   426 +
 cake_exports/kmeans/VALIDATION.json           |   427 +
 cake_exports/kmeans/VALIDATION.md             |    41 +
 .../benchmarks/all_expected_routes.json       |  1142 +
 cake_exports/kmeans/benchmarks/benchmark.py   |  1645 +
 .../benchmarks/benchmark_exported_kernels.py  |   144 +
 .../kmeans/benchmarks/benchmark_shapes.py     |   252 +
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 .../flash_kmeans_triton_h200_raw_adapter.py   |   251 +
 .../kmeans/benchmarks/shape_records.json      |  4458 +
 cake_exports/kmeans/benchmarks/workload.py    |    29 +
 cake_exports/kmeans/pyproject.toml            |    40 +
 .../src/flashlib_cake_kmeans/__init__.py      |  1455 +
 .../src/flashlib_cake_kmeans/_benchmark.py    |   648 +
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 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0340.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0341.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0342.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0343.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0344.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0345.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0346.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0347.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0348.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0349.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0350.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0351.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0352.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0353.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0355.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0357.cu
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/kernels.py
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
 create mode 100644 cake_exports/kmeans/src/flashlib_cake_kmeans/tvm_ffi.py
 create mode 100644 cake_exports/kmeans/tests/test_benchmark_harness.py
 create mode 100644 cake_exports/kmeans/tests/test_correctness.py
 create mode 100644 cake_exports/kmeans/tests/test_exported_kernels.py

diff --git a/cake_exports/kmeans/.gitignore b/cake_exports/kmeans/.gitignore
new file mode 100644
index 00000000..735d478a
--- /dev/null
+++ b/cake_exports/kmeans/.gitignore
@@ -0,0 +1,8 @@
+__pycache__/
+*.py[cod]
+*.egg-info/
+.pytest_cache/
+.ruff_cache/
+results/
+build/
+dist/
diff --git a/cake_exports/kmeans/BENCHMARK_RESULTS.json b/cake_exports/kmeans/BENCHMARK_RESULTS.json
new file mode 100644
index 00000000..60f3f07d
--- /dev/null
+++ b/cake_exports/kmeans/BENCHMARK_RESULTS.json
@@ -0,0 +1,76007 @@
+{
+  "api": "flashlib_cake_kmeans.init(...).compute",
+  "artifact": "artifacts/generalize_auto_tuning/flash_kmeans_assign_20260620/dispatcher_perf_all_shapes_latest.md",
+  "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+  "baseline_entrypoint": "benchmarks.flash_kmeans_triton_h200_raw_adapter:TritonH20007cfRawAdapter.compute",
+  "baseline_name": "triton_h200_07cf_raw_adapter_v1",
+  "baseline_timing_boundary": "raw_inputs_default_output_shared_fused_pair_norm_plus_pinned_07cf_assign_synchronized_e2e",
+  "benchmark_registry_baseline_key": "triton_h200_07cf_dual_lane_v1",
+  "benchmark_registry_baseline_profile": {
+    "official": {
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_entrypoint": "benchmarks.flash_kmeans_triton_h200_raw_adapter:TritonH20007cfRawAdapter.compute",
+      "baseline_name": "triton_h200_07cf_raw_adapter_v1",
+      "baseline_timing_backend_field": "baseline_07cf_adapter_timing_backend",
+      "baseline_timing_boundary": "raw_inputs_default_output_shared_fused_pair_norm_plus_pinned_07cf_assign_synchronized_e2e",
+      "candidate_entrypoint": "flashlib_cake_kmeans.interface:FlashKMeansAssignRuntime.compute",
+      "candidate_timing_backend_field": "candidate_public_raw_timing_backend",
+      "candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
+      "role": "publication",
+      "speedup_denominator_metric": "candidate_public_raw_synchronized_e2e_ms",
+      "speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+      "speedup_numerator_metric": "baseline_07cf_adapter_synchronized_e2e_ms",
+      "timing_backend": "cupti"
+    },
+    "parity": {
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_entrypoint": "benchmarks.flash_kmeans_triton_h200:euclid_assign_triton_h200",
+      "baseline_name": "triton_h200_07cf_precomputed",
+      "baseline_timing_backend_field": "baseline_07cf_precomputed_timing_backend",
+      "baseline_timing_boundary": "precomputed_norms_preallocated_output_pinned_07cf_assignment_gpu_span",
+      "candidate_entrypoint": "flashlib_cake_kmeans.interface:flash_kmeans_assign_prepared",
+      "candidate_timing_backend_field": "candidate_precomputed_timing_backend",
+      "candidate_timing_boundary": "precomputed_norms_preallocated_output_prepared_assignment_gpu_span",
+      "role": "diagnostic_only",
+      "speedup_denominator_metric": "candidate_precomputed_gpu_span_ms",
+      "speedup_metric": "precomputed_gpu_speedup_vs_07cf",
+      "speedup_numerator_metric": "baseline_07cf_precomputed_gpu_span_ms",
+      "timing_backend": "cupti"
+    },
+    "registry_candidate_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
+    "shared_preprocess": {
+      "implementation_entrypoint": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+      "result_source_sha256_field": "preprocess_source_sha256",
+      "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104"
+    }
+  },
+  "benchmark_registry_baseline_sha256": "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c",
+  "benchmark_registry_candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
+  "candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
+  "evolution_summary": {
+    "mean_evolution_speedup": 19.980689035087718,
+    "mean_evolution_tflops": 25.401755701754386,
+    "min_evolution_speedup": 1.3307,
+    "row_count": 228,
+    "unique_shape_count": 225
+  },
+  "hardware": {
+    "arch": "sm_100a",
+    "device": "NVIDIA GB200"
+  },
+  "measured_candidate_entrypoint": "flashlib_cake_kmeans.interface:FlashKMeansAssignRuntime.compute",
+  "measurement_sessions": [
+    {
+      "adaptive_probe_scope": "separate_nonreportable_cupti_estimation_only",
+      "alternate_two_pointer_sets": true,
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_has_explicit_init": true,
+      "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+      "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+      "id": "3462c70f2aa84e4793077c9e9ca68837",
+      "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+      "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+      "interleaved": true,
+      "order_policy": "deterministic_interleaved_adjacent_ab_pairs",
+      "order_seed": "flashlib-kmeans-export-paired-replay-v1",
+      "precomputed_kernel_parity": {
+        "baseline_api": "euclid_assign_triton_h200_07cf",
+        "baseline_norm_policy": "explicit_precomputed_outside_timing",
+        "baseline_output_policy": "preallocated_outside_timing",
+        "both_pointer_sets_prepared_before_timing": true,
+        "candidate_api": "flash_kmeans_assign_prepared",
+        "candidate_norm_policy": "explicit_precomputed_outside_timing",
+        "candidate_output_policy": "preallocated_outside_timing"
+      },
+      "public_raw_e2e": {
+        "assignment_baseline": "frozen_07cf",
+        "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute(raw_inputs)",
+        "baseline_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+        "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "baseline_runtime_initialized_once": true,
+        "baseline_scratch_policy": "per_shape_per_stream_cached",
+        "candidate_api": "flashlib_cake_kmeans.init(...).compute(raw_inputs)",
+        "candidate_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+        "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "candidate_runtime_initialized_once": true,
+        "candidate_scratch_policy": "per_shape_per_stream_cached",
+        "comparison_scope": "complete_raw_input_operators_not_assignment_only",
+        "fixture_synchronized_before_cold_calls": true,
+        "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "shared_preprocess_cold_compile_attributed_to_lane": null
+      },
+      "randomized_or_interleaved_order": true,
+      "reportable_timing_collected": true,
+      "resident_multi_shape_cache_benchmarked": false,
+      "runtime_instances_reused_across_shapes": true,
+      "same_cupti_session": true,
+      "same_process": true,
+      "scope": "per_shape_single_cupti_activity_session_interleaved_paired_roles",
+      "sequential_full_sweeps": false,
+      "timing_blocks": "one_interleaved_cupti_activity_session_per_shape"
+    },
+    {
+      "adaptive_probe_scope": "separate_nonreportable_cupti_estimation_only",
+      "alternate_two_pointer_sets": true,
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_has_explicit_init": true,
+      "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+      "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+      "id": "a618b8f9b7234b02aa0a0e6f8a02f141",
+      "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+      "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+      "interleaved": true,
+      "order_policy": "deterministic_interleaved_adjacent_ab_pairs",
+      "order_seed": "flashlib-kmeans-export-paired-replay-v1",
+      "precomputed_kernel_parity": {
+        "baseline_api": "euclid_assign_triton_h200_07cf",
+        "baseline_norm_policy": "explicit_precomputed_outside_timing",
+        "baseline_output_policy": "preallocated_outside_timing",
+        "both_pointer_sets_prepared_before_timing": true,
+        "candidate_api": "flash_kmeans_assign_prepared",
+        "candidate_norm_policy": "explicit_precomputed_outside_timing",
+        "candidate_output_policy": "preallocated_outside_timing"
+      },
+      "public_raw_e2e": {
+        "assignment_baseline": "frozen_07cf",
+        "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute(raw_inputs)",
+        "baseline_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+        "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "baseline_runtime_initialized_once": true,
+        "baseline_scratch_policy": "per_shape_per_stream_cached",
+        "candidate_api": "flashlib_cake_kmeans.init(...).compute(raw_inputs)",
+        "candidate_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+        "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "candidate_runtime_initialized_once": true,
+        "candidate_scratch_policy": "per_shape_per_stream_cached",
+        "comparison_scope": "complete_raw_input_operators_not_assignment_only",
+        "fixture_synchronized_before_cold_calls": true,
+        "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "shared_preprocess_cold_compile_attributed_to_lane": null
+      },
+      "randomized_or_interleaved_order": true,
+      "reportable_timing_collected": true,
+      "resident_multi_shape_cache_benchmarked": false,
+      "runtime_instances_reused_across_shapes": true,
+      "same_cupti_session": true,
+      "same_process": true,
+      "scope": "per_shape_single_cupti_activity_session_interleaved_paired_roles",
+      "sequential_full_sweeps": false,
+      "timing_blocks": "one_interleaved_cupti_activity_session_per_shape"
+    },
+    {
+      "adaptive_probe_scope": "separate_nonreportable_cupti_estimation_only",
+      "alternate_two_pointer_sets": true,
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_has_explicit_init": true,
+      "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+      "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+      "id": "bb057d64f5dd4a68a07fac499aa57dd5",
+      "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+      "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+      "interleaved": true,
+      "order_policy": "deterministic_interleaved_adjacent_ab_pairs",
+      "order_seed": "flashlib-kmeans-export-paired-replay-v1",
+      "precomputed_kernel_parity": {
+        "baseline_api": "euclid_assign_triton_h200_07cf",
+        "baseline_norm_policy": "explicit_precomputed_outside_timing",
+        "baseline_output_policy": "preallocated_outside_timing",
+        "both_pointer_sets_prepared_before_timing": true,
+        "candidate_api": "flash_kmeans_assign_prepared",
+        "candidate_norm_policy": "explicit_precomputed_outside_timing",
+        "candidate_output_policy": "preallocated_outside_timing"
+      },
+      "public_raw_e2e": {
+        "assignment_baseline": "frozen_07cf",
+        "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute(raw_inputs)",
+        "baseline_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+        "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "baseline_runtime_initialized_once": true,
+        "baseline_scratch_policy": "per_shape_per_stream_cached",
+        "candidate_api": "flashlib_cake_kmeans.init(...).compute(raw_inputs)",
+        "candidate_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+        "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "candidate_runtime_initialized_once": true,
+        "candidate_scratch_policy": "per_shape_per_stream_cached",
+        "comparison_scope": "complete_raw_input_operators_not_assignment_only",
+        "fixture_synchronized_before_cold_calls": true,
+        "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "shared_preprocess_cold_compile_attributed_to_lane": null
+      },
+      "randomized_or_interleaved_order": true,
+      "reportable_timing_collected": true,
+      "resident_multi_shape_cache_benchmarked": false,
+      "runtime_instances_reused_across_shapes": true,
+      "same_cupti_session": true,
+      "same_process": true,
+      "scope": "per_shape_single_cupti_activity_session_interleaved_paired_roles",
+      "sequential_full_sweeps": false,
+      "timing_blocks": "one_interleaved_cupti_activity_session_per_shape"
+    },
+    {
+      "adaptive_probe_scope": "separate_nonreportable_cupti_estimation_only",
+      "alternate_two_pointer_sets": true,
+      "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+      "baseline_has_explicit_init": true,
+      "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+      "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+      "id": "3b3cb0beb21c413cab220416f38fa203",
+      "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+      "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+      "interleaved": true,
+      "order_policy": "deterministic_interleaved_adjacent_ab_pairs",
+      "order_seed": "flashlib-kmeans-export-paired-replay-v1",
+      "precomputed_kernel_parity": {
+        "baseline_api": "euclid_assign_triton_h200_07cf",
+        "baseline_norm_policy": "explicit_precomputed_outside_timing",
+        "baseline_output_policy": "preallocated_outside_timing",
+        "both_pointer_sets_prepared_before_timing": true,
+        "candidate_api": "flash_kmeans_assign_prepared",
+        "candidate_norm_policy": "explicit_precomputed_outside_timing",
+        "candidate_output_policy": "preallocated_outside_timing"
+      },
+      "public_raw_e2e": {
+        "assignment_baseline": "frozen_07cf",
+        "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute(raw_inputs)",
+        "baseline_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+        "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "baseline_runtime_initialized_once": true,
+        "baseline_scratch_policy": "per_shape_per_stream_cached",
+        "candidate_api": "flashlib_cake_kmeans.init(...).compute(raw_inputs)",
+        "candidate_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+        "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "candidate_runtime_initialized_once": true,
+        "candidate_scratch_policy": "per_shape_per_stream_cached",
+        "comparison_scope": "complete_raw_input_operators_not_assignment_only",
+        "fixture_synchronized_before_cold_calls": true,
+        "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "shared_preprocess_cold_compile_attributed_to_lane": null
+      },
+      "randomized_or_interleaved_order": true,
+      "reportable_timing_collected": true,
+      "resident_multi_shape_cache_benchmarked": false,
+      "runtime_instances_reused_across_shapes": true,
+      "same_cupti_session": true,
+      "same_process": true,
+      "scope": "per_shape_single_cupti_activity_session_interleaved_paired_roles",
+      "sequential_full_sweeps": false,
+      "timing_blocks": "one_interleaved_cupti_activity_session_per_shape"
+    }
+  ],
+  "metadata_only": false,
+  "official_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
+  "parity_metric": "precomputed_gpu_speedup_vs_07cf",
+  "precomputed_baseline_name": "triton_h200_07cf_precomputed",
+  "precomputed_parity_speedup_convention": "precomputed_gpu_speedup_vs_07cf = baseline_07cf_precomputed_gpu_span_ms / candidate_precomputed_gpu_span_ms",
+  "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+  "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+  "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
+  "publication_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+  "publication_speedup_convention": "public_raw_e2e_speedup_vs_07cf_adapter = baseline_07cf_adapter_synchronized_e2e_ms / candidate_public_raw_synchronized_e2e_ms",
+  "publication_speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+  "publication_timing_backend": "cupti",
+  "registry_candidate_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
+  "results": [
+    {
+      "B": 1,
+      "D": 112,
+      "K": 4096,
+      "N": 1408,
+      "baseline_07cf_adapter_bench_iters": 2218,
+      "baseline_07cf_adapter_gpu_span_ms": 0.088257,
+      "baseline_07cf_adapter_host_enqueue_ms": 0.1388325,
+      "baseline_07cf_adapter_inter_kernel_gap_ms": 0.037184,
+      "baseline_07cf_adapter_kernel_sum_ms": 0.051073,
+      "baseline_07cf_adapter_submission_ms": 0.1388325,
+      "baseline_07cf_adapter_synchronized_e2e_ms": 0.182849,
+      "baseline_07cf_adapter_timing_backend": "cupti",
+      "baseline_07cf_adapter_timing_diagnostics": {
+        "active_union_ms": {
+          "median": 0.051073
+        },
+        "activity_count": {
+          "median": 2.0
+        },
+        "cold_first_call": {
+          "host_enqueue_ms": 0.256929,
+          "synchronized_e2e_ms": 0.293665
+        },
+        "correlated_kernel_activity_count": {
+          "median": 2.0
+        },
+        "correlated_launch_activity_count": {
+          "median": 2.0
+        },
+        "gpu_span_ms": {
+          "median": 0.088257
+        },
+        "host_enqueue_ms": {
+          "median": 0.1388325
+        },
+        "inter_kernel_gap_ms": {
+          "median": 0.037184
+        },
+        "kernel_sum_ms": {
+          "median": 0.051073
+        },
+        "lane_primary_metric": "synchronized_e2e_ms",
+        "sample_count": 2218,
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+      "seed": 248003,
+      "source": "high_k_low_n"
+    },
+    {
+      "B": 2,
+      "D": 480,
+      "K": 1024,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 5.9879,
+      "evolution_flashlib_ms": 0.672447,
+      "evolution_kernel_ms": 0.197919,
+      "evolution_speedup": 3.3976,
+      "evolution_tflops": 20.3443,
+      "label": "post_d895_d480_b2_n2048_k1024_d480",
+      "route": "gap_pad_to_supported_seed_v1",
+      "runtime_coverage": false,
+      "seed": 248001,
+      "source": "new_high_gap"
+    },
+    {
+      "B": 4,
+      "D": 480,
+      "K": 1024,
+      "N": 8192,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 43.8869,
+      "evolution_flashlib_ms": 0.733983,
+      "evolution_kernel_ms": 0.24,
+      "evolution_speedup": 3.0583,
+      "evolution_tflops": 134.2177,
+      "label": "post_d895_d480_b4_n8192_k1024_d480",
+      "route": "gap_pad_to_supported_seed_v1",
+      "runtime_coverage": false,
+      "seed": 248002,
+      "source": "new_high_gap"
+    },
+    {
+      "B": 1,
+      "D": 48,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.275,
+      "evolution_flashlib_ms": 1.464301,
+      "evolution_kernel_ms": 0.21952,
+      "evolution_speedup": 6.6705,
+      "evolution_tflops": 1.8342,
+      "label": "post_d895_d48_b1_n512_k8192_d48",
+      "route": "gap_pad_to_supported_seed_v1",
+      "runtime_coverage": false,
+      "seed": 24803,
+      "source": "high_k_low_n"
+    },
+    {
+      "B": 2,
+      "D": 48,
+      "K": 512,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.6574,
+      "evolution_flashlib_ms": 0.30624,
+      "evolution_kernel_ms": 0.166656,
+      "evolution_speedup": 1.8376,
+      "evolution_tflops": 1.208,
+      "label": "post_d895_d48_b2_n2048_k512_d48",
+      "route": "gap_pad_to_supported_seed_v1",
+      "runtime_coverage": false,
+      "seed": 24801,
+      "source": "new_lowmid_gap"
+    },
+    {
+      "B": 4,
+      "D": 48,
+      "K": 1024,
+      "N": 8192,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 9.5879,
+      "evolution_flashlib_ms": 0.335967,
+      "evolution_kernel_ms": 0.179807,
+      "evolution_speedup": 1.8685,
+      "evolution_tflops": 17.9149,
+      "label": "post_d895_d48_b4_n8192_k1024_d48",
+      "route": "gap_pad_to_supported_seed_v1",
+      "runtime_coverage": false,
+      "seed": 24802,
+      "source": "new_lowmid_gap"
+    }
+  ],
+  "submission_metric": {
+    "field": "submission_ms",
+    "host_enqueue_alias_field": "host_enqueue_ms",
+    "relationship": "same_cpu_submission_bracket"
+  },
+  "timing_window_ms": {
+    "bench_ms": 100.0,
+    "warmup_ms": 20.0
+  },
+  "validation_shard": {
+    "count": 4,
+    "index": 0
+  },
+  "validation_shards": [
+    {
+      "count": 4,
+      "index": 0
+    },
+    {
+      "count": 4,
+      "index": 1
+    },
+    {
+      "count": 4,
+      "index": 2
+    },
+    {
+      "count": 4,
+      "index": 3
+    }
+  ]
+}
diff --git a/cake_exports/kmeans/EXPORT_TIMING.json b/cake_exports/kmeans/EXPORT_TIMING.json
new file mode 100644
index 00000000..add831ab
--- /dev/null
+++ b/cake_exports/kmeans/EXPORT_TIMING.json
@@ -0,0 +1,11 @@
+{
+  "host_wall_phase_seconds": {
+    "benchmark": 154.0538639901206,
+    "correctness": 17.579008210916072,
+    "validation_total": 171.63287220103666
+  },
+  "recorded_at_utc": "2026-07-08T23:29:04+00:00",
+  "reportable_gpu_timing_source": "BENCHMARK_RESULTS.json:CUPTI",
+  "schema": "loom-export-host-wall-phases-v1",
+  "validation_shard_count": 4
+}
diff --git a/cake_exports/kmeans/README.md b/cake_exports/kmeans/README.md
new file mode 100644
index 00000000..2a6881e2
--- /dev/null
+++ b/cake_exports/kmeans/README.md
@@ -0,0 +1,567 @@
+# Exported Loom Kernels
+
+## Pre-publication GPU validation: PASS — declared 124-shape performance floor
+
+- Hardware: `NVIDIA GB200` (`sm_100a`)
+- Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
+- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+
+#### Hot steady-state synchronized E2E speedup
+
+| Validated shape scope | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+
+#### Modeled after-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
+| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
+| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
+| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+
+#### Modeled including-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
+| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
+| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
+| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+
+- All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
+- `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
+- `Including-init amortized(N) = (init + first_compute + (N-1) * hot_median) / N`; it includes init. Each latency formula is evaluated separately for baseline and candidate, then reported as `baseline/candidate`. Both amortized scenarios are composed from measured components, not a directly timed N-call loop. A lane without explicit init uses `I=0`.
+- Init scope: `runtime_init_plus_standalone_shared_preprocess_support_once_per_validation_shard_process_device_operator`; composition: `runtime_init_plus_shared_preprocess_support_each_standalone_lane`; baseline has explicit init: `yes`.
+- Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
+- Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
+
+- Measured: `2026-07-08T23:29:04+00:00`
+- Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
+
+This repository was generated by `loom.export.kernel_repo`. It contains frozen
+CUDA source plus a lightweight Python binding that compiles the source with
+NVRTC and launches it through CUDA driver APIs.
+
+## Complete Workload Entry Points
+
+This export is a complete workload package. Its three review and execution
+entry points are deliberately separate and have stable names:
+
+- Python interface: [`src/flashlib_cake_kmeans/interface.py`](src/flashlib_cake_kmeans/interface.py) — public APIs: `FlashKMeansAssignRuntime`, `PreparedFlashKMeansAssign`, `init`, `prepare_flash_kmeans_assign`, `flash_kmeans_assign_prepared`, `flash_kmeans_assign`
+- GPU correctness test: [`tests/test_correctness.py`](tests/test_correctness.py)
+- CUPTI performance benchmark: [`benchmarks/benchmark.py`](benchmarks/benchmark.py)
+
+```bash
+pytest tests/test_correctness.py -q
+python benchmarks/benchmark.py --no-correctness --json results/performance.json
+```
+
+The public interface can be imported directly from the package root; the
+implementation contains frozen CUDA and bindings but no Weave IR.
+
+## Repository Layout
+
+```text
+src/flashlib_cake_kmeans/
+  __init__.py          # public Python exports
+  kernels.py           # KernelSpec, get_kernel(), launch_<kernel>() wrappers
+  tvm_ffi.py           # optional TVM FFI global-function registration
+  _runtime.py          # NVRTC + CUDA driver launch support
+  _benchmark.py        # strict CUPTI timing with cold-L2 flushing
+  manifest.json        # provenance, parameter order, launch metadata
+  cuda/*.cu            # frozen bundled CUDA sources; no Weave IR
+tests/
+  test_exported_kernels.py
+  test_benchmark_harness.py
+benchmarks/
+  benchmark_exported_kernels.py
+  benchmark_shapes.py  # semantic correctness + CUPTI performance runner
+  workload.py          # workload shapes/reference/metric adapter
+RESULTS.md             # correctness and performance results
+```
+
+## Kernels
+
+- `dispatch_kernel_0000`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0001`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0002`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0003`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0004`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0005`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0006`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0007`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0008`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0009`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0010`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0011`: `kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0012`: `kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0013`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0014`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0015`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0016`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0017`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0018`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0019`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0020`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0021`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0022`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0023`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0024`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0025`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0026`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0027`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0028`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0029`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0030`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0031`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0032`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0033`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0034`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0035`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0036`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0037`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0038`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0039`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0040`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0041`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0042`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0043`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0044`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0045`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0046`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0047`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0048`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0049`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0050`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0051`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0052`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0053`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0054`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0055`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0056`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0057`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0058`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0059`: `kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0060`: `kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0061`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0062`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0063`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0064`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0065`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0066`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0067`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0068`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0069`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0070`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0071`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0072`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0073`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0074`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0075`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0076`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0077`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0078`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0079`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0080`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0081`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0082`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0083`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0084`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0085`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0086`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0087`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0088`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0089`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0090`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0091`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0092`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0093`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0094`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0095`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0096`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0097`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0098`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0099`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0100`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0101`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0102`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0103`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0104`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0105`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0106`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0107`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0108`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0109`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0110`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0111`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0112`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0113`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0114`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0115`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0116`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0117`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0118`: `kernel_flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_keys, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0119`: `kernel_flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_keys, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0120`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0121`: `kernel_flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_keys, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0122`: `kernel_flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_keys, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0123`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0124`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0125`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0126`: `kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0127`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0128`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0129`: `kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0130`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0131`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0132`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0133`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0134`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0135`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0136`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0137`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0138`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0139`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0140`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0141`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0142`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0143`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0144`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0145`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0146`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0147`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0148`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0149`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0150`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0151`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0152`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0153`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0154`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0155`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0156`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0157`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0158`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0159`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0160`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0161`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0162`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0163`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0164`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0165`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0166`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0167`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0168`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0169`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0170`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0171`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0172`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0173`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0174`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0175`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0176`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0177`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0178`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0179`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0180`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0181`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0182`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0183`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0184`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0185`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0186`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0187`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0188`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0189`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0190`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0191`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0192`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0193`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0194`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0195`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0196`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0197`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0198`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0199`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0200`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0201`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0202`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0203`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0204`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0205`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0206`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0207`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0208`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0209`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0210`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0211`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0212`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0213`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0214`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0215`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0216`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0217`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0218`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0219`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0220`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0221`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0222`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0223`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0224`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0225`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0226`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0227`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0228`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0229`: `kernel_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0230`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0231`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0232`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0233`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0234`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0235`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0236`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0237`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0238`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0239`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0240`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0241`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0242`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0243`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0244`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0245`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0246`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0247`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0248`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0249`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0250`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0251`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0252`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0253`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0254`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0255`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0256`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0257`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0258`: `kernel_flash_kmeans_assign_d480_splitk_partial_d32k256_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0259`: `kernel_flash_kmeans_assign_d480_splitk_reduce_d32k256_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0260`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0261`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0262`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0263`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0264`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0265`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0266`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0267`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0268`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0269`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0270`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0271`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0272`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0273`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0274`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0275`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0276`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0277`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0278`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0279`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0280`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0281`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0282`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0283`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0284`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0285`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0286`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0287`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0288`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0289`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0290`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0291`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0292`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0293`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0294`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0295`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0296`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0297`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0298`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0299`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0300`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0301`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0302`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0303`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0304`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0305`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0306`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0307`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0308`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0309`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0310`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0311`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0312`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0313`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0314`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0315`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0316`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0317`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0318`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0319`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0320`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0321`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0322`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0323`: `kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0324`: `kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0325`: `kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0326`: `kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0327`: `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0328`: `kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0329`: `kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0330`: `kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0331`: `kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0332`: `kernel_flash_kmeans_assign_microdim_direct_9c0d_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0333`: `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0334`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0335`: `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0336`: `kernel_flash_kmeans_assign_microdim_6cd2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0337`: `kernel_flash_kmeans_assign_lowdim_e50c_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0338`: `kernel_flash_kmeans_assign_gap_pad_pack_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, D_PAD, total_x_pad, total_c_pad)
+- `dispatch_kernel_0339`: `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0340`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0341`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0342`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0343`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0344`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0345`: `kernel_flash_kmeans_assign_d480_splitk_partial_d32k256_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles, K_slices)
+- `dispatch_kernel_0346`: `kernel_flash_kmeans_assign_d480_splitk_reduce_d32k256_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_slices)
+- `dispatch_kernel_0347`: `kernel_flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0348`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, partial_scores, partial_indices, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0349`: `kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce`, launch_mode=`standard`, threads=256, shared_mem=0, params=(partial_scores, partial_indices, out, B, N, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0350`: `kernel_flash_kmeans_assign_d288_exactd_a532_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0351`: `kernel_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, x_sq, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0352`: `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+- `dispatch_kernel_0353`: `kernel_flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0354`: `kernel_flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0355`: `kernel_flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x_tmap, c_tmap, c_sq, out, B, N, D, K, num_n_tiles, K_tiles)
+- `dispatch_kernel_0356`: `kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, c_sq, out, B, N, D, K, num_n_tiles)
+- `dispatch_kernel_0357`: `kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1`, launch_mode=`standard`, threads=256, shared_mem=0, params=(x, centroids, x_pad, c_pad, B, N, D, K, total_x_pad, total_c_pad)
+
+## Install
+
+```bash
+python -m pip install -e .
+```
+
+The runtime expects PyTorch and a CUDA Python package that provides
+`cuda.bindings.driver` and `cuda.bindings.nvrtc`.
+
+Install the optional Apache TVM FFI adapter with:
+
+```bash
+python -m pip install -e ".[tvm-ffi]"
+```
+
+## API Entry Points
+
+The complete workload API is exported from the package root. The bindings below
+remain available for inspecting or launching individual frozen kernels.
+
+- `flashlib_cake_kmeans.KERNELS`: mapping from exported kernel name to `ExportedKernel`.
+- `flashlib_cake_kmeans.get_kernel(name)`: inspect metadata, source text, or compile.
+- `flashlib_cake_kmeans.launch_<kernel>(*args, grid=...)`: low-level launch wrapper.
+- `ExportedKernel.source_text()`: read the frozen CUDA source.
+- `ExportedKernel.compile(arch="sm_100a")`: compile with NVRTC.
+- `ExportedKernel.launch(...)`: launch with explicit CUDA parameter order.
+
+Frozen sources are compiled through a process-local content-addressed cache.
+Aliases with identical CUDA source, architecture, options, active device, and
+function symbol share one loaded kernel; translation units with different
+symbols or active device contexts share the NVRTC cubin but retain separate
+loaded function objects. Semantic APIs may use
+the generated `_runtime.launch_context(...)` helper to capture one current or
+explicit PyTorch CUDA stream for every stage in a multi-kernel call.
+
+```python
+import torch
+from flashlib_cake_kmeans import get_kernel, launch_dispatch_kernel_0000
+
+kernel = get_kernel("dispatch_kernel_0000")
+print(kernel.parameters)
+
+# Pass CUDA tensors or scalar values in the parameter order shown in
+# src/flashlib_cake_kmeans/manifest.json. Pointer parameters accept CUDA tensors
+# or integer device pointers. Scalar parameters are range-checked and packed
+# with the exact signedness and width recorded by the Cake-STD-derived ABI.
+launch_dispatch_kernel_0000(*args, grid=(1, 1, 1))
+torch.cuda.synchronize()
+```
+
+## TVM FFI
+
+`flashlib_cake_kmeans.register_tvm_ffi()` registers both the workload-level public API
+declared by a complete export plan and every low-level frozen kernel in the
+TVM FFI global registry. Tensor arguments use DLPack zero-copy conversion and
+launches honor the current TVM FFI CUDA stream.
+
+```python
+import tvm_ffi
+import flashlib_cake_kmeans
+
+names = flashlib_cake_kmeans.register_tvm_ffi()
+print(names)
+
+# Complete plans expose semantic functions as <package>.<public_name>.
+semantic = tvm_ffi.get_global_func("flashlib_cake_kmeans.<public_name>", allow_missing=True)
+
+# Low-level functions use <package>.launch_<kernel>. The final seven
+# positional arguments are grid xyz, block xyz, and dynamic shared-memory bytes.
+launch = tvm_ffi.get_global_func("flashlib_cake_kmeans.launch_dispatch_kernel_0000")
+launch(*kernel_args, 1, 1, 1, 256, 1, 1, 0)
+```
+
+## Correctness And Performance
+
+Recorded correctness and performance results live in `RESULTS.md`.
+`benchmarks/workload.py` is the workload adapter: it declares concrete shapes
+and builds candidate/reference/compare callables for each shape. When the
+export command receives `--benchmark-adapter path/to/workload.py`, the
+generated repository is immediately runnable; otherwise the file is an
+explicit template that must be completed before performance can be reported.
+
+## Tests
+
+The exported repository includes unit tests that do not require a GPU or CUDA
+Python bindings:
+
+```bash
+python -m pip install -e ".[test]"
+pytest
+```
+
+## Benchmarks
+
+The generated benchmark script measures NVRTC compile latency for the frozen
+CUDA sources. It is a build/runtime smoke benchmark, not a semantic kernel
+throughput benchmark:
+
+```bash
+python benchmarks/benchmark_exported_kernels.py --arch sm_100a --json results/compile_benchmark.json
+python benchmarks/benchmark_shapes.py --json results/shape_benchmark.json
+```
+
+The shape runner checks correctness before timing and refuses to report
+performance unless the requested timing backend is CUPTI. `gpu_span_ms` remains
+the official kernel timing used for throughput and speedup. Each result also
+records the exact per-iteration kernel sum, active interval union, uncovered
+gap, activity count, host enqueue bracket, synchronized end-to-end bracket, and
+the first semantic-call host diagnostic. Host brackets may include an internal
+API synchronization. Cold-L2 flushing completes before the host bracket starts,
+so synchronized E2E isolates semantic call start through candidate completion.
+Neither host bracket may be substituted for GPU-only timing.
+
+Stateful production plans may also publish an init-once lifecycle record. It
+separates the one-time runtime init, first-signature compute, repeated hot
+``runtime.compute`` distribution, and modeled amortized latency. Init and first
+compute remain CUPTI-timestamp host diagnostics; only the repeated-call GPU span
+is strict correlated CUPTI activity. The report states the output/preprocessing
+policy, per-shard init samples, cache hit/miss evidence, clear policy, and whether
+resident multi-shape caching was actually measured.
diff --git a/cake_exports/kmeans/RESULTS.md b/cake_exports/kmeans/RESULTS.md
new file mode 100644
index 00000000..1e27fdd3
--- /dev/null
+++ b/cake_exports/kmeans/RESULTS.md
@@ -0,0 +1,426 @@
+# Correctness And Performance Results
+
+## Export Provenance
+
+- Package: `flashlib_cake_kmeans`
+- Source repository: `ssh://git@gitlab-master.nvidia.com:12051/cake/cake.git`
+- Source commit: `a03428fc8362e2785d2e6a657fd70a74c8ed1c0d`
+- Generated at: `2026-07-08T23:26:07.392069+00:00`
+
+## Latest Recorded Results
+
+## Pre-publication GPU validation: PASS — declared 124-shape performance floor
+
+- Hardware: `NVIDIA GB200` (`sm_100a`)
+- Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
+- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+
+#### Hot steady-state synchronized E2E speedup
+
+| Validated shape scope | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+
+#### Modeled after-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
+| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
+| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
+| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+
+#### Modeled including-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
+| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
+| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
+| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+
+- All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
+- `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
+- `Including-init amortized(N) = (init + first_compute + (N-1) * hot_median) / N`; it includes init. Each latency formula is evaluated separately for baseline and candidate, then reported as `baseline/candidate`. Both amortized scenarios are composed from measured components, not a directly timed N-call loop. A lane without explicit init uses `I=0`.
+- Init scope: `runtime_init_plus_standalone_shared_preprocess_support_once_per_validation_shard_process_device_operator`; composition: `runtime_init_plus_shared_preprocess_support_each_standalone_lane`; baseline has explicit init: `yes`.
+- Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
+- Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
+
+- Measured: `2026-07-08T23:29:04+00:00`
+- Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
+
+The machine-readable per-shape public lifecycle and CUPTI evidence is in [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json).
+
+## Result Table
+
+| Test | Hardware | Command | Result |
+| --- | --- | --- | --- |
+| metadata unit tests | not required | `pytest tests/test_exported_kernels.py tests/test_benchmark_harness.py -q` | pending |
+| NVRTC compile benchmark | CUDA host | `python benchmarks/benchmark_exported_kernels.py --arch sm_100a --json results/compile_benchmark.json` | pending |
+| semantic correctness | target GPU | `pytest tests/test_correctness.py -q` | PASS |
+| kernel performance | target GPU | `python benchmarks/benchmark.py --no-correctness` | PASS (declared publication floor) |
+
+## Kernel Inventory
+
+| Name | Symbol | Launch Mode | Threads | Shared Memory Bytes |
+| --- | --- | --- | ---: | ---: |
+| `dispatch_kernel_0000` | `kernel_flash_kmeans_assign_lowdim_pack_e50c_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0001` | `kernel_flash_kmeans_assign_lowdim_e50c_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0002` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10` | `standard` | 256 | 0 |
+| `dispatch_kernel_0003` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_v10` | `standard` | 256 | 0 |
+| `dispatch_kernel_0004` | `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0005` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0006` | `kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0007` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0008` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0009` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0010` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0011` | `kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0012` | `kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0013` | `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0014` | `kernel_flash_kmeans_assign_microdim_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0015` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0020` | `kernel_flash_kmeans_assign_microdim_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0021` | `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0022` | `kernel_flash_kmeans_assign_microdim_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0023` | `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0100` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_v15` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0105` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0107` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0108` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0109` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0110` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0111` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0112` | `kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0113` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0114` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0115` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0116` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0117` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0118` | `kernel_flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0119` | `kernel_flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0122` | `kernel_flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0123` | `kernel_flash_kmeans_assign_highd_splitd_6fcf_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0124` | `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0125` | `kernel_flash_kmeans_assign_microdim_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0126` | `kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4` | `standard` | 256 | 0 |
+| `dispatch_kernel_0127` | `kernel_flash_kmeans_assign_microdim_pack_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0128` | `kernel_flash_kmeans_assign_microdim_6cd2_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0129` | `kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0130` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
+| `dispatch_kernel_0131` | `kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0138` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0140` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0142` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
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+| `dispatch_kernel_0144` | `kernel_flash_kmeans_assign_gap_pad_pack_v1` | `standard` | 256 | 0 |
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diff --git a/cake_exports/kmeans/VALIDATION.json b/cake_exports/kmeans/VALIDATION.json
new file mode 100644
index 00000000..e1669133
--- /dev/null
+++ b/cake_exports/kmeans/VALIDATION.json
@@ -0,0 +1,427 @@
+{
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+    "below_minimum_speedup_count": 0,
+    "floor_enforced": true,
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+      "benchmarks/benchmark.py",
+      "--no-correctness",
+      "--json",
+      "BENCHMARK_RESULTS.shard-0000-of-0004.json",
+      "--shard-index",
+      "0",
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+      "4",
+      "--quiet"
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+    [
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+      "benchmarks/benchmark.py",
+      "--no-correctness",
+      "--json",
+      "BENCHMARK_RESULTS.shard-0001-of-0004.json",
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+    [
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+      "benchmarks/benchmark.py",
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+      "BENCHMARK_RESULTS.shard-0002-of-0004.json",
+      "--shard-index",
+      "2",
+      "--shard-count",
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+      "--quiet"
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+    [
+      "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+      "benchmarks/benchmark.py",
+      "--no-correctness",
+      "--json",
+      "BENCHMARK_RESULTS.shard-0003-of-0004.json",
+      "--shard-index",
+      "3",
+      "--shard-count",
+      "4",
+      "--quiet"
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+    "-m",
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+  "measured_at_utc": "2026-07-08T23:29:04+00:00",
+  "minimum_speedup": 1.0,
+  "performance_shape_count": 124,
+  "performance_speedup_denominator_metric": "candidate_public_raw_synchronized_e2e_ms",
+  "performance_speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+  "performance_speedup_numerator_metric": "baseline_07cf_adapter_synchronized_e2e_ms",
+  "phase_seconds": {
+    "benchmark": 154.0538639901206,
+    "correctness": 17.579008210916072,
+    "validation_total": 171.63287220103666
+  },
+  "publication_performance_floor": {
+    "below_floor": [],
+    "below_floor_count": 0,
+    "minimum_speedup": 1.0,
+    "scope": "all_benchmarked_shapes",
+    "shape_count": 124,
+    "shape_labels": [
+      "adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112",
+      "adjacent_1d49_d128_forced_fallback_b5_n7296_k512_d128",
+      "adjacent_1d49_d224_highn_overlap_b5_n5632_k768_d224",
+      "adjacent_1d49_d288_low_n_heldout_b3_n1152_k2048_d288",
+      "adjacent_1d49_d352_request_highk_b2_n1024_k8192_d352",
+      "adjacent_1d49_d416_random_b4_n3840_k512_d416",
+      "adjacent_1d49_d480_smallk_boundary_b2_n2816_k256_d480",
+      "adjacent_1d49_d48_lowk_boundary_b4_n3968_k256_d48",
+      "adjacent_3328_d112_highk_low_n_b2_n512_k8192_d112",
+      "adjacent_3328_d128_exact_guard_k_neighbor_b8_n8192_k512_d128",
+      "adjacent_3328_d224_tail_div_b3_n3840_k512_d224",
+      "adjacent_3328_d288_guard_overlap_b4_n8192_k256_d288",
+      "adjacent_3328_d352_random_legal_b3_n2048_k768_d352",
+      "adjacent_3328_d416_highk_low_n_b1_n384_k8192_d416",
+      "adjacent_3328_d480_min_boundary_b1_n128_k256_d480",
+      "adjacent_3328_d48_small_boundary_b1_n256_k256_d48",
+      "adjacent_5600_d112_odd_tile_tail_b5_n2176_k512_d112",
+      "adjacent_5600_d128_fallback_neighbor_b8_n8320_k256_d128",
+      "adjacent_5600_d224_k512_overlap_b3_n3072_k512_d224",
+      "adjacent_5600_d288_mid_highk_b2_n1024_k2048_d288",
+      "adjacent_5600_d352_splitk_edge_b2_n768_k4096_d352",
+      "adjacent_5600_d416_smallk_boundary_b4_n2048_k256_d416",
+      "adjacent_5600_d480_random_b1_n1536_k1024_d480",
+      "adjacent_5600_d48_low_n_boundary_b3_n1536_k256_d48",
+      "adjacent_68cf_d112_tail_b5_n2944_k512_d112",
+      "adjacent_68cf_d128_forced_fallback_b7_n6016_k512_d128",
+      "adjacent_68cf_d224_overlap_b3_n5120_k1024_d224",
+      "adjacent_68cf_d288_boundary_b2_n1920_k512_d288",
+      "adjacent_68cf_d352_tail_b3_n2816_k768_d352",
+      "adjacent_68cf_d416_overlap_b2_n2304_k1024_d416",
+      "adjacent_68cf_d480_boundary_b4_n1664_k512_d480",
+      "adjacent_68cf_d48_boundary_b4_n2304_k512_d48",
+      "adjacent_8f09_d112_small_highk_b1_n384_k4096_d112",
+      "adjacent_8f09_d128_fallback_neighbor_b4_n4480_k512_d128",
+      "adjacent_8f09_d224_low_n_boundary_b4_n1536_k256_d224",
+      "adjacent_8f09_d288_k768_overlap_b1_n2560_k768_d288",
+      "adjacent_8f09_d352_smallk_large_n_b4_n4096_k256_d352",
+      "adjacent_8f09_d416_midk_tail_b3_n3456_k768_d416",
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+      "adjacent_8f09_d48_medium_tail_b2_n1792_k512_d48",
+      "adjacent_9ca0_d112_tail_div_b3_n3840_k768_d112",
+      "adjacent_9ca0_d128_exact_guard_neighbor_b8_n8064_k256_d128",
+      "adjacent_9ca0_d224_guard_overlap_b2_n4096_k256_d224",
+      "adjacent_9ca0_d288_highk_low_n_b1_n384_k4096_d288",
+      "adjacent_9ca0_d352_splitk_boundary_b1_n512_k8192_d352",
+      "adjacent_9ca0_d416_splitk_min_b1_n1024_k4096_d416",
+      "adjacent_9ca0_d480_splitd_large_n_b2_n4096_k512_d480",
+      "adjacent_9ca0_d48_guard_boundary_b6_n12288_k512_d48",
+      "adjacent_a2f8_d112_lowk_tail_b4_n3456_k256_d112",
+      "adjacent_a2f8_d128_odd_fallback_b6_n8576_k512_d128",
+      "adjacent_a2f8_d224_highn_overlap_b2_n6144_k768_d224",
+      "adjacent_a2f8_d288_splitk_probe_b1_n640_k4096_d288",
+      "adjacent_a2f8_d352_smallk_boundary_b4_n1024_k256_d352",
+      "adjacent_a2f8_d416_random_b2_n2560_k768_d416",
+      "adjacent_a2f8_d480_highk_request_b1_n896_k4096_d480",
+      "adjacent_a2f8_d48_k1024_boundary_b2_n768_k1024_d48",
+      "adjacent_c44f_d112_odd_tail_b2_n3200_k768_d112",
+      "adjacent_c44f_d128_forced_fallback_b6_n6272_k512_d128",
+      "adjacent_c44f_d224_overlap_b4_n4480_k512_d224",
+      "adjacent_c44f_d288_highk_heldout_b2_n768_k4096_d288",
+      "adjacent_c44f_d352_random_b1_n3328_k768_d352",
+      "adjacent_c44f_d416_highk_request_b3_n512_k8192_d416",
+      "adjacent_c44f_d480_boundary_b5_n2048_k512_d480",
+      "adjacent_c44f_d48_midk_boundary_b3_n2688_k768_d48",
+      "adjacent_d9d5_d112_highk_request_b3_n768_k8192_d112",
+      "adjacent_d9d5_d128_guard_miss_fallback_b5_n6016_k1024_d128",
+      "adjacent_d9d5_d224_random_midk_b2_n2944_k1280_d224",
+      "adjacent_d9d5_d288_heldout_low_n_b1_n896_k4096_d288",
+      "adjacent_d9d5_d352_random_b5_n2304_k768_d352",
+      "adjacent_d9d5_d416_highk_request_b2_n640_k8192_d416",
+      "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480",
+      "adjacent_d9d5_d48_highk_heldout_b2_n640_k4096_d48",
+      "adjacent_ef00_d112_odd_tail_b4_n3712_k1024_d112",
+      "adjacent_ef00_d128_forced_fallback_b4_n7552_k512_d128",
+      "adjacent_ef00_d224_midn_overlap_b2_n5376_k512_d224",
+      "adjacent_ef00_d288_highk_heldout_b1_n1664_k4096_d288",
+      "adjacent_ef00_d352_request_low_n_b3_n896_k8192_d352",
+      "adjacent_ef00_d416_random_midk_b1_n2176_k768_d416",
+      "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480",
+      "adjacent_ef00_d48_midn_boundary_b3_n3456_k512_d48",
+      "post_d895_d112_b1_n256_k256_d112",
+      "post_d895_d112_b1_n512_k8192_d112",
+      "post_d895_d112_b2_n2048_k512_d112",
+      "post_d895_d112_b4_n8192_k1024_d112",
+      "post_d895_d128_fallback_b3_n1920_k256_d128",
+      "post_d895_d128_fallback_b5_n2176_k512_d128",
+      "post_d895_d128_fallback_b7_n2432_k1024_d128",
+      "post_d895_d128_paired_b2_n262144_k256_d128",
+      "post_d895_d128_paired_b8_n8192_k256_d128",
+      "post_d895_d144_b1_n256_k256_d144",
+      "post_d895_d144_b1_n512_k8192_d144",
+      "post_d895_d144_b2_n2048_k1024_d144",
+      "post_d895_d144_b4_n8192_k1024_d144",
+      "post_d895_d16_b4_n32768_k1024_d16",
+      "post_d895_d16_b8_n65536_k512_d16",
+      "post_d895_d176_b1_n256_k256_d176",
+      "post_d895_d176_b1_n512_k8192_d176",
+      "post_d895_d176_b2_n2048_k1024_d176",
+      "post_d895_d176_b4_n8192_k1024_d176",
+      "post_d895_d224_b1_n256_k256_d224",
+      "post_d895_d224_b1_n512_k8192_d224",
+      "post_d895_d224_b2_n2048_k1024_d224",
+      "post_d895_d224_b4_n8192_k1024_d224",
+      "post_d895_d288_b1_n256_k256_d288",
+      "post_d895_d288_b1_n512_k8192_d288",
+      "post_d895_d288_b2_n2048_k1024_d288",
+      "post_d895_d288_b4_n8192_k1024_d288",
+      "post_d895_d32_b4_n32768_k1024_d32",
+      "post_d895_d32_b8_n65536_k512_d32",
+      "post_d895_d352_b1_n256_k256_d352",
+      "post_d895_d352_b1_n512_k8192_d352",
+      "post_d895_d352_b2_n2048_k1024_d352",
+      "post_d895_d352_b4_n8192_k1024_d352",
+      "post_d895_d416_b1_n256_k256_d416",
+      "post_d895_d416_b1_n512_k8192_d416",
+      "post_d895_d416_b2_n2048_k1024_d416",
+      "post_d895_d416_b4_n8192_k1024_d416",
+      "post_d895_d480_b1_n256_k256_d480",
+      "post_d895_d480_b1_n512_k8192_d480",
+      "post_d895_d480_b2_n2048_k1024_d480",
+      "post_d895_d480_b4_n8192_k1024_d480",
+      "post_d895_d48_b1_n512_k8192_d48",
+      "post_d895_d48_b2_n2048_k512_d48",
+      "post_d895_d48_b4_n8192_k1024_d48"
+    ],
+    "speedup_vs_baseline": {
+      "geomean": 1.6916873320768158,
+      "max": 3.1904450554863906,
+      "median": 1.6730758887255512,
+      "min": 1.038602901150967,
+      "p90": 2.2643380868174727,
+      "sample_count": 124
+    },
+    "status": "passed"
+  },
+  "route_count": 124,
+  "runtime_lifecycle": {
+    "amortized_after_init_synchronized_e2e_speedup": {
+      "1": {
+        "geomean": 1.3889160389178896,
+        "max": 10.779323991419206,
+        "median": 3.355393396642872,
+        "min": 0.07586420392417595,
+        "p90": 4.006561914159356,
+        "sample_count": 124
+      },
+      "10": {
+        "geomean": 1.307355798617821,
+        "max": 10.53411537391263,
+        "median": 2.7971699472139107,
+        "min": 0.1082360578653832,
+        "p90": 3.2902130577424313,
+        "sample_count": 124
+      },
+      "100": {
+        "geomean": 1.321002621423908,
+        "max": 8.649797268629165,
+        "median": 1.8382901113434449,
+        "min": 0.2874713583728166,
+        "p90": 2.447388612352715,
+        "sample_count": 124
+      },
+      "1000": {
+        "geomean": 1.5936102009532662,
+        "max": 3.8584927877502286,
+        "median": 1.6051653436433109,
+        "min": 0.9247614976643037,
+        "p90": 2.2810664792185826,
+        "sample_count": 124
+      }
+    },
+    "amortized_including_init_synchronized_e2e_speedup": {
+      "1": {
+        "geomean": 0.9787867358001275,
+        "max": 15.098129694717327,
+        "median": 2.392392494120844,
+        "min": 0.07339598623291214,
+        "p90": 14.903145960609656,
+        "sample_count": 124
+      },
+      "10": {
+        "geomean": 0.9883599649332888,
+        "max": 14.74946941441697,
+        "median": 2.3838259809720013,
+        "min": 0.07827496375561803,
+        "p90": 14.52521021193764,
+        "sample_count": 124
+      },
+      "100": {
+        "geomean": 1.0625734771300246,
+        "max": 12.280738012861928,
+        "median": 2.266977314672681,
+        "min": 0.10470166796960959,
+        "p90": 11.64426554947311,
+        "sample_count": 124
+      },
+      "1000": {
+        "geomean": 1.3037983467106373,
+        "max": 6.147177463228467,
+        "median": 1.3855552638525674,
+        "min": 0.3072695344894631,
+        "p90": 4.849531660761203,
+        "sample_count": 124
+      }
+    },
+    "baseline_has_explicit_init": true,
+    "baseline_hot_public_synchronized_e2e_ms": {
+      "geomean": 0.20105525733859214,
+      "max": 0.48014650000000003,
+      "median": 0.172529,
+      "min": 0.159457,
+      "p90": 0.3341426500000001,
+      "sample_count": 124
+    },
+    "baseline_init_host_enqueue_ms": {
+      "geomean": 36.37204484396895,
+      "max": 38.303733,
+      "median": 37.78005,
+      "min": 32.011411,
+      "p90": 38.1521769,
+      "sample_count": 4
+    },
+    "baseline_init_synchronized_e2e_ms": {
+      "geomean": 134.60988585908277,
+      "max": 511.423938,
+      "median": 240.2103465,
+      "min": 37.838611,
+      "p90": 490.6082571,
+      "sample_count": 4
+    },
+    "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+    "candidate_first_compute_host_enqueue_ms": {
+      "geomean": 6.0825652761787,
+      "max": 91.566558,
+      "median": 2.2524765,
+      "min": 1.560873,
+      "p90": 67.7166651,
+      "sample_count": 124
+    },
+    "candidate_first_compute_synchronized_e2e_ms": {
+      "geomean": 6.151633003253004,
+      "max": 91.62739,
+      "median": 2.3083485,
+      "min": 1.583753,
+      "p90": 67.7591774,
+      "sample_count": 124
+    },
+    "candidate_hot_compute_gpu_span_ms": {
+      "geomean": 0.044683032963121115,
+      "max": 0.390658,
+      "median": 0.0421445,
+      "min": 0.014848,
+      "p90": 0.1080554,
+      "sample_count": 124
+    },
+    "candidate_hot_compute_host_enqueue_ms": {
+      "geomean": 0.07779807502075908,
+      "max": 0.13169599999999998,
+      "median": 0.07708899999999999,
+      "min": 0.066816,
+      "p90": 0.0829399,
+      "sample_count": 124
+    },
+    "candidate_hot_compute_synchronized_e2e_ms": {
+      "geomean": 0.11884894656730967,
+      "max": 0.459266,
+      "median": 0.10857675,
+      "min": 0.088064,
+      "p90": 0.1767082,
+      "sample_count": 124
+    },
+    "candidate_init_host_enqueue_ms": {
+      "geomean": 36.68171053908005,
+      "max": 38.535318000000004,
+      "median": 38.086867999999996,
+      "min": 32.388565,
+      "p90": 38.4300921,
+      "sample_count": 4
+    },
+    "candidate_init_synchronized_e2e_ms": {
+      "geomean": 130.63995290830067,
+      "max": 526.030323,
+      "median": 242.07677249999998,
+      "min": 32.456148999999996,
+      "p90": 501.9887073,
+      "sample_count": 4
+    },
+    "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+    "hot_gpu_span_speedup": {
+      "geomean": 2.008775202457142,
+      "max": 5.886473025071239,
+      "median": 1.9678408409147718,
+      "min": 0.9682996380465778,
+      "p90": 3.371271168769499,
+      "sample_count": 124
+    },
+    "hot_synchronized_e2e_speedup": {
+      "geomean": 1.6916873320768158,
+      "max": 3.1904450554863906,
+      "median": 1.6730758887255512,
+      "min": 1.038602901150967,
+      "p90": 2.2643380868174727,
+      "sample_count": 124
+    },
+    "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+    "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+    "init_scope": "runtime_init_plus_standalone_shared_preprocess_support_once_per_validation_shard_process_device_operator",
+    "resident_multi_shape_cache_benchmarked": false,
+    "schema": "loom-public-runtime-lifecycle-summary-v1",
+    "shape_count": 124,
+    "validation_shard_count": 4
+  },
+  "semantic_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
+  "shape_count": 124,
+  "status": "passed",
+  "status_scope": "full_correctness_and_evidence_plus_declared_publication_performance_floor",
+  "timing_backend": "cupti",
+  "validation_shard_count": 4
+}
diff --git a/cake_exports/kmeans/VALIDATION.md b/cake_exports/kmeans/VALIDATION.md
new file mode 100644
index 00000000..3a0fc81d
--- /dev/null
+++ b/cake_exports/kmeans/VALIDATION.md
@@ -0,0 +1,41 @@
+## Pre-publication GPU validation: PASS — declared 124-shape performance floor
+
+- Hardware: `NVIDIA GB200` (`sm_100a`)
+- Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
+- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+
+#### Hot steady-state synchronized E2E speedup
+
+| Validated shape scope | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+
+#### Modeled after-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
+| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
+| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
+| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+
+#### Modeled including-init amortized synchronized E2E speedup
+
+| Public calls N | Min | Geomean | Median | P90 | Max |
+| --- | ---: | ---: | ---: | ---: | ---: |
+| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
+| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
+| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
+| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+
+- All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
+- `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
+- `Including-init amortized(N) = (init + first_compute + (N-1) * hot_median) / N`; it includes init. Each latency formula is evaluated separately for baseline and candidate, then reported as `baseline/candidate`. Both amortized scenarios are composed from measured components, not a directly timed N-call loop. A lane without explicit init uses `I=0`.
+- Init scope: `runtime_init_plus_standalone_shared_preprocess_support_once_per_validation_shard_process_device_operator`; composition: `runtime_init_plus_shared_preprocess_support_each_standalone_lane`; baseline has explicit init: `yes`.
+- Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
+- Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
+
+- Measured: `2026-07-08T23:29:04+00:00`
+- Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
diff --git a/cake_exports/kmeans/benchmarks/all_expected_routes.json b/cake_exports/kmeans/benchmarks/all_expected_routes.json
new file mode 100644
index 00000000..11ab68fa
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/all_expected_routes.json
@@ -0,0 +1,1142 @@
+[
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d895_expanded_heldout_neighborhood_d80_b2_n2176_k1024_d80"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "d895_expanded_guard_miss_fallback_d128_b1_n1408_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "d895_expanded_forced_fallback_d128_b1_n1664_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "d895_expanded_guard_boundary_d144_b1_n128_k256_d144"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "d895_expanded_tail_divisibility_d176_b1_n1152_k512_d176"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1:launch_for_eval",
+    "selected_route": "d192_paired_repeated_mma_v1",
+    "shape": "d895_expanded_guard_overlap_d192_b1_n1024_k768_d192"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_highd_splitd_6fcf_v1:launch_for_eval",
+    "selected_route": "highd_splitd_single_tile_6fcf_v1",
+    "shape": "d895_expanded_random_legal_d320_b1_n1280_k512_d320"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_highd_splitd_6fcf_v1:launch_for_eval",
+    "selected_route": "highd_splitd_single_tile_6fcf_v1",
+    "shape": "d895_expanded_request_specific_d448_b1_n1280_k1024_d448"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1:launch_for_eval",
+    "selected_route": "flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1",
+    "shape": "d895_expanded_request_specific_d512_splitk_b1_n512_k8192_d512"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "d16_paired_b2_n4096_k1024_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "microdim_pad64_d64_direct_v1",
+    "shape": "d16_fallback_b3_n2432_k512_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "microdim_pad64_d64_direct_v1",
+    "shape": "d16_small_b4_n1024_k512_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "d16_large_b8_n32768_k512_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "d32_hugek_b1_n512_k8192_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "d32_paired_b2_n4096_k1024_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "microdim_pad64_d64_direct_v1",
+    "shape": "d32_fallback_b3_n2432_k512_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "microdim_pad64_d64_direct_v1",
+    "shape": "d32_small_b4_n1024_k512_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval",
+    "selected_route": "d64_direct_single64_1p2gap_9f2a_v1",
+    "shape": "d64_paired_b2_n4096_k1024_d64"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval",
+    "selected_route": "d64_direct_single64_1p2gap_9f2a_v1",
+    "shape": "d64_fallback_b3_n2432_k512_d64"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval",
+    "selected_route": "d64_direct_single64_1p2gap_9f2a_v1",
+    "shape": "d64_small_b4_n1024_k512_d64"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval",
+    "selected_route": "d64_direct_single64_1p2gap_9f2a_v1",
+    "shape": "d64_large_b8_n32768_k512_d64"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d80_paired_b1_n2048_k1024_d80"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d80_small_b2_n1024_k512_d80"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d96_paired_b1_n1536_k1024_d96"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d96_small_b2_n896_k512_d96"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d96_random_b3_n6144_k1280_d96"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval",
+    "selected_route": "lowdim_e50c_v1",
+    "shape": "d96_fallback_b5_n1664_k256_d96"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "boundary_b1_n128_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_tiny_hugek_b1_n128_k4096_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_b1_n256_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_min_even_b1_n256_k768_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_low_n_hugek_b1_n256_k4096_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_b1_n896_k512_d128"
+  },
+  {
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+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_odd_kover_b1_n896_k768_d128"
+  },
+  {
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+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_hugek_b1_n896_k16384_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "boundary_b1_n1024_k768_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_kover_b1_n1024_k2048_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "forced_fallback_b1_n1152_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_first_after_small_b1_n1152_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "boundary_b1_n1280_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_even_b1_n1536_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d128_splitk_priority_575c_v1:launch_for_eval",
+    "selected_route": "d128_splitk_priority_575c_v1",
+    "shape": "paired_largek_b1_n2048_k4096_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_odd_b1_n2176_k4096_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "tail_odd_b1_n4224_k1024_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_large_odd_b1_n8320_k1280_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_large_b1_n65536_k4096_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_large_n_b1_n131072_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_kover_b2_n256_k768_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_low_n_hugek_b2_n384_k8192_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_even_b2_n512_k8192_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_random_b2_n768_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "random_b2_n768_k3072_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "smoke_b2_n1024_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_first_odd_b2_n1408_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_even_tail_b2_n1792_k256_d128"
+  },
+  {
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+    "selected_route": "paired_large_v15",
+    "shape": "tail_even_b2_n2048_k2048_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "random_legal_b2_n4736_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_large_b2_n65664_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_low_b3_n256_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_first_even_b3_n1536_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_mid_odd_b3_n2432_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "random_legal_b3_n2560_k1536_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "random_b3_n6144_k1280_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_b4_n128_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "random_legal_b4_n640_k1024_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "boundary_b4_n1024_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "fallback_odd_b4_n1664_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "paired_widek_b4_n3072_k3072_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "random_legal_b5_n512_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "random_b5_n3456_k512_d128"
+  },
+  {
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+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_cap_b6_n1024_k256_d128"
+  },
+  {
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+    "selected_route": "paired_large_v15",
+    "shape": "paired_large_b6_n65536_k512_d128"
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+  {
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+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_boundary_b7_n896_k256_d128"
+  },
+  {
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+    "selected_route": "paired_large_v15",
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+    "shape": "fallback_b8_n3712_k2048_d128"
+  },
+  {
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+    "selected_route": "paired_large_v15",
+    "shape": "paired_b8_n4096_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "mid_b8_n8192_k512_d128"
+  },
+  {
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+    "selected_route": "paired_large_v15",
+    "shape": "random_legal_b9_n3840_k1792_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "small_grid_single_tile_v10",
+    "shape": "small_b12_n640_k256_d128"
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+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d480_b4_n8192_k1024_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d480_boundary_b5_n2048_k512_d480"
+  }
+]
diff --git a/cake_exports/kmeans/benchmarks/benchmark.py b/cake_exports/kmeans/benchmarks/benchmark.py
new file mode 100644
index 00000000..1baf0f47
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/benchmark.py
@@ -0,0 +1,1645 @@
+from __future__ import annotations
+
+import argparse
+import hashlib
+import json
+import math
+import os
+import sys
+import uuid
+from pathlib import Path
+from typing import Any
+
+ROOT = Path(__file__).resolve().parents[1]
+SRC = ROOT / "src"
+if str(SRC) not in sys.path:
+    sys.path.insert(0, str(SRC))
+
+from flash_kmeans_shapes import (  # noqa: E402
+    FLASH_KMEANS_EVOLUTION_ARTIFACT,
+    FLASH_KMEANS_EVOLUTION_SUMMARY,
+)
+from flash_kmeans_triton_h200 import euclid_assign_triton_h200  # noqa: E402
+from flash_kmeans_triton_h200_raw_adapter import (  # noqa: E402
+    BASELINE_COMMIT,
+    PREPROCESS_IMPL,
+    TritonH20007cfRawAdapter,
+)
+from flash_kmeans_triton_h200_raw_adapter import (  # noqa: E402
+    BASELINE_NAME as PUBLIC_RAW_BASELINE_NAME,
+)
+from flashlib_cake_kmeans._benchmark import (  # noqa: E402
+    BenchResult,
+    HostCallTiming,
+    bench_gpu_time,
+    compare_runtime_lifecycles,
+    measure_host_call,
+    require_cupti,
+    runtime_lifecycle_metrics,
+)
+
+
+def _sum_host_timings(*timings: HostCallTiming) -> HostCallTiming:
+    """Compose sequential one-time setup costs for standalone-lane modeling."""
+
+    if not timings:
+        raise ValueError("at least one host timing is required")
+    return HostCallTiming(
+        host_enqueue_ms=sum(float(timing.host_enqueue_ms) for timing in timings),
+        synchronized_e2e_ms=sum(float(timing.synchronized_e2e_ms) for timing in timings),
+    )
+
+
+SHAPE_RECORDS = json.loads((Path(__file__).with_name("shape_records.json")).read_text(encoding="utf-8"))
+ROUTE_MANIFEST = json.loads((Path(__file__).with_name("expected_routes.json")).read_text(encoding="utf-8"))
+ALL_ROUTE_MANIFEST = json.loads((Path(__file__).with_name("all_expected_routes.json")).read_text(encoding="utf-8"))
+EXPECTED_ROUTES = {row["shape"]: row["selected_route"] for row in ALL_ROUTE_MANIFEST}
+
+
+def _shape_from_record(record: dict[str, Any]) -> dict[str, Any]:
+    params = dict(record["params"])
+    recorded = dict(record.get("recorded", {}))
+    row = {"label": record["label"], **params}
+    row["runtime_coverage"] = bool(record.get("runtime_coverage", False))
+    row["route"] = recorded.get("evolution_route", params.get("route"))
+    for key in (
+        "evolution_kernel_ms",
+        "evolution_flashlib_ms",
+        "evolution_tflops",
+        "evolution_flashlib_equiv_tflops",
+        "evolution_speedup",
+    ):
+        row[key] = recorded.get(key, params.get(key))
+    return row
+
+
+FLASH_KMEANS_SHAPES = [_shape_from_record(record) for record in SHAPE_RECORDS]
+_SHAPES_BY_LABEL = {row["label"]: row for row in FLASH_KMEANS_SHAPES}
+FLASH_KMEANS_REGISTRY_SHAPES = [_SHAPES_BY_LABEL[route["shape"]] for route in ROUTE_MANIFEST]
+SEMANTIC_ENTRYPOINT = "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval"
+PRECOMPUTED_BASELINE_NAME = "triton_h200_07cf_precomputed"
+BASELINE_REGISTRY_KEY = "triton_h200_07cf_dual_lane_v1"
+# Updated together with benchmark_data.json by the registry sync gate.
+BASELINE_REGISTRY_SHA256 = "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c"
+REGISTRY_CANDIDATE_ENTRYPOINT = SEMANTIC_ENTRYPOINT
+MEASURED_CANDIDATE_ENTRYPOINT = "flashlib_cake_kmeans.interface:FlashKMeansAssignRuntime.compute"
+BASELINE_ENTRYPOINT = "benchmarks.flash_kmeans_triton_h200_raw_adapter:TritonH20007cfRawAdapter.compute"
+PARITY_CANDIDATE_ENTRYPOINT = "flashlib_cake_kmeans.interface:flash_kmeans_assign_prepared"
+PARITY_BASELINE_ENTRYPOINT = "benchmarks.flash_kmeans_triton_h200:euclid_assign_triton_h200"
+REGISTRY_CANDIDATE_TIMING_BOUNDARY = (
+    "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
+)
+CANDIDATE_TIMING_BOUNDARY = (
+    "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
+)
+BASELINE_TIMING_BOUNDARY = "raw_inputs_default_output_shared_fused_pair_norm_plus_pinned_07cf_assign_synchronized_e2e"
+PARITY_CANDIDATE_TIMING_BOUNDARY = "precomputed_norms_preallocated_output_prepared_assignment_gpu_span"
+PARITY_BASELINE_TIMING_BOUNDARY = "precomputed_norms_preallocated_output_pinned_07cf_assignment_gpu_span"
+BASELINE_REGISTRY_PROFILE = {
+    "registry_candidate_entrypoint": REGISTRY_CANDIDATE_ENTRYPOINT,
+    "shared_preprocess": {
+        "implementation_entrypoint": PREPROCESS_IMPL,
+        "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "result_source_sha256_field": "preprocess_source_sha256",
+    },
+    "official": {
+        "role": "publication",
+        "candidate_entrypoint": MEASURED_CANDIDATE_ENTRYPOINT,
+        "baseline_name": PUBLIC_RAW_BASELINE_NAME,
+        "baseline_commit": BASELINE_COMMIT,
+        "baseline_entrypoint": BASELINE_ENTRYPOINT,
+        # This digest-bound identity belongs to the frozen benchmark registry.
+        # The live raw payload carries the request-owned official boundary.
+        "candidate_timing_boundary": REGISTRY_CANDIDATE_TIMING_BOUNDARY,
+        "baseline_timing_boundary": BASELINE_TIMING_BOUNDARY,
+        "candidate_timing_backend_field": "candidate_public_raw_timing_backend",
+        "baseline_timing_backend_field": "baseline_07cf_adapter_timing_backend",
+        "speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+        "speedup_numerator_metric": "baseline_07cf_adapter_synchronized_e2e_ms",
+        "speedup_denominator_metric": "candidate_public_raw_synchronized_e2e_ms",
+        "timing_backend": "cupti",
+    },
+    "parity": {
+        "role": "diagnostic_only",
+        "candidate_entrypoint": PARITY_CANDIDATE_ENTRYPOINT,
+        "baseline_name": PRECOMPUTED_BASELINE_NAME,
+        "baseline_commit": BASELINE_COMMIT,
+        "baseline_entrypoint": PARITY_BASELINE_ENTRYPOINT,
+        "candidate_timing_boundary": PARITY_CANDIDATE_TIMING_BOUNDARY,
+        "baseline_timing_boundary": PARITY_BASELINE_TIMING_BOUNDARY,
+        "candidate_timing_backend_field": "candidate_precomputed_timing_backend",
+        "baseline_timing_backend_field": "baseline_07cf_precomputed_timing_backend",
+        "speedup_metric": "precomputed_gpu_speedup_vs_07cf",
+        "speedup_numerator_metric": "baseline_07cf_precomputed_gpu_span_ms",
+        "speedup_denominator_metric": "candidate_precomputed_gpu_span_ms",
+        "timing_backend": "cupti",
+    },
+}
+WARMUP_MS = 20.0
+BENCH_MS = 100.0
+DEFAULT_MEASUREMENT_ORDER_SEED = "flashlib-kmeans-export-paired-replay-v1"
+MEASUREMENT_ROLES = (
+    "candidate_public_raw",
+    "baseline_public_raw",
+    "candidate_precomputed",
+    "baseline_precomputed",
+)
+
+
+def _preprocess_source_digest() -> str:
+    """Hash the exact Python/CUDA pair-row-norm implementation in this export."""
+
+    source_dir = Path(__file__).resolve().parent
+    candidates = (
+        (
+            ROOT / "src/flashlib_cake_kmeans/_row_norm.py",
+            ROOT / "src/flashlib_cake_kmeans/_row_norm.cu",
+        ),
+        (source_dir / "row_norm.py", source_dir / "row_norm.cu"),
+    )
+    for paths in candidates:
+        if all(path.is_file() for path in paths):
+            digest = hashlib.sha256()
+            for canonical_name, path in zip(("_row_norm.py", "_row_norm.cu"), paths, strict=True):
+                digest.update(canonical_name.encode("utf-8"))
+                digest.update(b"\0")
+                digest.update(path.read_bytes())
+                digest.update(b"\0")
+            return digest.hexdigest()
+    searched = ", ".join(str(path) for pair in candidates for path in pair)
+    raise RuntimeError(f"cannot locate exported pair-row-norm sources; searched {searched}")
+
+
+def _timing_diagnostics(timing: Any, *, primary_metric: str) -> dict[str, Any]:
+    return {
+        "lane_primary_metric": primary_metric,
+        # KMeans uses an adaptive 100 ms window that can contain thousands of
+        # iterations. The generated BenchResult retains every exact sample;
+        # the publication JSON records medians and sample count to avoid
+        # multiplying artifact size across the 228-shape portfolio.
+        "sample_count": len(timing.times_ms),
+        "gpu_span_ms": {"median": timing.median_gpu_span_ms},
+        "kernel_sum_ms": {"median": timing.median_kernel_sum_ms},
+        "active_union_ms": {"median": timing.median_active_union_ms},
+        "inter_kernel_gap_ms": {"median": timing.median_inter_kernel_gap_ms},
+        "activity_count": {"median": timing.median_activity_count},
+        "correlated_launch_activity_count": {"median": timing.median_launch_activity_count},
+        "correlated_kernel_activity_count": {"median": timing.median_kernel_activity_count},
+        "submission_ms": {"median": timing.median_submission_ms},
+        "host_enqueue_ms": {"median": timing.median_host_enqueue_ms},
+        "synchronized_e2e_ms": {"median": timing.median_synchronized_e2e_ms},
+        "cold_first_call": {
+            "host_enqueue_ms": timing.cold_first_call_host_enqueue_ms,
+            "synchronized_e2e_ms": timing.cold_first_call_synchronized_e2e_ms,
+        },
+    }
+
+
+def _pair_order(
+    label: str,
+    pair_name: str,
+    pair_index: int,
+    order_seed: str,
+) -> tuple[str, str]:
+    pairs = {
+        "public": ("candidate_public_raw", "baseline_public_raw"),
+        "precomputed": ("candidate_precomputed", "baseline_precomputed"),
+    }
+    pair = pairs[pair_name]
+    digest = hashlib.sha256(
+        f"{order_seed}:{label}:{pair_name}:{pair_index}".encode()
+    ).digest()
+    return pair if digest[0] & 1 else tuple(reversed(pair))
+
+
+def _interleaved_pair_schedule(
+    label: str,
+    *,
+    public_pair_count: int,
+    precomputed_pair_count: int,
+    order_seed: str,
+) -> tuple[str, ...]:
+    """Build balanced adjacent A/B pairs for one shared CUPTI session."""
+
+    if not isinstance(order_seed, str) or not order_seed:
+        raise ValueError("measurement order seed must be a non-empty string")
+    if public_pair_count <= 0 or precomputed_pair_count <= 0:
+        raise ValueError("interleaved pair counts must be positive")
+    pair_slots = [
+        ((index + 0.5) / public_pair_count, "public", index)
+        for index in range(public_pair_count)
+    ]
+    pair_slots.extend(
+        ((index + 0.5) / precomputed_pair_count, "precomputed", index)
+        for index in range(precomputed_pair_count)
+    )
+    pair_slots.sort(
+        key=lambda item: (
+            item[0],
+            hashlib.sha256(
+                f"{order_seed}:{label}:pair-slot:{item[1]}:{item[2]}".encode()
+            ).digest(),
+        )
+    )
+    schedule: list[str] = []
+    for _position, pair_name, pair_index in pair_slots:
+        schedule.extend(_pair_order(label, pair_name, pair_index, order_seed))
+    counts = {role: schedule.count(role) for role in MEASUREMENT_ROLES}
+    expected = {
+        "candidate_public_raw": public_pair_count,
+        "baseline_public_raw": public_pair_count,
+        "candidate_precomputed": precomputed_pair_count,
+        "baseline_precomputed": precomputed_pair_count,
+    }
+    if counts != expected:
+        raise RuntimeError(f"interleaved role schedule is incomplete: {counts!r} != {expected!r}")
+    return tuple(schedule)
+
+
+def _slice_bench_result(
+    result: BenchResult,
+    indices: list[int],
+    *,
+    cold_first_call: HostCallTiming | None,
+) -> BenchResult:
+    if not indices:
+        raise ValueError("each paired role requires at least one reportable sample")
+
+    def select(values):
+        if values is None:
+            return None
+        if len(values) != len(result.times_ms):
+            raise RuntimeError("shared CUPTI result fields have inconsistent sample counts")
+        return [values[index] for index in indices]
+
+    return BenchResult(
+        times_ms=select(result.times_ms),
+        backend=result.backend,
+        kernel_sum_times_ms=select(result.kernel_sum_times_ms),
+        inter_kernel_gap_times_ms=select(result.inter_kernel_gap_times_ms),
+        active_union_times_ms=select(result.active_union_times_ms),
+        activity_counts=select(result.activity_counts),
+        launch_activity_counts=select(result.launch_activity_counts),
+        kernel_activity_counts=select(result.kernel_activity_counts),
+        submission_times_ms=select(result.submission_times_ms),
+        synchronized_e2e_times_ms=select(result.synchronized_e2e_times_ms),
+        cold_first_call_host_enqueue_ms=(
+            cold_first_call.host_enqueue_ms if cold_first_call is not None else None
+        ),
+        cold_first_call_synchronized_e2e_ms=(
+            cold_first_call.synchronized_e2e_ms if cold_first_call is not None else None
+        ),
+    )
+
+
+def _bench_interleaved_roles(
+    *,
+    label: str,
+    order_seed: str,
+    role_factories: dict[str, Any],
+    cold_first_calls: dict[str, HostCallTiming | None],
+) -> tuple[dict[str, BenchResult], dict[str, Any]]:
+    """Measure all reportable roles in one interleaved CUPTI activity session."""
+
+    if tuple(role_factories) != MEASUREMENT_ROLES:
+        raise ValueError("paired benchmark role factories are incomplete or out of order")
+    probes: dict[str, BenchResult] = {}
+    for role in MEASUREMENT_ROLES:
+        probes[role] = bench_gpu_time(
+            role_factories[role](),
+            warmup_iters=5,
+            bench_iters=20,
+            cold_l2=True,
+        )
+    estimates = {role: float(probes[role].median_ms) for role in MEASUREMENT_ROLES}
+    if any(not math.isfinite(value) or value <= 0.0 for value in estimates.values()):
+        raise RuntimeError(f"paired benchmark probes produced invalid estimates: {estimates!r}")
+
+    public_bench_pairs = max(
+        8,
+        math.ceil(BENCH_MS / estimates["candidate_public_raw"]),
+        math.ceil(BENCH_MS / estimates["baseline_public_raw"]),
+    )
+    precomputed_bench_pairs = max(
+        8,
+        math.ceil(BENCH_MS / estimates["candidate_precomputed"]),
+        math.ceil(BENCH_MS / estimates["baseline_precomputed"]),
+    )
+    public_warmup_pairs = max(
+        1,
+        math.ceil(WARMUP_MS / estimates["candidate_public_raw"]),
+        math.ceil(WARMUP_MS / estimates["baseline_public_raw"]),
+    )
+    precomputed_warmup_pairs = max(
+        1,
+        math.ceil(WARMUP_MS / estimates["candidate_precomputed"]),
+        math.ceil(WARMUP_MS / estimates["baseline_precomputed"]),
+    )
+    warmup_schedule = _interleaved_pair_schedule(
+        label,
+        public_pair_count=public_warmup_pairs,
+        precomputed_pair_count=precomputed_warmup_pairs,
+        order_seed=f"{order_seed}:warmup",
+    )
+    measurement_schedule = _interleaved_pair_schedule(
+        label,
+        public_pair_count=public_bench_pairs,
+        precomputed_pair_count=precomputed_bench_pairs,
+        order_seed=order_seed,
+    )
+    combined_schedule = (*warmup_schedule, *measurement_schedule)
+    role_callables = {role: role_factories[role]() for role in MEASUREMENT_ROLES}
+    next_index = 0
+
+    def invoke_scheduled_role():
+        nonlocal next_index
+        role = combined_schedule[next_index]
+        next_index += 1
+        return role_callables[role]()
+
+    shared = bench_gpu_time(
+        invoke_scheduled_role,
+        warmup_iters=len(warmup_schedule),
+        bench_iters=len(measurement_schedule),
+        cold_l2=True,
+    )
+    if next_index != len(combined_schedule):
+        raise RuntimeError("paired benchmark did not consume its complete role schedule")
+    timings: dict[str, BenchResult] = {}
+    sample_counts: dict[str, int] = {}
+    for role in MEASUREMENT_ROLES:
+        indices = [index for index, scheduled_role in enumerate(measurement_schedule) if scheduled_role == role]
+        timings[role] = _slice_bench_result(
+            shared,
+            indices,
+            cold_first_call=cold_first_calls.get(role),
+        )
+        sample_counts[role] = len(indices)
+
+    schedule_text = "\n".join(measurement_schedule).encode()
+    provenance = {
+        "schema": "flash-kmeans-interleaved-cupti-session-v1",
+        "same_cupti_session": True,
+        "interleaved": True,
+        "adjacent_candidate_baseline_pairs": True,
+        "reportable_cupti_session_count": 1,
+        "adaptive_probe_cupti_session_count": len(MEASUREMENT_ROLES),
+        "adaptive_probes_reportable": False,
+        "order_seed": order_seed,
+        "measurement_schedule_sha256": hashlib.sha256(schedule_text).hexdigest(),
+        "measurement_schedule_iteration_count": len(measurement_schedule),
+        "warmup_schedule_iteration_count": len(warmup_schedule),
+        "role_sample_counts": sample_counts,
+        "public_pair_count": public_bench_pairs,
+        "precomputed_pair_count": precomputed_bench_pairs,
+        "first_reportable_roles": list(measurement_schedule[:16]),
+    }
+    return timings, provenance
+
+
+def _label_seed(label: str) -> int:
+    digest = hashlib.sha256(label.encode("utf-8")).digest()
+    return int.from_bytes(digest[:8], "little") % (2**31)
+
+
+_REGISTRY_COLD_LABELS = frozenset(row["label"] for row in FLASH_KMEANS_REGISTRY_SHAPES)
+_CANDIDATE_FIRST_COLD_LABELS_BY_SEED: dict[str, frozenset[str]] = {}
+
+
+def _candidate_first_cold_labels(order_seed: str) -> frozenset[str]:
+    cached = _CANDIDATE_FIRST_COLD_LABELS_BY_SEED.get(order_seed)
+    if cached is None:
+        ordered = sorted(
+            (row["label"] for row in FLASH_KMEANS_REGISTRY_SHAPES),
+            key=lambda label: hashlib.sha256(f"{order_seed}:cold:{label}".encode()).digest(),
+        )
+        cached = frozenset(ordered[::2])
+        _CANDIDATE_FIRST_COLD_LABELS_BY_SEED[order_seed] = cached
+    return cached
+
+
+def _cold_measurement_order(label: str, order_seed: str) -> tuple[str, str]:
+    """Counterbalance process-shared cold effects across contract shapes.
+
+    Rank-alternate over the seeded hash order of the full contract portfolio
+    so the split is exactly balanced (|candidate_first - baseline_first| <= 1)
+    for every shard decomposition, matching the declared
+    ``deterministic_balanced_per_publication_contract_portfolio`` policy.
+    """
+
+    if label in _REGISTRY_COLD_LABELS:
+        first_candidate = label in _candidate_first_cold_labels(order_seed)
+    else:
+        # Runtime-coverage diagnostic rows sit outside the publication
+        # contract balance gate; keep the per-label seeded coin flip.
+        digest = hashlib.sha256(f"{order_seed}:cold:{label}".encode()).digest()
+        first_candidate = bool(digest[0] & 1)
+    return ("candidate", "baseline") if first_candidate else ("baseline", "candidate")
+
+
+def _alternating_call(first, second):
+    """Return a callable that alternates two equivalent fresh-pointer cases."""
+
+    calls = (first, second)
+    next_index = 0
+
+    def invoke():
+        nonlocal next_index
+        current = next_index
+        next_index ^= 1
+        return calls[current]()
+
+    return invoke
+
+
+def _required_median(value: float | None, *, metric: str) -> float:
+    if value is None:
+        raise RuntimeError(f"CUPTI benchmark did not report required {metric}")
+    return float(value)
+
+
+def _dual_lane_speedups(
+    *,
+    candidate_public_raw_timing: Any,
+    baseline_public_raw_timing: Any,
+    candidate_precomputed_timing: Any,
+    baseline_precomputed_timing: Any,
+) -> dict[str, float]:
+    """Return the one official E2E ratio and the precomputed GPU parity ratio."""
+
+    candidate_public_raw_e2e = _required_median(
+        candidate_public_raw_timing.median_synchronized_e2e_ms,
+        metric="candidate public-raw synchronized_e2e_ms",
+    )
+    baseline_public_raw_e2e = _required_median(
+        baseline_public_raw_timing.median_synchronized_e2e_ms,
+        metric="07cf raw-adapter synchronized_e2e_ms",
+    )
+    return {
+        "public_raw_e2e_speedup_vs_07cf_adapter": baseline_public_raw_e2e / candidate_public_raw_e2e,
+        "precomputed_gpu_speedup_vs_07cf": (
+            float(baseline_precomputed_timing.median_gpu_span_ms)
+            / float(candidate_precomputed_timing.median_gpu_span_ms)
+        ),
+    }
+
+
+def _public_prepared_ratios(public_timing: Any, prepared_timing: Any) -> dict[str, float]:
+    """Return public/prepared ratios from one per-shape measurement session."""
+
+    public_submission = _required_median(
+        public_timing.median_submission_ms,
+        metric="public submission_ms",
+    )
+    prepared_submission = _required_median(
+        prepared_timing.median_submission_ms,
+        metric="prepared submission_ms",
+    )
+    public_e2e = _required_median(
+        public_timing.median_synchronized_e2e_ms,
+        metric="public synchronized_e2e_ms",
+    )
+    prepared_e2e = _required_median(
+        prepared_timing.median_synchronized_e2e_ms,
+        metric="prepared synchronized_e2e_ms",
+    )
+    denominators = {
+        "gpu_span_ms": float(prepared_timing.median_gpu_span_ms),
+        "submission_ms": prepared_submission,
+        "synchronized_e2e_ms": prepared_e2e,
+    }
+    if any(value <= 0.0 for value in denominators.values()):
+        raise RuntimeError(f"prepared timing ratios require positive denominators, got {denominators!r}")
+    return {
+        "gpu_span": float(public_timing.median_gpu_span_ms) / denominators["gpu_span_ms"],
+        "submission": public_submission / denominators["submission_ms"],
+        "synchronized_e2e": public_e2e / denominators["synchronized_e2e_ms"],
+    }
+
+
+def _cold_call_fields(timing: Any | None) -> dict[str, float | None]:
+    return {
+        "submission_ms": timing.host_enqueue_ms if timing is not None else None,
+        "host_enqueue_ms": timing.host_enqueue_ms if timing is not None else None,
+        "synchronized_e2e_ms": timing.synchronized_e2e_ms if timing is not None else None,
+    }
+
+
+def _shape_key(row: dict[str, Any]) -> tuple[int, int, int, int, str]:
+    return (
+        int(row["B"]),
+        int(row["N"]),
+        int(row["D"]),
+        int(row["K"]),
+        str(row.get("dtype", "bfloat16")),
+    )
+
+
+def _selected_rows(args: argparse.Namespace) -> list[dict[str, Any]]:
+    rows = list(FLASH_KMEANS_SHAPES if args.include_runtime_coverage else FLASH_KMEANS_REGISTRY_SHAPES)
+    if args.source:
+        wanted_sources = set(args.source)
+        rows = [row for row in rows if row["source"] in wanted_sources]
+    if args.shape:
+        by_label = {row["label"]: row for row in rows}
+        missing = sorted(set(args.shape) - set(by_label))
+        if missing:
+            available = ", ".join(sorted(by_label))
+            raise SystemExit(f"unknown shape label(s) {missing}. Available: {available}")
+        rows = [by_label[label] for label in args.shape]
+    if args.unique:
+        seen: set[tuple[int, int, int, int, str]] = set()
+        unique_rows: list[dict[str, Any]] = []
+        for row in rows:
+            key = _shape_key(row)
+            if key in seen:
+                continue
+            seen.add(key)
+            unique_rows.append(row)
+        rows = unique_rows
+    if args.limit is not None:
+        rows = rows[: args.limit]
+    rows = rows[args.shard_index :: args.shard_count]
+    return rows
+
+
+def _write_json_atomic(path: Path, text: str) -> None:
+    temporary = path.with_name(f".{path.name}.{os.getpid()}.tmp")
+    temporary.write_text(text + "\n", encoding="utf-8")
+    temporary.replace(path)
+
+
+def _make_inputs(row: dict[str, Any], *, variant: int = 0):
+    import torch
+
+    generator = torch.Generator(device="cuda")
+    seed = int(row.get("seed", _label_seed(str(row["label"]))))
+    if variant != 0:
+        seed = _label_seed(f"{row['label']}:fresh-pointer:{variant}:{seed}")
+    generator.manual_seed(seed)
+    x = torch.randn(
+        (int(row["B"]), int(row["N"]), int(row["D"])),
+        dtype=torch.bfloat16,
+        device="cuda",
+        generator=generator,
+    ).contiguous()
+    centroids = torch.randn(
+        (int(row["B"]), int(row["K"]), int(row["D"])),
+        dtype=torch.bfloat16,
+        device="cuda",
+        generator=generator,
+    ).contiguous()
+    return x, centroids
+
+
+def _measure_shared_preprocess_cold_compile(row: dict[str, Any], *, arch: str):
+    """Compile the shared row-norm support once, outside either comparison lane."""
+
+    import torch
+    from flashlib_cake_kmeans._row_norm import prepare_bf16_pair_row_norm
+
+    x, centroids = _make_inputs(row, variant=0xC01D)
+    x_sq = torch.empty((int(row["B"]), int(row["N"])), dtype=torch.float32, device=x.device)
+    c_sq = torch.empty((int(row["B"]), int(row["K"])), dtype=torch.float32, device=x.device)
+    # Fixture generation is asynchronous. Complete it before the cold bracket
+    # so neither lane inherits unrelated random-generation/allocation work.
+    torch.cuda.synchronize()
+
+    def prepare_shared_support():
+        prepared = prepare_bf16_pair_row_norm(
+            x,
+            centroids,
+            x_sq,
+            c_sq,
+            compute_x=True,
+            compute_c=True,
+            arch=arch,
+        )
+        prepared.release_bound_callers(x_sq)
+
+    _, cold_compile = measure_host_call(prepare_shared_support)
+    return cold_compile
+
+
+def _reference_assign(x, centroids, *, chunk_rows: int):
+    import torch
+
+    bsz = int(x.shape[0])
+    n_points = int(x.shape[1])
+    x_f32 = x.float()
+    c_f32 = centroids.float()
+    c_sq = (c_f32 * c_f32).sum(-1)
+    ref = torch.empty((bsz, n_points), dtype=torch.int32, device=x.device)
+    with torch.no_grad():
+        for b in range(bsz):
+            c_t = c_f32[b].transpose(0, 1).contiguous()
+            c_bias = 0.5 * c_sq[b]
+            for start in range(0, n_points, chunk_rows):
+                q = x_f32[b, start : start + chunk_rows]
+                scores = torch.matmul(q, c_t) - c_bias.unsqueeze(0)
+                ref[b, start : start + q.shape[0]] = scores.argmax(dim=-1).to(torch.int32)
+    return ref
+
+
+def _assignment_correctness(cluster_ids, ref, x, centroids) -> dict[str, Any]:
+    """Validate assignment indices while accepting exact-distance ties."""
+
+    import torch
+
+    matches = cluster_ids == ref
+    mismatch_count = int((~matches).sum().item())
+    diagnostics: dict[str, Any] = {
+        "match_rate": float(matches.float().mean().item()),
+        "mismatch_count": mismatch_count,
+    }
+    if mismatch_count == 0:
+        diagnostics.update({"correct": True, "tie_inclusive": False})
+        return diagnostics
+
+    dim = int(x.shape[-1])
+    pred_idx = cluster_ids.to(torch.int64).unsqueeze(-1).expand(-1, -1, dim)
+    ref_idx = ref.to(torch.int64).unsqueeze(-1).expand(-1, -1, dim)
+    pred_centroids = torch.gather(centroids, 1, pred_idx).float()
+    ref_centroids = torch.gather(centroids, 1, ref_idx).float()
+    points = x.float()
+    pred_dist = ((points - pred_centroids) ** 2).sum(-1)
+    ref_dist = ((points - ref_centroids) ** 2).sum(-1)
+    distance_delta = (pred_dist - ref_dist).abs()
+    tie_ok = matches | (distance_delta <= 1.0e-3)
+    diagnostics.update(
+        {
+            "correct": bool(tie_ok.all().item()),
+            "tie_inclusive": True,
+            "tie_inclusive_match_rate": float(tie_ok.float().mean().item()),
+            "max_selected_distance_delta": float(distance_delta.max().item()),
+        }
+    )
+    return diagnostics
+
+
+def _run_shape(
+    row: dict[str, Any],
+    *,
+    runtime: Any,
+    baseline_adapter: Any,
+    candidate_init_timing: Any = None,
+    baseline_init_timing: Any = None,
+    arch: str | None,
+    correctness: bool,
+    benchmark: bool,
+    reference_chunk_rows: int,
+    measurement_session_id: str,
+    measurement_order_seed: str,
+) -> dict[str, Any]:
+    import torch
+    from flashlib_cake_kmeans import (
+        flash_kmeans_assign_prepared,
+        prepare_flash_kmeans_assign,
+    )
+
+    x, centroids = _make_inputs(row, variant=0)
+    fresh_x, fresh_centroids = _make_inputs(row, variant=1)
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    fresh_x_sq = (fresh_x.float() ** 2).sum(-1).contiguous()
+    fresh_c_sq = (fresh_centroids.float() ** 2).sum(-1).contiguous()
+    out_shape = (int(row["B"]), int(row["N"]))
+    candidate_precomputed_out = torch.empty(out_shape, dtype=torch.int32, device=x.device)
+    fresh_candidate_precomputed_out = torch.empty_like(candidate_precomputed_out)
+    baseline_precomputed_out = torch.empty_like(candidate_precomputed_out)
+    fresh_baseline_precomputed_out = torch.empty_like(candidate_precomputed_out)
+
+    pointer_pairs = (
+        (x, fresh_x),
+        (centroids, fresh_centroids),
+        (x_sq, fresh_x_sq),
+        (c_sq, fresh_c_sq),
+    )
+    if any(first.data_ptr() == second.data_ptr() for first, second in pointer_pairs):
+        raise RuntimeError("fresh-pointer benchmark inputs unexpectedly alias the first input set")
+    # Keep cold diagnostics honest: random input generation, explicit parity
+    # norms, and preallocated parity outputs all precede every measured call.
+    torch.cuda.synchronize()
+
+    def baseline_public_raw_first_call():
+        return baseline_adapter.compute(x, centroids, return_info=True)
+
+    def baseline_public_raw_fresh_pointer_call():
+        return baseline_adapter.compute(fresh_x, fresh_centroids, return_info=True)
+
+    def baseline_precomputed_first_call():
+        return euclid_assign_triton_h200(
+            x,
+            centroids,
+            x_sq,
+            c_sq,
+            out=baseline_precomputed_out,
+        )
+
+    def baseline_precomputed_fresh_pointer_call():
+        return euclid_assign_triton_h200(
+            fresh_x,
+            fresh_centroids,
+            fresh_x_sq,
+            fresh_c_sq,
+            out=fresh_baseline_precomputed_out,
+        )
+
+    def candidate_public_raw_shape_first_call():
+        return runtime.compute(
+            x,
+            centroids,
+            return_info=True,
+        )
+
+    def candidate_public_raw_fresh_pointer_call():
+        return runtime.compute(
+            fresh_x,
+            fresh_centroids,
+            return_info=True,
+        )
+
+    baseline_public_raw_shape_cold_call = None
+    baseline_public_raw_fresh_cold_call = None
+    baseline_precomputed_first_cold_call = None
+    baseline_precomputed_fresh_cold_call = None
+    candidate_public_raw_shape_cold_call = None
+    candidate_public_raw_fresh_cold_call = None
+    candidate_precomputed_prepare_cold_call = None
+    fresh_candidate_precomputed_prepare_cold_call = None
+    candidate_precomputed_first_cold_call = None
+    fresh_candidate_precomputed_first_cold_call = None
+    cold_measurement_order = _cold_measurement_order(
+        str(row["label"]),
+        measurement_order_seed,
+    )
+    if benchmark:
+        for lane in cold_measurement_order:
+            if lane == "baseline":
+                (
+                    (baseline_public_raw_out, baseline_public_raw_shape_info),
+                    baseline_public_raw_shape_cold_call,
+                ) = measure_host_call(baseline_public_raw_first_call)
+            else:
+                (
+                    (candidate_public_raw_out, candidate_public_raw_shape_info),
+                    candidate_public_raw_shape_cold_call,
+                ) = measure_host_call(candidate_public_raw_shape_first_call)
+        for lane in cold_measurement_order:
+            if lane == "baseline":
+                (
+                    (fresh_baseline_public_raw_out, baseline_public_raw_fresh_info),
+                    baseline_public_raw_fresh_cold_call,
+                ) = measure_host_call(baseline_public_raw_fresh_pointer_call)
+            else:
+                (
+                    (fresh_candidate_public_raw_out, candidate_public_raw_info),
+                    candidate_public_raw_fresh_cold_call,
+                ) = measure_host_call(candidate_public_raw_fresh_pointer_call)
+        candidate_prepared, candidate_precomputed_prepare_cold_call = measure_host_call(
+            lambda: prepare_flash_kmeans_assign(
+                x,
+                centroids,
+                out=candidate_precomputed_out,
+                x_sq=x_sq,
+                c_sq=c_sq,
+                arch=arch,
+            )
+        )
+        fresh_candidate_prepared, fresh_candidate_precomputed_prepare_cold_call = measure_host_call(
+            lambda: prepare_flash_kmeans_assign(
+                fresh_x,
+                fresh_centroids,
+                out=fresh_candidate_precomputed_out,
+                x_sq=fresh_x_sq,
+                c_sq=fresh_c_sq,
+                arch=arch,
+            )
+        )
+        (
+            (
+                candidate_precomputed_result,
+                candidate_precomputed_info,
+            ),
+            candidate_precomputed_first_cold_call,
+        ) = measure_host_call(lambda: flash_kmeans_assign_prepared(candidate_prepared, return_info=True))
+        (
+            (
+                fresh_candidate_precomputed_result,
+                fresh_candidate_precomputed_info,
+            ),
+            fresh_candidate_precomputed_first_cold_call,
+        ) = measure_host_call(lambda: flash_kmeans_assign_prepared(fresh_candidate_prepared, return_info=True))
+        (
+            (
+                baseline_precomputed_result,
+                baseline_precomputed_config,
+            ),
+            baseline_precomputed_first_cold_call,
+        ) = measure_host_call(baseline_precomputed_first_call)
+        (
+            (
+                fresh_baseline_precomputed_result,
+                fresh_baseline_precomputed_config,
+            ),
+            baseline_precomputed_fresh_cold_call,
+        ) = measure_host_call(baseline_precomputed_fresh_pointer_call)
+    else:
+        (
+            baseline_public_raw_out,
+            baseline_public_raw_shape_info,
+        ) = baseline_public_raw_first_call()
+        (
+            fresh_baseline_public_raw_out,
+            baseline_public_raw_fresh_info,
+        ) = baseline_public_raw_fresh_pointer_call()
+        candidate_public_raw_out, candidate_public_raw_shape_info = candidate_public_raw_shape_first_call()
+        fresh_candidate_public_raw_out, candidate_public_raw_info = candidate_public_raw_fresh_pointer_call()
+        candidate_prepared = prepare_flash_kmeans_assign(
+            x,
+            centroids,
+            out=candidate_precomputed_out,
+            x_sq=x_sq,
+            c_sq=c_sq,
+            arch=arch,
+        )
+        fresh_candidate_prepared = prepare_flash_kmeans_assign(
+            fresh_x,
+            fresh_centroids,
+            out=fresh_candidate_precomputed_out,
+            x_sq=fresh_x_sq,
+            c_sq=fresh_c_sq,
+            arch=arch,
+        )
+        candidate_precomputed_result, candidate_precomputed_info = flash_kmeans_assign_prepared(
+            candidate_prepared,
+            return_info=True,
+        )
+        fresh_candidate_precomputed_result, fresh_candidate_precomputed_info = flash_kmeans_assign_prepared(
+            fresh_candidate_prepared,
+            return_info=True,
+        )
+        baseline_precomputed_result, baseline_precomputed_config = baseline_precomputed_first_call()
+        fresh_baseline_precomputed_result, fresh_baseline_precomputed_config = baseline_precomputed_fresh_pointer_call()
+        torch.cuda.synchronize()
+
+    baseline_configs = (
+        baseline_public_raw_shape_info["triton_h200_07cf_config"],
+        baseline_public_raw_fresh_info["triton_h200_07cf_config"],
+        baseline_precomputed_config,
+        fresh_baseline_precomputed_config,
+    )
+    if any(config != baseline_configs[0] for config in baseline_configs[1:]):
+        raise RuntimeError("07cf Triton selected different configs across equivalent dual-lane calls")
+    if candidate_public_raw_info["selected_route"] != candidate_public_raw_shape_info["selected_route"]:
+        raise RuntimeError(
+            "runtime shape-first and fresh-pointer calls selected different routes: "
+            f"{candidate_public_raw_shape_info['selected_route']!r} != "
+            f"{candidate_public_raw_info['selected_route']!r}"
+        )
+    if not candidate_public_raw_info["runtime_cache_hit"]:
+        raise RuntimeError("fresh-pointer runtime.compute call did not reuse the shape/stream launch plan")
+    if not baseline_public_raw_fresh_info["runtime_cache_hit"]:
+        raise RuntimeError("fresh-pointer 07cf raw-adapter call did not reuse the shape/stream norm plan")
+    candidate_shape_norm_fields = tuple(candidate_public_raw_shape_info.get("norm_compute_fields", ()))
+    candidate_fresh_norm_fields = tuple(candidate_public_raw_info.get("norm_compute_fields", ()))
+    if candidate_shape_norm_fields != candidate_fresh_norm_fields:
+        raise RuntimeError(
+            "runtime shape-first and fresh-pointer calls computed different norm fields: "
+            f"{candidate_shape_norm_fields!r} != {candidate_fresh_norm_fields!r}"
+        )
+    for prepared_info in (candidate_precomputed_info, fresh_candidate_precomputed_info):
+        if prepared_info["selected_route"] != candidate_public_raw_info["selected_route"]:
+            raise RuntimeError(
+                "public-raw and precomputed Flash-KMeans calls selected different routes: "
+                f"{candidate_public_raw_info['selected_route']!r} != {prepared_info['selected_route']!r}"
+            )
+    if candidate_precomputed_result is not candidate_precomputed_out:
+        raise RuntimeError("prepared candidate did not preserve its first caller-owned output")
+    if fresh_candidate_precomputed_result is not fresh_candidate_precomputed_out:
+        raise RuntimeError("prepared candidate did not preserve its fresh-pointer caller-owned output")
+
+    prepared_direct_launcher = candidate_prepared.launch_plan.direct_launcher
+    fresh_prepared_direct_launcher = fresh_candidate_prepared.launch_plan.direct_launcher
+    prepared_path_proof = {
+        "resolved_direct_launcher": bool(callable(prepared_direct_launcher)),
+        "stable_direct_launcher_tokens": [
+            f"{type(prepared_direct_launcher).__module__}.{type(prepared_direct_launcher).__qualname__}"
+            f"@{id(prepared_direct_launcher):x}",
+            f"{type(fresh_prepared_direct_launcher).__module__}."
+            f"{type(fresh_prepared_direct_launcher).__qualname__}@{id(fresh_prepared_direct_launcher):x}",
+        ],
+        "caller_owned_outputs": True,
+        "scratch_reused": True,
+        "stream_bound": bool(
+            candidate_precomputed_info["stream_handle"] == candidate_prepared.launch_plan.stream_handle
+            and fresh_candidate_precomputed_info["stream_handle"]
+            == fresh_candidate_prepared.launch_plan.stream_handle
+        ),
+        "root_dispatch_traversal_count": 0,
+        "parent_dispatch_traversal_count": 0,
+        "internal_device_wide_synchronization_count": 0,
+        "proof_scope": "prepared_direct_launcher_identity_and_source_invariants",
+    }
+    if not all(
+        prepared_path_proof[key]
+        for key in ("resolved_direct_launcher", "caller_owned_outputs", "scratch_reused", "stream_bound")
+    ):
+        raise RuntimeError(f"prepared candidate hot-path proof failed: {prepared_path_proof!r}")
+
+    candidate_shape_first_was_cache_hit = bool(candidate_public_raw_shape_info["runtime_cache_hit"])
+    baseline_shape_first_was_cache_hit = bool(baseline_public_raw_shape_info["runtime_cache_hit"])
+
+    result: dict[str, Any] = {
+        "shape": row["label"],
+        "label": row["label"],
+        "source": row["source"],
+        "seed": row.get("seed"),
+        "runtime_coverage": bool(row.get("runtime_coverage", False)),
+        "B": int(row["B"]),
+        "N": int(row["N"]),
+        "D": int(row["D"]),
+        "K": int(row["K"]),
+        "dtype": row.get("dtype", "bfloat16"),
+        "semantic_entrypoint": candidate_public_raw_info["semantic_entrypoint"],
+        "expected_route": EXPECTED_ROUTES[row["label"]],
+        "selected_route": candidate_public_raw_info["selected_route"],
+        "child_route": candidate_public_raw_info.get("child_route"),
+        "route_matches_expected": bool(candidate_public_raw_info["selected_route"] == EXPECTED_ROUTES[row["label"]]),
+        "evolution_kernel_ms": row["evolution_kernel_ms"],
+        "evolution_flashlib_ms": row["evolution_flashlib_ms"],
+        "evolution_tflops": row["evolution_tflops"],
+        "evolution_speedup": row["evolution_speedup"],
+        "public_raw_baseline_name": PUBLIC_RAW_BASELINE_NAME,
+        "precomputed_baseline_name": PRECOMPUTED_BASELINE_NAME,
+        "baseline_commit": BASELINE_COMMIT,
+        "triton_h200_07cf_config": baseline_configs[0],
+        "measurement_session_id": measurement_session_id,
+        "candidate_public_raw_assignment_launch_count": candidate_public_raw_info["assignment_launch_count"],
+        "candidate_public_raw_norm_launch_count": candidate_public_raw_info["norm_launch_count"],
+        "candidate_public_raw_norm_compute_fields": list(candidate_fresh_norm_fields),
+        "candidate_public_raw_total_launch_count": candidate_public_raw_info["runtime_launch_count"],
+        "baseline_public_raw_assignment_launch_count": baseline_public_raw_fresh_info["assignment_launch_count"],
+        "baseline_public_raw_norm_launch_count": baseline_public_raw_fresh_info["norm_launch_count"],
+        "baseline_public_raw_norm_compute_fields": list(baseline_public_raw_fresh_info["norm_compute_fields"]),
+        "baseline_public_raw_total_launch_count": baseline_public_raw_fresh_info["runtime_launch_count"],
+        "candidate_precomputed_launch_count": candidate_precomputed_info["prepared_launch_count"],
+        "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+        "baseline_public_raw_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+        "candidate_precomputed_norm_policy": "explicit_precomputed_outside_timing",
+        "baseline_precomputed_norm_policy": "explicit_precomputed_outside_timing",
+        "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "baseline_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+        "candidate_precomputed_output_policy": "preallocated_outside_timing",
+        "baseline_precomputed_output_policy": "preallocated_outside_timing",
+        "candidate_public_raw_shape_first_was_cache_hit": candidate_shape_first_was_cache_hit,
+        "baseline_public_raw_shape_first_was_cache_hit": baseline_shape_first_was_cache_hit,
+        "candidate_public_raw_fresh_pointer_cache_hit": bool(candidate_public_raw_info["runtime_cache_hit"]),
+        "baseline_public_raw_fresh_pointer_cache_hit": bool(baseline_public_raw_fresh_info["runtime_cache_hit"]),
+        "fresh_pointer_rebind_verified": True,
+        "candidate_public_raw_cold_first_call_activity": candidate_public_raw_shape_info[
+            "cold_first_call_activity"
+        ],
+        "candidate_prepared_path_proof": prepared_path_proof,
+        "cold_candidate_public_raw_shape_miss": (
+            None if candidate_shape_first_was_cache_hit else _cold_call_fields(candidate_public_raw_shape_cold_call)
+        ),
+        "cold_candidate_public_raw_existing_shape_hit": (
+            _cold_call_fields(candidate_public_raw_shape_cold_call) if candidate_shape_first_was_cache_hit else None
+        ),
+        "cold_candidate_public_raw_fresh_pointer_hit": _cold_call_fields(candidate_public_raw_fresh_cold_call),
+        "cold_baseline_public_raw_shape_miss": (
+            None if baseline_shape_first_was_cache_hit else _cold_call_fields(baseline_public_raw_shape_cold_call)
+        ),
+        "cold_baseline_public_raw_existing_shape_hit": (
+            _cold_call_fields(baseline_public_raw_shape_cold_call) if baseline_shape_first_was_cache_hit else None
+        ),
+        "cold_baseline_public_raw_fresh_pointer_hit": _cold_call_fields(baseline_public_raw_fresh_cold_call),
+        "cold_candidate_precomputed_prepare_first_pointer": _cold_call_fields(candidate_precomputed_prepare_cold_call),
+        "cold_candidate_precomputed_prepare_fresh_pointer": _cold_call_fields(
+            fresh_candidate_precomputed_prepare_cold_call
+        ),
+        "cold_candidate_precomputed_first_pointer": _cold_call_fields(candidate_precomputed_first_cold_call),
+        "cold_candidate_precomputed_fresh_pointer": _cold_call_fields(fresh_candidate_precomputed_first_cold_call),
+        "cold_baseline_precomputed_first_pointer": _cold_call_fields(baseline_precomputed_first_cold_call),
+        "cold_baseline_precomputed_fresh_pointer": _cold_call_fields(baseline_precomputed_fresh_cold_call),
+    }
+
+    if correctness:
+        ref = _reference_assign(x, centroids, chunk_rows=reference_chunk_rows)
+        fresh_ref = _reference_assign(fresh_x, fresh_centroids, chunk_rows=reference_chunk_rows)
+        torch.cuda.synchronize()
+        baseline_public_raw_correctness = _assignment_correctness(
+            baseline_public_raw_out,
+            ref,
+            x,
+            centroids,
+        )
+        fresh_baseline_public_raw_correctness = _assignment_correctness(
+            fresh_baseline_public_raw_out,
+            fresh_ref,
+            fresh_x,
+            fresh_centroids,
+        )
+        candidate_public_raw_correctness = _assignment_correctness(
+            candidate_public_raw_out,
+            ref,
+            x,
+            centroids,
+        )
+        fresh_candidate_public_raw_correctness = _assignment_correctness(
+            fresh_candidate_public_raw_out,
+            fresh_ref,
+            fresh_x,
+            fresh_centroids,
+        )
+        candidate_precomputed_correctness = _assignment_correctness(
+            candidate_precomputed_result,
+            ref,
+            x,
+            centroids,
+        )
+        fresh_candidate_precomputed_correctness = _assignment_correctness(
+            fresh_candidate_precomputed_result,
+            fresh_ref,
+            fresh_x,
+            fresh_centroids,
+        )
+        baseline_precomputed_correctness = _assignment_correctness(
+            baseline_precomputed_result,
+            ref,
+            x,
+            centroids,
+        )
+        fresh_baseline_precomputed_correctness = _assignment_correctness(
+            fresh_baseline_precomputed_result,
+            fresh_ref,
+            fresh_x,
+            fresh_centroids,
+        )
+        result["candidate_public_raw_correctness"] = candidate_public_raw_correctness
+        result["candidate_public_raw_fresh_pointer_correctness"] = fresh_candidate_public_raw_correctness
+        result["baseline_public_raw_correctness"] = baseline_public_raw_correctness
+        result["baseline_public_raw_fresh_pointer_correctness"] = fresh_baseline_public_raw_correctness
+        result["candidate_precomputed_correctness"] = candidate_precomputed_correctness
+        result["candidate_precomputed_fresh_pointer_correctness"] = fresh_candidate_precomputed_correctness
+        result["baseline_precomputed_correctness"] = baseline_precomputed_correctness
+        result["baseline_precomputed_fresh_pointer_correctness"] = fresh_baseline_precomputed_correctness
+        correctness_rows = (
+            candidate_public_raw_correctness,
+            fresh_candidate_public_raw_correctness,
+            baseline_public_raw_correctness,
+            fresh_baseline_public_raw_correctness,
+            candidate_precomputed_correctness,
+            fresh_candidate_precomputed_correctness,
+            baseline_precomputed_correctness,
+            fresh_baseline_precomputed_correctness,
+        )
+        result["correct"] = all(bool(item["correct"]) for item in correctness_rows)
+
+    if benchmark:
+        baseline_public_raw_output_holder = [fresh_baseline_public_raw_out]
+        candidate_public_raw_output_holder = [fresh_candidate_public_raw_out]
+
+        def held_baseline_public_raw(x_value, centroids_value):
+            baseline_public_raw_output_holder[0] = baseline_adapter.compute(x_value, centroids_value)
+            return baseline_public_raw_output_holder[0]
+
+        def held_candidate_public_raw(x_value, centroids_value):
+            candidate_public_raw_output_holder[0] = runtime.compute(x_value, centroids_value)
+            return candidate_public_raw_output_holder[0]
+
+        role_factories = {
+            "candidate_public_raw": lambda: _alternating_call(
+                lambda: held_candidate_public_raw(x, centroids),
+                lambda: held_candidate_public_raw(fresh_x, fresh_centroids),
+            ),
+            "baseline_public_raw": lambda: _alternating_call(
+                lambda: held_baseline_public_raw(x, centroids),
+                lambda: held_baseline_public_raw(fresh_x, fresh_centroids),
+            ),
+            "candidate_precomputed": lambda: _alternating_call(
+                lambda: flash_kmeans_assign_prepared(candidate_prepared),
+                lambda: flash_kmeans_assign_prepared(fresh_candidate_prepared),
+            ),
+            "baseline_precomputed": lambda: _alternating_call(
+                baseline_precomputed_first_call,
+                baseline_precomputed_fresh_pointer_call,
+            ),
+        }
+        cold_first_calls = {
+            "candidate_public_raw": candidate_public_raw_fresh_cold_call,
+            "baseline_public_raw": baseline_public_raw_fresh_cold_call,
+            "candidate_precomputed": fresh_candidate_precomputed_first_cold_call,
+            "baseline_precomputed": baseline_precomputed_fresh_cold_call,
+        }
+        timings, paired_session = _bench_interleaved_roles(
+            label=str(row["label"]),
+            order_seed=measurement_order_seed,
+            role_factories=role_factories,
+            cold_first_calls=cold_first_calls,
+        )
+        candidate_public_raw_timing = timings["candidate_public_raw"]
+        baseline_public_raw_timing = timings["baseline_public_raw"]
+        candidate_precomputed_timing = timings["candidate_precomputed"]
+        baseline_precomputed_timing = timings["baseline_precomputed"]
+        timing_backends = {
+            candidate_public_raw_timing.backend,
+            baseline_public_raw_timing.backend,
+            candidate_precomputed_timing.backend,
+            baseline_precomputed_timing.backend,
+        }
+        if timing_backends != {"cupti"}:
+            raise RuntimeError(f"dual-lane benchmark requires CUPTI for every timing block, got {timing_backends}")
+        result["measurement_order"] = paired_session["first_reportable_roles"]
+        result["measurement_order_policy"] = "deterministic_interleaved_adjacent_ab_pairs"
+        result["measurement_order_seed"] = measurement_order_seed
+        result["paired_cupti_session_id"] = f"{measurement_session_id}:{row['label']}"
+        result["paired_cupti_session"] = paired_session
+        result["cold_measurement_order"] = list(cold_measurement_order)
+        result["cold_measurement_order_policy"] = "deterministic_balanced_per_publication_contract_portfolio"
+        result["timing_backend"] = "cupti"
+        result["candidate_public_raw_gpu_span_ms"] = candidate_public_raw_timing.median_gpu_span_ms
+        result["candidate_public_raw_kernel_sum_ms"] = candidate_public_raw_timing.median_kernel_sum_ms
+        result["candidate_public_raw_inter_kernel_gap_ms"] = candidate_public_raw_timing.median_inter_kernel_gap_ms
+        result["candidate_public_raw_submission_ms"] = _required_median(
+            candidate_public_raw_timing.median_submission_ms,
+            metric="candidate public-raw submission_ms",
+        )
+        result["candidate_public_raw_host_enqueue_ms"] = _required_median(
+            candidate_public_raw_timing.median_host_enqueue_ms,
+            metric="candidate public-raw host_enqueue_ms",
+        )
+        result["candidate_public_raw_synchronized_e2e_ms"] = _required_median(
+            candidate_public_raw_timing.median_synchronized_e2e_ms,
+            metric="candidate public-raw synchronized_e2e_ms",
+        )
+        result["candidate_public_raw_timing_backend"] = candidate_public_raw_timing.backend
+        result["candidate_public_raw_bench_iters"] = len(candidate_public_raw_timing.times_ms)
+        result["candidate_public_raw_timing_diagnostics"] = _timing_diagnostics(
+            candidate_public_raw_timing,
+            primary_metric="synchronized_e2e_ms",
+        )
+
+        result["baseline_07cf_adapter_gpu_span_ms"] = baseline_public_raw_timing.median_gpu_span_ms
+        result["baseline_07cf_adapter_kernel_sum_ms"] = baseline_public_raw_timing.median_kernel_sum_ms
+        result["baseline_07cf_adapter_inter_kernel_gap_ms"] = baseline_public_raw_timing.median_inter_kernel_gap_ms
+        result["baseline_07cf_adapter_submission_ms"] = _required_median(
+            baseline_public_raw_timing.median_submission_ms,
+            metric="07cf raw-adapter submission_ms",
+        )
+        result["baseline_07cf_adapter_host_enqueue_ms"] = _required_median(
+            baseline_public_raw_timing.median_host_enqueue_ms,
+            metric="07cf raw-adapter host_enqueue_ms",
+        )
+        result["baseline_07cf_adapter_synchronized_e2e_ms"] = _required_median(
+            baseline_public_raw_timing.median_synchronized_e2e_ms,
+            metric="07cf raw-adapter synchronized_e2e_ms",
+        )
+        result["baseline_07cf_adapter_timing_backend"] = baseline_public_raw_timing.backend
+        result["baseline_07cf_adapter_bench_iters"] = len(baseline_public_raw_timing.times_ms)
+        result["baseline_07cf_adapter_timing_diagnostics"] = _timing_diagnostics(
+            baseline_public_raw_timing,
+            primary_metric="synchronized_e2e_ms",
+        )
+
+        result["candidate_precomputed_gpu_span_ms"] = candidate_precomputed_timing.median_gpu_span_ms
+        result["candidate_precomputed_kernel_sum_ms"] = candidate_precomputed_timing.median_kernel_sum_ms
+        result["candidate_precomputed_inter_kernel_gap_ms"] = candidate_precomputed_timing.median_inter_kernel_gap_ms
+        result["candidate_precomputed_submission_ms"] = _required_median(
+            candidate_precomputed_timing.median_submission_ms,
+            metric="candidate prepared submission_ms",
+        )
+        result["candidate_precomputed_host_enqueue_ms"] = _required_median(
+            candidate_precomputed_timing.median_host_enqueue_ms,
+            metric="candidate prepared host_enqueue_ms",
+        )
+        result["candidate_precomputed_synchronized_e2e_ms"] = _required_median(
+            candidate_precomputed_timing.median_synchronized_e2e_ms,
+            metric="candidate prepared synchronized_e2e_ms",
+        )
+        result["candidate_precomputed_timing_backend"] = candidate_precomputed_timing.backend
+        result["candidate_precomputed_bench_iters"] = len(candidate_precomputed_timing.times_ms)
+        result["candidate_precomputed_timing_diagnostics"] = _timing_diagnostics(
+            candidate_precomputed_timing,
+            primary_metric="gpu_span_ms",
+        )
+
+        result["baseline_07cf_precomputed_gpu_span_ms"] = baseline_precomputed_timing.median_gpu_span_ms
+        result["baseline_07cf_precomputed_kernel_sum_ms"] = baseline_precomputed_timing.median_kernel_sum_ms
+        result["baseline_07cf_precomputed_inter_kernel_gap_ms"] = baseline_precomputed_timing.median_inter_kernel_gap_ms
+        result["baseline_07cf_precomputed_submission_ms"] = _required_median(
+            baseline_precomputed_timing.median_submission_ms,
+            metric="07cf prepared submission_ms",
+        )
+        result["baseline_07cf_precomputed_host_enqueue_ms"] = _required_median(
+            baseline_precomputed_timing.median_host_enqueue_ms,
+            metric="07cf prepared host_enqueue_ms",
+        )
+        result["baseline_07cf_precomputed_synchronized_e2e_ms"] = _required_median(
+            baseline_precomputed_timing.median_synchronized_e2e_ms,
+            metric="07cf prepared synchronized_e2e_ms",
+        )
+        result["baseline_07cf_precomputed_timing_backend"] = baseline_precomputed_timing.backend
+        result["baseline_07cf_precomputed_bench_iters"] = len(baseline_precomputed_timing.times_ms)
+        result["baseline_07cf_precomputed_timing_diagnostics"] = _timing_diagnostics(
+            baseline_precomputed_timing,
+            primary_metric="gpu_span_ms",
+        )
+
+        flops = 2.0 * int(row["B"]) * int(row["N"]) * int(row["K"]) * int(row["D"])
+        result["candidate_public_raw_tflops_from_gpu_span"] = (
+            flops / candidate_public_raw_timing.median_gpu_span_ms / 1e9
+        )
+        result.update(
+            _dual_lane_speedups(
+                candidate_public_raw_timing=candidate_public_raw_timing,
+                baseline_public_raw_timing=baseline_public_raw_timing,
+                candidate_precomputed_timing=candidate_precomputed_timing,
+                baseline_precomputed_timing=baseline_precomputed_timing,
+            )
+        )
+        result["candidate_public_prepared_ratios"] = _public_prepared_ratios(
+            candidate_public_raw_timing,
+            candidate_precomputed_timing,
+        )
+        result["baseline_public_prepared_ratios"] = _public_prepared_ratios(
+            baseline_public_raw_timing,
+            baseline_precomputed_timing,
+        )
+        candidate_lifecycle = runtime_lifecycle_metrics(
+            api="flashlib_cake_kmeans.init(...).compute",
+            measurement_session_id=measurement_session_id,
+            timing_boundary=CANDIDATE_TIMING_BOUNDARY,
+            output_policy="default_output_allocated_before_preprocessing_inside_timing",
+            init=candidate_init_timing,
+            init_sample_id=measurement_session_id,
+            first_compute=candidate_public_raw_shape_cold_call,
+            first_cache_state=("shape_slot_hit" if candidate_shape_first_was_cache_hit else "shape_slot_miss"),
+            hot_compute=candidate_public_raw_timing,
+            hot_cache_state="fresh_pointer_shape_slot_hit",
+            code_cache_state="process_order_dependent",
+        )
+        baseline_lifecycle = runtime_lifecycle_metrics(
+            api="triton_h200_07cf_raw_adapter_v1.compute",
+            measurement_session_id=measurement_session_id,
+            timing_boundary=BASELINE_TIMING_BOUNDARY,
+            output_policy="default_output_allocated_before_preprocessing_inside_timing",
+            init=baseline_init_timing,
+            init_sample_id=measurement_session_id,
+            first_compute=baseline_public_raw_shape_cold_call,
+            first_cache_state=("shape_slot_hit" if baseline_shape_first_was_cache_hit else "shape_slot_miss"),
+            hot_compute=baseline_public_raw_timing,
+            hot_cache_state="fresh_pointer_shape_slot_hit",
+            code_cache_state="process_order_dependent",
+        )
+        lifecycle_comparison = compare_runtime_lifecycles(candidate_lifecycle, baseline_lifecycle)
+        if not math.isclose(
+            lifecycle_comparison["hot_synchronized_e2e_speedup"],
+            result["public_raw_e2e_speedup_vs_07cf_adapter"],
+            rel_tol=1.0e-12,
+            abs_tol=0.0,
+        ):
+            raise RuntimeError("KMeans lifecycle hot E2E speedup disagrees with publication speedup")
+        result["candidate_runtime_lifecycle"] = candidate_lifecycle
+        result["baseline_runtime_lifecycle"] = baseline_lifecycle
+        result["runtime_lifecycle_comparison"] = lifecycle_comparison
+
+    return result
+
+
+def main() -> int:
+    parser = argparse.ArgumentParser(
+        description="Correctness and CUPTI benchmark for flashlib_cake_kmeans.flash_kmeans_assign"
+    )
+    parser.add_argument("--shape", action="append", help="Shape label to run. Repeatable.")
+    parser.add_argument(
+        "--source",
+        action="append",
+        help="Source set to run, for example full95. Repeatable.",
+    )
+    parser.add_argument("--unique", action="store_true", help="Run one row per unique (B,N,D,K,dtype).")
+    parser.add_argument(
+        "--include-runtime-coverage",
+        action="store_true",
+        help="Include the 104 runtime-only rows; publication defaults to the registry 124.",
+    )
+    parser.add_argument("--limit", type=int, default=None, help="Limit selected rows after filtering.")
+    parser.add_argument("--arch", default=None, help="NVRTC architecture, e.g. sm_100a.")
+    parser.add_argument(
+        "--metadata-only",
+        action="store_true",
+        help="Emit available benchmark metadata without CUDA.",
+    )
+    parser.add_argument(
+        "--no-correctness",
+        action="store_true",
+        help="Skip PyTorch reference correctness checks.",
+    )
+    parser.add_argument("--no-benchmark", action="store_true", help="Skip CUPTI timing.")
+    parser.add_argument(
+        "--reference-chunk-rows",
+        type=int,
+        default=128,
+        help="Rows per chunk for PyTorch reference.",
+    )
+    parser.add_argument("--json", type=Path, default=None, help="Optional path for JSON output.")
+    parser.add_argument(
+        "--order-seed",
+        default=DEFAULT_MEASUREMENT_ORDER_SEED,
+        help="Deterministic seed for the interleaved paired CUPTI schedule.",
+    )
+    parser.add_argument("--shard-index", type=int, default=0, help="Zero-based validation shard index.")
+    parser.add_argument("--shard-count", type=int, default=1, help="Number of validation shards.")
+    parser.add_argument("--quiet", action="store_true", help="Do not print the full JSON payload.")
+    args = parser.parse_args()
+
+    if args.limit is not None and args.limit < 0:
+        parser.error("--limit must be non-negative")
+    if args.reference_chunk_rows <= 0:
+        parser.error("--reference-chunk-rows must be positive")
+    if args.shard_count <= 0 or not 0 <= args.shard_index < args.shard_count:
+        parser.error("shard index must satisfy 0 <= index < count and count must be positive")
+    if not args.order_seed:
+        parser.error("--order-seed must be non-empty")
+    if args.json is not None:
+        args.json.unlink(missing_ok=True)
+
+    rows = _selected_rows(args)
+    measurement_session_id = uuid.uuid4().hex
+    preprocess_source_digest = _preprocess_source_digest()
+    if preprocess_source_digest != BASELINE_REGISTRY_PROFILE["shared_preprocess"]["source_sha256"]:
+        raise RuntimeError("exported preprocessing sources do not match the pinned registry profile")
+    profile_digest = hashlib.sha256(
+        json.dumps(
+            BASELINE_REGISTRY_PROFILE,
+            sort_keys=True,
+            separators=(",", ":"),
+            ensure_ascii=False,
+        ).encode("utf-8")
+    ).hexdigest()
+    if profile_digest != BASELINE_REGISTRY_SHA256:
+        raise RuntimeError("embedded registry baseline profile digest is stale")
+    payload: dict[str, Any] = {
+        "schema": "flash-kmeans-export-dual-lane-v2",
+        "api": "flashlib_cake_kmeans.init(...).compute",
+        "semantic_entrypoint": SEMANTIC_ENTRYPOINT,
+        "publication_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+        "parity_metric": "precomputed_gpu_speedup_vs_07cf",
+        "baseline_name": PUBLIC_RAW_BASELINE_NAME,
+        "public_raw_baseline_name": PUBLIC_RAW_BASELINE_NAME,
+        "precomputed_baseline_name": PRECOMPUTED_BASELINE_NAME,
+        "baseline_commit": BASELINE_COMMIT,
+        "baseline_entrypoint": BASELINE_ENTRYPOINT,
+        "benchmark_registry_baseline_key": BASELINE_REGISTRY_KEY,
+        "benchmark_registry_baseline_sha256": BASELINE_REGISTRY_SHA256,
+        "benchmark_registry_baseline_profile": BASELINE_REGISTRY_PROFILE,
+        "registry_candidate_entrypoint": REGISTRY_CANDIDATE_ENTRYPOINT,
+        "measured_candidate_entrypoint": MEASURED_CANDIDATE_ENTRYPOINT,
+        "official_timing_boundary": CANDIDATE_TIMING_BOUNDARY,
+        "candidate_timing_boundary": CANDIDATE_TIMING_BOUNDARY,
+        "benchmark_registry_candidate_timing_boundary": REGISTRY_CANDIDATE_TIMING_BOUNDARY,
+        "baseline_timing_boundary": BASELINE_TIMING_BOUNDARY,
+        "publication_speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+        "publication_timing_backend": "cupti",
+        "publication_speedup_convention": (
+            "public_raw_e2e_speedup_vs_07cf_adapter = "
+            "baseline_07cf_adapter_synchronized_e2e_ms / candidate_public_raw_synchronized_e2e_ms"
+        ),
+        "precomputed_parity_speedup_convention": (
+            "precomputed_gpu_speedup_vs_07cf = "
+            "baseline_07cf_precomputed_gpu_span_ms / candidate_precomputed_gpu_span_ms"
+        ),
+        "preprocess_impl": PREPROCESS_IMPL,
+        "preprocess_source_sha256": preprocess_source_digest,
+        "timing_window_ms": {"warmup_ms": WARMUP_MS, "bench_ms": BENCH_MS},
+        "submission_metric": {
+            "field": "submission_ms",
+            "host_enqueue_alias_field": "host_enqueue_ms",
+            "relationship": "same_cpu_submission_bracket",
+        },
+        "artifact": FLASH_KMEANS_EVOLUTION_ARTIFACT,
+        "evolution_summary": FLASH_KMEANS_EVOLUTION_SUMMARY,
+        "selected_row_count": len(rows),
+        "selected_unique_shape_count": len({_shape_key(row) for row in rows}),
+        "metadata_only": bool(args.metadata_only),
+        "validation_shard": {"index": args.shard_index, "count": args.shard_count},
+        "shapes": rows,
+        "measurement_session": {
+            "id": measurement_session_id,
+            "scope": "per_shape_single_cupti_activity_session_interleaved_paired_roles",
+            "same_process": True,
+            "same_cupti_session": (
+                True if not args.metadata_only and not args.no_benchmark else None
+            ),
+            "interleaved": (
+                True if not args.metadata_only and not args.no_benchmark else None
+            ),
+            "reportable_timing_collected": bool(
+                not args.metadata_only and not args.no_benchmark
+            ),
+            "randomized_or_interleaved_order": True,
+            "sequential_full_sweeps": False,
+            "timing_blocks": "one_interleaved_cupti_activity_session_per_shape",
+            "adaptive_probe_scope": "separate_nonreportable_cupti_estimation_only",
+            "alternate_two_pointer_sets": True,
+            "public_raw_e2e": {
+                "candidate_api": "flashlib_cake_kmeans.init(...).compute(raw_inputs)",
+                "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute(raw_inputs)",
+                "comparison_scope": "complete_raw_input_operators_not_assignment_only",
+                "candidate_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
+                "baseline_norm_policy": "shared_kernel_all_fields_required_by_frozen_07cf",
+                "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+                "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+                "candidate_scratch_policy": "per_shape_per_stream_cached",
+                "baseline_scratch_policy": "per_shape_per_stream_cached",
+                "candidate_runtime_initialized_once": True,
+                "baseline_runtime_initialized_once": True,
+                "preprocess_impl": PREPROCESS_IMPL,
+                "preprocess_source_sha256": preprocess_source_digest,
+                "shared_preprocess_cold_compile_attributed_to_lane": None,
+                "fixture_synchronized_before_cold_calls": True,
+                "assignment_baseline": "frozen_07cf",
+            },
+            "precomputed_kernel_parity": {
+                "candidate_api": "flash_kmeans_assign_prepared",
+                "baseline_api": "euclid_assign_triton_h200_07cf",
+                "candidate_norm_policy": "explicit_precomputed_outside_timing",
+                "baseline_norm_policy": "explicit_precomputed_outside_timing",
+                "candidate_output_policy": "preallocated_outside_timing",
+                "baseline_output_policy": "preallocated_outside_timing",
+                "both_pointer_sets_prepared_before_timing": True,
+            },
+            "runtime_instances_reused_across_shapes": True,
+            "resident_multi_shape_cache_benchmarked": False,
+            "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+            "baseline_commit": BASELINE_COMMIT,
+            "order_policy": "deterministic_interleaved_adjacent_ab_pairs",
+            "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+            "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+            "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+            "baseline_has_explicit_init": True,
+            "order_seed": args.order_seed,
+        },
+        "runtime_lifecycle": {
+            "schema": "loom-public-runtime-lifecycle-v1",
+            "candidate_api": "flashlib_cake_kmeans.init(...).compute",
+            "baseline_api": "triton_h200_07cf_raw_adapter_v1.compute",
+            "candidate_timing_boundary": CANDIDATE_TIMING_BOUNDARY,
+            "baseline_timing_boundary": BASELINE_TIMING_BOUNDARY,
+            "init_scope": (
+                "runtime_init_plus_standalone_shared_preprocess_support_once_per_"
+                "validation_shard_process_device_operator"
+            ),
+            "amortization_call_counts": [1, 10, 100, 1000],
+            "cache_policy": "synchronize_and_clear_after_each_completed_shape",
+            "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
+            "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
+            "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
+            "baseline_has_explicit_init": True,
+            "resident_multi_shape_cache_benchmarked": False,
+            "candidate_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+            "baseline_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
+            "session": None,
+        },
+    }
+    if args.metadata_only:
+        payload["results"] = []
+    else:
+        import torch
+        from flashlib_cake_kmeans import init
+
+        capability = torch.cuda.get_device_capability()
+        detected_arch = f"sm_{capability[0]}{capability[1]}" + ("" if capability[0] == 8 else "a")
+        payload["hardware"] = {
+            "device": torch.cuda.get_device_name(),
+            "arch": detected_arch,
+        }
+        device_index = torch.cuda.current_device()
+        resolved_arch = args.arch or payload["hardware"]["arch"]
+        init_measurement_order = ("candidate", "baseline") if args.shard_index % 2 == 0 else ("baseline", "candidate")
+        if not args.no_benchmark:
+            require_cupti()
+            runtime = None
+            baseline_adapter = None
+            runtime_init_call = None
+            baseline_adapter_init_call = None
+            for lane in init_measurement_order:
+                if lane == "candidate":
+                    runtime, runtime_init_call = measure_host_call(
+                        lambda: init(
+                            device=device_index,
+                            arch=resolved_arch,
+                            compile="lazy",
+                        )
+                    )
+                else:
+                    baseline_adapter, baseline_adapter_init_call = measure_host_call(
+                        lambda: TritonH20007cfRawAdapter(
+                            device_index=device_index,
+                            arch=resolved_arch,
+                        )
+                    )
+            if runtime is None or baseline_adapter is None:
+                raise RuntimeError("KMeans init measurement did not construct both standalone lanes")
+        else:
+            runtime = init(
+                device=device_index,
+                arch=resolved_arch,
+                compile="lazy",
+            )
+            runtime_init_call = None
+            baseline_adapter = TritonH20007cfRawAdapter(
+                device_index=device_index,
+                arch=resolved_arch,
+            )
+            baseline_adapter_init_call = None
+        shared_preprocess_cold_compile = (
+            _measure_shared_preprocess_cold_compile(rows[0], arch=runtime.arch)
+            if rows and not args.no_benchmark
+            else None
+        )
+        candidate_lifecycle_init = (
+            _sum_host_timings(runtime_init_call, shared_preprocess_cold_compile)
+            if runtime_init_call is not None and shared_preprocess_cold_compile is not None
+            else runtime_init_call
+        )
+        baseline_lifecycle_init = (
+            _sum_host_timings(baseline_adapter_init_call, shared_preprocess_cold_compile)
+            if baseline_adapter_init_call is not None and shared_preprocess_cold_compile is not None
+            else baseline_adapter_init_call
+        )
+        payload["cold_candidate_runtime_init"] = _cold_call_fields(runtime_init_call)
+        payload["cold_baseline_07cf_adapter_init"] = _cold_call_fields(baseline_adapter_init_call)
+        payload["cold_shared_preprocess_compile"] = _cold_call_fields(shared_preprocess_cold_compile)
+        results = []
+        for row in rows:
+            try:
+                results.append(
+                    _run_shape(
+                        row,
+                        runtime=runtime,
+                        baseline_adapter=baseline_adapter,
+                        candidate_init_timing=candidate_lifecycle_init,
+                        baseline_init_timing=baseline_lifecycle_init,
+                        arch=args.arch,
+                        correctness=not args.no_correctness,
+                        benchmark=not args.no_benchmark,
+                        reference_chunk_rows=args.reference_chunk_rows,
+                        measurement_session_id=measurement_session_id,
+                        measurement_order_seed=args.order_seed,
+                    )
+                )
+            finally:
+                runtime.clear()
+                baseline_adapter.clear()
+        payload["results"] = results
+        payload["runtime_workspace_lifecycle"] = (
+            "both_init_once_runtimes_synchronize_and_clear_after_each_completed_shape"
+        )
+        candidate_first_miss_count = sum(
+            not bool(row["candidate_public_raw_shape_first_was_cache_hit"]) for row in results
+        )
+        baseline_first_miss_count = sum(
+            not bool(row["baseline_public_raw_shape_first_was_cache_hit"]) for row in results
+        )
+        candidate_fresh_hit_count = sum(bool(row["candidate_public_raw_fresh_pointer_cache_hit"]) for row in results)
+        baseline_fresh_hit_count = sum(bool(row["baseline_public_raw_fresh_pointer_cache_hit"]) for row in results)
+        if args.no_benchmark:
+            payload.pop("runtime_lifecycle", None)
+        else:
+            payload["runtime_lifecycle"]["session"] = {
+                "id": measurement_session_id,
+                "init_measurement_order": [*init_measurement_order, "shared_preprocess_compile"],
+                "candidate_init": _cold_call_fields(candidate_lifecycle_init),
+                "baseline_init": _cold_call_fields(baseline_lifecycle_init),
+                "init_components": {
+                    "candidate_runtime_init": _cold_call_fields(runtime_init_call),
+                    "baseline_runtime_init": _cold_call_fields(baseline_adapter_init_call),
+                    "shared_preprocess_compile": _cold_call_fields(shared_preprocess_cold_compile),
+                    "attribution": "included_once_in_each_standalone_lane_init_total",
+                },
+                "clear_count": {"candidate": len(results), "baseline": len(results)},
+                "first_lookup_miss_count": {
+                    "candidate": candidate_first_miss_count,
+                    "baseline": baseline_first_miss_count,
+                },
+                "fresh_pointer_hit_count": {
+                    "candidate": candidate_fresh_hit_count,
+                    "baseline": baseline_fresh_hit_count,
+                },
+                "final_candidate_cache_info": runtime.cache_info(),
+                "final_baseline_cache_info": baseline_adapter.cache_info(),
+            }
+
+    text = json.dumps(payload, indent=2, sort_keys=True)
+    if args.json is not None:
+        args.json.parent.mkdir(parents=True, exist_ok=True)
+        _write_json_atomic(args.json, text)
+    if not args.quiet:
+        print(text)
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
diff --git a/cake_exports/kmeans/benchmarks/benchmark_exported_kernels.py b/cake_exports/kmeans/benchmarks/benchmark_exported_kernels.py
new file mode 100644
index 00000000..4e237f98
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/benchmark_exported_kernels.py
@@ -0,0 +1,144 @@
+from __future__ import annotations
+
+import argparse
+import importlib
+import json
+import statistics
+import sys
+import time
+from pathlib import Path
+from typing import Any
+
+
+ROOT = Path(__file__).resolve().parents[1]
+SRC = ROOT / "src"
+if str(SRC) not in sys.path:
+    sys.path.insert(0, str(SRC))
+
+PACKAGE_NAME = 'flashlib_cake_kmeans'
+
+
+def _selected_names(pkg: Any, requested: list[str] | None) -> list[str]:
+    if not requested:
+        return list(pkg.KERNELS)
+    missing = sorted(set(requested) - set(pkg.KERNELS))
+    if missing:
+        available = ", ".join(sorted(pkg.KERNELS))
+        raise SystemExit(f"unknown kernel(s) {missing}. Available: {available}")
+    return requested
+
+
+def _entry_for_kernel(pkg: Any, name: str, *, metadata_only: bool, arch: str | None, iterations: int):
+    kernel = pkg.get_kernel(name)
+    entry: dict[str, Any] = {
+        "name": name,
+        "symbol": kernel.spec.symbol,
+        "launch_mode": kernel.spec.launch_mode,
+        "threads": kernel.spec.threads,
+        "shared_mem_bytes": kernel.spec.shared_mem_bytes,
+        "parameter_count": len(kernel.parameters),
+        "status": "metadata_only" if metadata_only else "pending",
+    }
+    if metadata_only:
+        return entry
+
+    times_ms: list[float] = []
+    try:
+        runtime = importlib.import_module(f"{PACKAGE_NAME}._runtime")
+        for _ in range(iterations):
+            runtime.clear_compilation_cache()
+            start = time.perf_counter()
+            kernel.compile(arch=arch)
+            times_ms.append((time.perf_counter() - start) * 1000.0)
+    except Exception as exc:  # noqa: BLE001 - benchmark report should preserve the failure.
+        entry["status"] = "failed"
+        entry["error"] = f"{type(exc).__name__}: {exc}"
+        return entry
+
+    entry["status"] = "passed"
+    entry["compile_ms_median"] = statistics.median(times_ms)
+    entry["compile_ms_min"] = min(times_ms)
+    entry["compile_ms_max"] = max(times_ms)
+    entry["iterations"] = iterations
+    return entry
+
+
+def run_benchmark(
+    *,
+    kernels: list[str] | None = None,
+    arch: str | None = None,
+    iterations: int = 1,
+    metadata_only: bool = False,
+) -> dict[str, Any]:
+    pkg = importlib.import_module(PACKAGE_NAME)
+    selected = _selected_names(pkg, kernels)
+    entries = [
+        _entry_for_kernel(pkg, name, metadata_only=metadata_only, arch=arch, iterations=iterations)
+        for name in selected
+    ]
+    passed = sum(1 for entry in entries if entry["status"] in {"passed", "metadata_only"})
+    failed = sum(1 for entry in entries if entry["status"] == "failed")
+    return {
+        "benchmark": "exported_kernel_compile",
+        "package": PACKAGE_NAME,
+        "arch": arch,
+        "iterations": iterations,
+        "metadata_only": metadata_only,
+        "summary": {
+            "kernel_count": len(entries),
+            "passed": passed,
+            "failed": failed,
+            "all_passed": failed == 0,
+        },
+        "kernels": entries,
+    }
+
+
+def _print_summary(payload: dict[str, Any]) -> None:
+    summary = payload["summary"]
+    print(
+        "benchmark={benchmark} package={package} kernels={kernel_count} passed={passed} failed={failed}".format(
+            benchmark=payload["benchmark"],
+            package=payload["package"],
+            kernel_count=summary["kernel_count"],
+            passed=summary["passed"],
+            failed=summary["failed"],
+        )
+    )
+    for entry in payload["kernels"]:
+        if entry["status"] == "passed":
+            print(
+                "{name}: compile_median={compile_ms_median:.3f} ms status=passed".format(**entry)
+            )
+        else:
+            detail = f" error={entry['error']}" if "error" in entry else ""
+            print(f"{entry['name']}: status={entry['status']}{detail}")
+
+
+def main(argv: list[str] | None = None) -> int:
+    parser = argparse.ArgumentParser(description="Benchmark exported CUDA kernel compile latency.")
+    parser.add_argument("--kernel", action="append", dest="kernels", help="Kernel name to benchmark.")
+    parser.add_argument("--arch", help="NVRTC GPU architecture, for example sm_100a.")
+    parser.add_argument("--iterations", type=int, default=1, help="Compile iterations per kernel.")
+    parser.add_argument("--metadata-only", action="store_true", help="Do not compile; emit benchmark schema.")
+    parser.add_argument("--json", type=Path, help="Write benchmark results as JSON.")
+    args = parser.parse_args(argv)
+    if args.iterations <= 0:
+        parser.error("--iterations must be positive")
+
+    payload = run_benchmark(
+        kernels=args.kernels,
+        arch=args.arch,
+        iterations=args.iterations,
+        metadata_only=args.metadata_only,
+    )
+    if args.json:
+        args.json.parent.mkdir(parents=True, exist_ok=True)
+        args.json.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8")
+    _print_summary(payload)
+    return 0 if payload["summary"]["all_passed"] else 1
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
+
diff --git a/cake_exports/kmeans/benchmarks/benchmark_shapes.py b/cake_exports/kmeans/benchmarks/benchmark_shapes.py
new file mode 100644
index 00000000..382538d6
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/benchmark_shapes.py
@@ -0,0 +1,252 @@
+from __future__ import annotations
+
+import argparse
+import importlib
+import json
+import sys
+from collections.abc import Mapping
+from pathlib import Path
+from typing import Any
+
+
+ROOT = Path(__file__).resolve().parents[1]
+SRC = ROOT / "src"
+if str(SRC) not in sys.path:
+    sys.path.insert(0, str(SRC))
+
+PACKAGE_NAME = 'flashlib_cake_kmeans'
+
+
+def _shape_name(shape: Mapping[str, Any], index: int) -> str:
+    return str(shape.get("name") or f"shape_{index}")
+
+
+def _selected_shapes(workload: Any, requested: list[str] | None) -> list[dict[str, Any]]:
+    shapes = [dict(shape) for shape in getattr(workload, "SHAPES", ())]
+    names = [_shape_name(shape, index) for index, shape in enumerate(shapes)]
+    if len(names) != len(set(names)):
+        raise ValueError("workload.SHAPES contains duplicate names")
+    if not requested:
+        return shapes
+    missing = sorted(set(requested) - set(names))
+    if missing:
+        raise ValueError(f"unknown shape(s) {missing}. Available: {', '.join(names)}")
+    requested_set = set(requested)
+    return [shape for index, shape in enumerate(shapes) if _shape_name(shape, index) in requested_set]
+
+
+def _comparison_payload(value: Any) -> dict[str, Any]:
+    if isinstance(value, bool):
+        return {"passed": value}
+    if not isinstance(value, Mapping) or "passed" not in value:
+        raise TypeError("case['compare'] must return bool or a mapping containing 'passed'")
+    return dict(value)
+
+
+def _run_shape(
+    pkg: Any,
+    workload: Any,
+    shape: dict[str, Any],
+    *,
+    index: int,
+    correctness_only: bool,
+    warmup_iters: int,
+    bench_iters: int,
+) -> dict[str, Any]:
+    name = _shape_name(shape, index)
+    entry: dict[str, Any] = {"name": name, "shape": shape, "status": "pending"}
+    try:
+        case = workload.make_case(pkg, shape)
+        if not isinstance(case, Mapping):
+            raise TypeError("make_case() must return a mapping")
+        missing = [key for key in ("run", "reference", "compare") if not callable(case.get(key))]
+        if missing:
+            raise TypeError(f"benchmark case is missing callable(s): {', '.join(missing)}")
+
+        expected = case["reference"]()
+        import torch
+
+        cold_first_call = None
+        if correctness_only:
+            actual = case["run"]()
+            torch.cuda.synchronize()
+        else:
+            from flashlib_cake_kmeans._benchmark import measure_host_call
+
+            actual, cold_first_call = measure_host_call(case["run"])
+        comparison = _comparison_payload(case["compare"](actual, expected))
+        entry["correctness"] = comparison
+        if not comparison["passed"]:
+            entry["status"] = "incorrect"
+            return entry
+        if correctness_only:
+            entry["status"] = "passed"
+            return entry
+
+        from flashlib_cake_kmeans._benchmark import bench_gpu_time
+
+        timing = bench_gpu_time(
+            case["run"],
+            warmup_iters=warmup_iters,
+            bench_iters=bench_iters,
+            cold_l2=True,
+            cold_first_call=cold_first_call,
+        )
+        entry["timing"] = {
+            "backend": timing.backend,
+            "official_gpu_metric": "gpu_span_ms",
+            "median_ms": timing.median_ms,
+            "min_ms": timing.min_ms,
+            "mean_ms": timing.mean_ms,
+            "iterations": len(timing.times_ms),
+            "cold_l2": True,
+            "gpu_span_ms": {
+                "median": timing.median_gpu_span_ms,
+                "iterations": timing.times_ms,
+            },
+            "kernel_sum_ms": {
+                "median": timing.median_kernel_sum_ms,
+                "iterations": timing.kernel_sum_times_ms,
+            },
+            "active_union_ms": {
+                "median": timing.median_active_union_ms,
+                "iterations": timing.active_union_times_ms,
+            },
+            "inter_kernel_gap_ms": {
+                "median": timing.median_inter_kernel_gap_ms,
+                "iterations": timing.inter_kernel_gap_times_ms,
+            },
+            "activity_count": {
+                "median": timing.median_activity_count,
+                "iterations": timing.activity_counts,
+            },
+            "correlated_launch_activity_count": {
+                "median": timing.median_launch_activity_count,
+                "iterations": timing.launch_activity_counts,
+            },
+            "correlated_kernel_activity_count": {
+                "median": timing.median_kernel_activity_count,
+                "iterations": timing.kernel_activity_counts,
+            },
+            "host_enqueue_ms": {
+                "median": timing.median_host_enqueue_ms,
+                "iterations": timing.host_enqueue_times_ms,
+            },
+            "synchronized_e2e_ms": {
+                "median": timing.median_synchronized_e2e_ms,
+                "iterations": timing.synchronized_e2e_times_ms,
+            },
+            "cold_first_call": {
+                "host_enqueue_ms": timing.cold_first_call_host_enqueue_ms,
+                "synchronized_e2e_ms": timing.cold_first_call_synchronized_e2e_ms,
+            },
+        }
+        flops = case.get("flops")
+        bytes_moved = case.get("bytes")
+        if flops is not None:
+            entry["tflops"] = float(flops) / timing.median_ms / 1e9
+        if bytes_moved is not None:
+            entry["gbps"] = float(bytes_moved) / timing.median_ms / 1e6
+        if case.get("metrics") is not None:
+            entry["metrics"] = dict(case["metrics"])
+        entry["status"] = "passed"
+    except Exception as exc:  # noqa: BLE001 - preserve per-shape failure in JSON.
+        entry["status"] = "failed"
+        entry["error"] = f"{type(exc).__name__}: {exc}"
+    return entry
+
+
+def run_benchmark(
+    *,
+    shapes: list[str] | None = None,
+    metadata_only: bool = False,
+    correctness_only: bool = False,
+    warmup_iters: int = 5,
+    bench_iters: int = 20,
+) -> dict[str, Any]:
+    pkg = importlib.import_module(PACKAGE_NAME)
+    workload = importlib.import_module("workload")
+    selected = _selected_shapes(workload, shapes)
+    configured = bool(getattr(workload, "CONFIGURED", bool(selected)))
+    entries = [
+        {"name": _shape_name(shape, index), "shape": shape, "status": "metadata_only"}
+        for index, shape in enumerate(selected)
+    ]
+    if not metadata_only:
+        if not configured or not selected:
+            raise RuntimeError(
+                "benchmarks/workload.py is not configured; provide --benchmark-adapter during export "
+                "or implement SHAPES and make_case()"
+            )
+        if not correctness_only:
+            # CUPTI must be imported before workload adapters import
+            # torch, which may otherwise load an incompatible system
+            # CUPTI soname first.
+            benchmark_runtime = importlib.import_module(f"{PACKAGE_NAME}._benchmark")
+            benchmark_runtime.require_cupti()
+        entries = [
+            _run_shape(
+                pkg,
+                workload,
+                shape,
+                index=index,
+                correctness_only=correctness_only,
+                warmup_iters=warmup_iters,
+                bench_iters=bench_iters,
+            )
+            for index, shape in enumerate(selected)
+        ]
+    passed = sum(1 for entry in entries if entry["status"] in {"passed", "metadata_only"})
+    failed = len(entries) - passed
+    return {
+        "benchmark": "exported_kernel_shapes",
+        "package": PACKAGE_NAME,
+        "metadata_only": metadata_only,
+        "correctness_only": correctness_only,
+        "adapter_configured": configured,
+        "timing_backend_requested": "cupti",
+        "summary": {
+            "shape_count": len(entries),
+            "passed": passed,
+            "failed": failed,
+            "all_passed": failed == 0,
+        },
+        "shapes": entries,
+    }
+
+
+def main(argv: list[str] | None = None) -> int:
+    parser = argparse.ArgumentParser(description="Validate and benchmark exported kernels by shape.")
+    parser.add_argument("--shape", action="append", dest="shapes", help="Shape name to run.")
+    parser.add_argument("--metadata-only", action="store_true", help="Emit adapter metadata without CUDA.")
+    parser.add_argument("--correctness-only", action="store_true", help="Validate without timing.")
+    parser.add_argument("--warmup-iters", type=int, default=5)
+    parser.add_argument("--bench-iters", type=int, default=20)
+    parser.add_argument("--json", type=Path, help="Write benchmark results as JSON.")
+    args = parser.parse_args(argv)
+    if args.warmup_iters < 0 or args.bench_iters <= 0:
+        parser.error("--warmup-iters must be non-negative and --bench-iters must be positive")
+    try:
+        payload = run_benchmark(
+            shapes=args.shapes,
+            metadata_only=args.metadata_only,
+            correctness_only=args.correctness_only,
+            warmup_iters=args.warmup_iters,
+            bench_iters=args.bench_iters,
+        )
+    except Exception as exc:  # noqa: BLE001 - CLI reports configuration failures cleanly.
+        parser.error(str(exc))
+    if args.json:
+        args.json.parent.mkdir(parents=True, exist_ok=True)
+        args.json.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8")
+    summary = payload["summary"]
+    print(
+        f"benchmark={payload['benchmark']} shapes={summary['shape_count']} "
+        f"passed={summary['passed']} failed={summary['failed']}"
+    )
+    return 0 if summary["all_passed"] else 1
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
+
diff --git a/cake_exports/kmeans/benchmarks/expected_routes.json b/cake_exports/kmeans/benchmarks/expected_routes.json
new file mode 100644
index 00000000..9c74f027
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/expected_routes.json
@@ -0,0 +1,622 @@
+[
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_1d49_d128_forced_fallback_b5_n7296_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_1d49_d224_highn_overlap_b5_n5632_k768_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_1d49_d288_low_n_heldout_b3_n1152_k2048_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "adjacent_1d49_d352_request_highk_b2_n1024_k8192_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_1d49_d416_random_b4_n3840_k512_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_1d49_d480_smallk_boundary_b2_n2816_k256_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_1d49_d48_lowk_boundary_b4_n3968_k256_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "adjacent_3328_d112_highk_low_n_b2_n512_k8192_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "adjacent_3328_d128_exact_guard_k_neighbor_b8_n8192_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_3328_d224_tail_div_b3_n3840_k512_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_3328_d288_guard_overlap_b4_n8192_k256_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_3328_d352_random_legal_b3_n2048_k768_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_3328_d416_highk_low_n_b1_n384_k8192_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_3328_d480_min_boundary_b1_n128_k256_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_3328_d48_small_boundary_b1_n256_k256_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_5600_d112_odd_tile_tail_b5_n2176_k512_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_5600_d128_fallback_neighbor_b8_n8320_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_5600_d224_k512_overlap_b3_n3072_k512_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_5600_d288_mid_highk_b2_n1024_k2048_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "adjacent_5600_d352_splitk_edge_b2_n768_k4096_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_5600_d416_smallk_boundary_b4_n2048_k256_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "adjacent_5600_d480_random_b1_n1536_k1024_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_5600_d48_low_n_boundary_b3_n1536_k256_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d112_tail_b5_n2944_k512_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_68cf_d128_forced_fallback_b7_n6016_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d224_overlap_b3_n5120_k1024_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_68cf_d288_boundary_b2_n1920_k512_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d352_tail_b3_n2816_k768_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d416_overlap_b2_n2304_k1024_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_68cf_d48_boundary_b4_n2304_k512_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "adjacent_8f09_d112_small_highk_b1_n384_k4096_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_8f09_d128_fallback_neighbor_b4_n4480_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4:launch_for_eval",
+    "selected_route": "d224_tmem_abi_repair_d17c_v4",
+    "shape": "adjacent_8f09_d224_low_n_boundary_b4_n1536_k256_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_8f09_d288_k768_overlap_b1_n2560_k768_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_8f09_d352_smallk_large_n_b4_n4096_k256_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_8f09_d416_midk_tail_b3_n3456_k768_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "adjacent_8f09_d480_highk_low_n_b2_n640_k4096_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_8f09_d48_medium_tail_b2_n1792_k512_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_9ca0_d112_tail_div_b3_n3840_k768_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_9ca0_d128_exact_guard_neighbor_b8_n8064_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_9ca0_d224_guard_overlap_b2_n4096_k256_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_9ca0_d288_highk_low_n_b1_n384_k4096_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "adjacent_9ca0_d352_splitk_boundary_b1_n512_k8192_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_9ca0_d416_splitk_min_b1_n1024_k4096_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_9ca0_d480_splitd_large_n_b2_n4096_k512_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_9ca0_d48_guard_boundary_b6_n12288_k512_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_a2f8_d112_lowk_tail_b4_n3456_k256_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_a2f8_d128_odd_fallback_b6_n8576_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_a2f8_d224_highn_overlap_b2_n6144_k768_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_a2f8_d288_splitk_probe_b1_n640_k4096_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_a2f8_d352_smallk_boundary_b4_n1024_k256_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_a2f8_d416_random_b2_n2560_k768_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "adjacent_a2f8_d480_highk_request_b1_n896_k4096_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_a2f8_d48_k1024_boundary_b2_n768_k1024_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d112_odd_tail_b2_n3200_k768_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_c44f_d128_forced_fallback_b6_n6272_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d224_overlap_b4_n4480_k512_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_c44f_d288_highk_heldout_b2_n768_k4096_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d352_random_b1_n3328_k768_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d416_highk_request_b3_n512_k8192_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d480_boundary_b5_n2048_k512_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_c44f_d48_midk_boundary_b3_n2688_k768_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "adjacent_d9d5_d112_highk_request_b3_n768_k8192_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_d9d5_d128_guard_miss_fallback_b5_n6016_k1024_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_d9d5_d224_random_midk_b2_n2944_k1280_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_d9d5_d288_heldout_low_n_b1_n896_k4096_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_d9d5_d352_random_b5_n2304_k768_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_d9d5_d416_highk_request_b2_n640_k8192_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_d9d5_d48_highk_heldout_b2_n640_k4096_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d112_odd_tail_b4_n3712_k1024_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "adjacent_ef00_d128_forced_fallback_b4_n7552_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d224_midn_overlap_b2_n5376_k512_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "adjacent_ef00_d288_highk_heldout_b1_n1664_k4096_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "adjacent_ef00_d352_request_low_n_b3_n896_k8192_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d416_random_midk_b1_n2176_k768_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "adjacent_ef00_d48_midn_boundary_b3_n3456_k512_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "post_d895_d112_b1_n256_k256_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "post_d895_d112_b1_n512_k8192_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval",
+    "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+    "shape": "post_d895_d112_b2_n2048_k512_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d112_b4_n8192_k1024_d112"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "post_d895_d128_fallback_b3_n1920_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "post_d895_d128_fallback_b5_n2176_k512_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "aligned_weave_v10_fallback",
+    "shape": "post_d895_d128_fallback_b7_n2432_k1024_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval",
+    "selected_route": "paired_large_v15",
+    "shape": "post_d895_d128_paired_b2_n262144_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval",
+    "selected_route": "d128_even_near_floor_v10_repair",
+    "shape": "post_d895_d128_paired_b8_n8192_k256_d128"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d144_b1_n256_k256_d144"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d144_b1_n512_k8192_d144"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d144_b2_n2048_k1024_d144"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d144_b4_n8192_k1024_d144"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "post_d895_d16_b4_n32768_k1024_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_pipeline4_08f9_v4:launch_for_eval",
+    "selected_route": "microdim_pipeline4_08f9_v4",
+    "shape": "post_d895_d16_b8_n65536_k512_d16"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d176_b1_n256_k256_d176"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d176_b1_n512_k8192_d176"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d176_b2_n2048_k1024_d176"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval",
+    "selected_route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+    "shape": "post_d895_d176_b4_n8192_k1024_d176"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d224_b1_n256_k256_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d224_b1_n512_k8192_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d224_b2_n2048_k1024_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d224_b4_n8192_k1024_d224"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "post_d895_d288_b1_n256_k256_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "post_d895_d288_b1_n512_k8192_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "post_d895_d288_b2_n2048_k1024_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval",
+    "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+    "shape": "post_d895_d288_b4_n8192_k1024_d288"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval",
+    "selected_route": "microdim_hybrid_9c0d_v1",
+    "shape": "post_d895_d32_b4_n32768_k1024_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_microdim_pipeline4_08f9_v4:launch_for_eval",
+    "selected_route": "microdim_pipeline4_08f9_v4",
+    "shape": "post_d895_d32_b8_n65536_k512_d32"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d352_b1_n256_k256_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "post_d895_d352_b1_n512_k8192_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval",
+    "selected_route": "d352_exactd_splitk_c95c_v2",
+    "shape": "post_d895_d352_b2_n2048_k1024_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d352_b4_n8192_k1024_d352"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d416_b1_n256_k256_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d416_b1_n512_k8192_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d416_b2_n2048_k1024_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d416_b4_n8192_k1024_d416"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d480_b1_n256_k256_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "post_d895_d480_b1_n512_k8192_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval",
+    "selected_route": "d480_splitk_k1024_eac2_v1",
+    "shape": "post_d895_d480_b2_n2048_k1024_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d480_b4_n8192_k1024_d480"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d48_b1_n512_k8192_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d48_b2_n2048_k512_d48"
+  },
+  {
+    "launch_entrypoint": "loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval",
+    "selected_route": "gap_pad_to_supported_seed_v1",
+    "shape": "post_d895_d48_b4_n8192_k1024_d48"
+  }
+]
diff --git a/cake_exports/kmeans/benchmarks/flash_kmeans_shapes.py b/cake_exports/kmeans/benchmarks/flash_kmeans_shapes.py
new file mode 100644
index 00000000..a66560b3
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/flash_kmeans_shapes.py
@@ -0,0 +1,3436 @@
+from __future__ import annotations
+
+FLASH_KMEANS_EVOLUTION_ARTIFACT = (
+    "artifacts/generalize_auto_tuning/flash_kmeans_assign_20260620/dispatcher_perf_all_shapes_latest.md"
+)
+
+FLASH_KMEANS_EVOLUTION_SUMMARY = {
+    "mean_evolution_speedup": 19.980689035087718,
+    "mean_evolution_tflops": 25.401755701754386,
+    "min_evolution_speedup": 1.3307,
+    "row_count": 228,
+    "unique_shape_count": 225,
+}
+
+FLASH_KMEANS_SHAPES = [
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_heldout_neighborhood_d80_b2_n2176_k1024_d80",
+        "B": 2,
+        "N": 2176,
+        "D": 80,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "lowdim_e50c_v1",
+        "evolution_kernel_ms": 0.176928,
+        "evolution_flashlib_ms": 0.402944,
+        "evolution_tflops": 4.0301,
+        "evolution_flashlib_equiv_tflops": 1.7696,
+        "evolution_speedup": 2.2774,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_guard_miss_fallback_d128_b1_n1408_k512_d128",
+        "B": 1,
+        "N": 1408,
+        "D": 128,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "aligned_v10_fallback",
+        "evolution_kernel_ms": 0.144544,
+        "evolution_flashlib_ms": 0.348175,
+        "evolution_tflops": 1.2768,
+        "evolution_flashlib_equiv_tflops": 0.53,
+        "evolution_speedup": 2.4088,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_forced_fallback_d128_b1_n1664_k256_d128",
+        "B": 1,
+        "N": 1664,
+        "D": 128,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "aligned_v10_fallback",
+        "evolution_kernel_ms": 0.142032,
+        "evolution_flashlib_ms": 0.277904,
+        "evolution_tflops": 0.7678,
+        "evolution_flashlib_equiv_tflops": 0.3924,
+        "evolution_speedup": 1.9566,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_guard_boundary_d144_b1_n128_k256_d144",
+        "B": 1,
+        "N": 128,
+        "D": 144,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+        "evolution_kernel_ms": 0.1664,
+        "evolution_flashlib_ms": 0.459647,
+        "evolution_tflops": 0.0567,
+        "evolution_flashlib_equiv_tflops": 0.0205,
+        "evolution_speedup": 2.7623,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_tail_divisibility_d176_b1_n1152_k512_d176",
+        "B": 1,
+        "N": 1152,
+        "D": 176,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+        "evolution_kernel_ms": 0.174944,
+        "evolution_flashlib_ms": 0.395232,
+        "evolution_tflops": 1.1868,
+        "evolution_flashlib_equiv_tflops": 0.5253,
+        "evolution_speedup": 2.2592,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_guard_overlap_d192_b1_n1024_k768_d192",
+        "B": 1,
+        "N": 1024,
+        "D": 192,
+        "K": 768,
+        "dtype": "bfloat16",
+        "route": "d192_paired_repeated_mma_v1",
+        "evolution_kernel_ms": 0.17168,
+        "evolution_flashlib_ms": 0.45632,
+        "evolution_tflops": 1.759,
+        "evolution_flashlib_equiv_tflops": 0.6618,
+        "evolution_speedup": 2.658,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_random_legal_d320_b1_n1280_k512_d320",
+        "B": 1,
+        "N": 1280,
+        "D": 320,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "highd_splitd_single_tile_6fcf_v1",
+        "evolution_kernel_ms": 0.152496,
+        "evolution_flashlib_ms": 0.507759,
+        "evolution_tflops": 2.7504,
+        "evolution_flashlib_equiv_tflops": 0.826,
+        "evolution_speedup": 3.3297,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_request_specific_d448_b1_n1280_k1024_d448",
+        "B": 1,
+        "N": 1280,
+        "D": 448,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "highd_splitd_single_tile_6fcf_v1",
+        "evolution_kernel_ms": 0.173743,
+        "evolution_flashlib_ms": 0.674512,
+        "evolution_tflops": 6.7594,
+        "evolution_flashlib_equiv_tflops": 1.7411,
+        "evolution_speedup": 3.8822,
+    },
+    {
+        "source": "expanded9",
+        "label": "d895_expanded_request_specific_d512_splitk_b1_n512_k8192_d512",
+        "B": 1,
+        "N": 512,
+        "D": 512,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1",
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+        "label": "adjacent_3328_d416_highk_low_n_b1_n384_k8192_d416",
+        "B": 1,
+        "N": 384,
+        "D": 416,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.276031,
+        "evolution_flashlib_ms": 41.538691,
+        "evolution_tflops": 9.4817,
+        "evolution_flashlib_equiv_tflops": 0.063,
+        "evolution_speedup": 150.4856,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d416_b1_n512_k8192_d416",
+        "B": 1,
+        "N": 512,
+        "D": 416,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.275103,
+        "evolution_flashlib_ms": 40.967689,
+        "evolution_tflops": 12.6849,
+        "evolution_flashlib_equiv_tflops": 0.0852,
+        "evolution_speedup": 148.9176,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_9ca0_d416_splitk_min_b1_n1024_k4096_d416",
+        "B": 1,
+        "N": 1024,
+        "D": 416,
+        "K": 4096,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.274271,
+        "evolution_flashlib_ms": 41.154087,
+        "evolution_tflops": 12.7234,
+        "evolution_flashlib_equiv_tflops": 0.0848,
+        "evolution_speedup": 150.049,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_ef00_d416_random_midk_b1_n2176_k768_d416",
+        "B": 1,
+        "N": 2176,
+        "D": 416,
+        "K": 768,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.191648,
+        "evolution_flashlib_ms": 0.529311,
+        "evolution_tflops": 7.255,
+        "evolution_flashlib_equiv_tflops": 2.6268,
+        "evolution_speedup": 2.7619,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_d9d5_d416_highk_request_b2_n640_k8192_d416",
+        "B": 2,
+        "N": 640,
+        "D": 416,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.298432,
+        "evolution_flashlib_ms": 3.254428,
+        "evolution_tflops": 29.2333,
+        "evolution_flashlib_equiv_tflops": 2.6807,
+        "evolution_speedup": 10.9051,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d416_b2_n2048_k1024_d416",
+        "B": 2,
+        "N": 2048,
+        "D": 416,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.193983,
+        "evolution_flashlib_ms": 0.642463,
+        "evolution_tflops": 17.9895,
+        "evolution_flashlib_equiv_tflops": 5.4317,
+        "evolution_speedup": 3.312,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_68cf_d416_overlap_b2_n2304_k1024_d416",
+        "B": 2,
+        "N": 2304,
+        "D": 416,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.196895,
+        "evolution_flashlib_ms": 0.613215,
+        "evolution_tflops": 19.9389,
+        "evolution_flashlib_equiv_tflops": 6.4021,
+        "evolution_speedup": 3.1144,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_a2f8_d416_random_b2_n2560_k768_d416",
+        "B": 2,
+        "N": 2560,
+        "D": 416,
+        "K": 768,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.189631,
+        "evolution_flashlib_ms": 0.492399,
+        "evolution_tflops": 17.2522,
+        "evolution_flashlib_equiv_tflops": 6.6441,
+        "evolution_speedup": 2.5966,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_c44f_d416_highk_request_b3_n512_k8192_d416",
+        "B": 3,
+        "N": 512,
+        "D": 416,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.303423,
+        "evolution_flashlib_ms": 3.822732,
+        "evolution_tflops": 34.5029,
+        "evolution_flashlib_equiv_tflops": 2.7386,
+        "evolution_speedup": 12.5987,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_8f09_d416_midk_tail_b3_n3456_k768_d416",
+        "B": 3,
+        "N": 3456,
+        "D": 416,
+        "K": 768,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.189088,
+        "evolution_flashlib_ms": 0.493791,
+        "evolution_tflops": 35.0361,
+        "evolution_flashlib_equiv_tflops": 13.4164,
+        "evolution_speedup": 2.6114,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_5600_d416_smallk_boundary_b4_n2048_k256_d416",
+        "B": 4,
+        "N": 2048,
+        "D": 416,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.175743,
+        "evolution_flashlib_ms": 0.370128,
+        "evolution_tflops": 9.9283,
+        "evolution_flashlib_equiv_tflops": 4.7141,
+        "evolution_speedup": 2.1061,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_1d49_d416_random_b4_n3840_k512_d416",
+        "B": 4,
+        "N": 3840,
+        "D": 416,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.184,
+        "evolution_flashlib_ms": 0.385919,
+        "evolution_tflops": 35.5604,
+        "evolution_flashlib_equiv_tflops": 16.9546,
+        "evolution_speedup": 2.0974,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d416_b4_n8192_k1024_d416",
+        "B": 4,
+        "N": 8192,
+        "D": 416,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.230463,
+        "evolution_flashlib_ms": 0.710015,
+        "evolution_tflops": 121.1354,
+        "evolution_flashlib_equiv_tflops": 39.3193,
+        "evolution_speedup": 3.0808,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_3328_d480_min_boundary_b1_n128_k256_d480",
+        "B": 1,
+        "N": 128,
+        "D": 480,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.177056,
+        "evolution_flashlib_ms": 0.488575,
+        "evolution_tflops": 0.1777,
+        "evolution_flashlib_equiv_tflops": 0.0644,
+        "evolution_speedup": 2.7594,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d480_b1_n256_k256_d480",
+        "B": 1,
+        "N": 256,
+        "D": 480,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.176655,
+        "evolution_flashlib_ms": 0.649151,
+        "evolution_tflops": 0.3561,
+        "evolution_flashlib_equiv_tflops": 0.0969,
+        "evolution_speedup": 3.6747,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d480_b1_n512_k8192_d480",
+        "B": 1,
+        "N": 512,
+        "D": 480,
+        "K": 8192,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.278559,
+        "evolution_flashlib_ms": 32.836689,
+        "evolution_tflops": 14.4548,
+        "evolution_flashlib_equiv_tflops": 0.1226,
+        "evolution_speedup": 117.8803,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_a2f8_d480_highk_request_b1_n896_k4096_d480",
+        "B": 1,
+        "N": 896,
+        "D": 480,
+        "K": 4096,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.274432,
+        "evolution_flashlib_ms": 32.096809,
+        "evolution_tflops": 12.8382,
+        "evolution_flashlib_equiv_tflops": 0.1098,
+        "evolution_speedup": 116.9572,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_5600_d480_random_b1_n1536_k1024_d480",
+        "B": 1,
+        "N": 1536,
+        "D": 480,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.199488,
+        "evolution_flashlib_ms": 0.718975,
+        "evolution_tflops": 7.5691,
+        "evolution_flashlib_equiv_tflops": 2.1001,
+        "evolution_speedup": 3.6041,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_8f09_d480_highk_low_n_b2_n640_k4096_d480",
+        "B": 2,
+        "N": 640,
+        "D": 480,
+        "K": 4096,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.284192,
+        "evolution_flashlib_ms": 1.999325,
+        "evolution_tflops": 17.7104,
+        "evolution_flashlib_equiv_tflops": 2.5174,
+        "evolution_speedup": 7.0351,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d480_b2_n2048_k1024_d480",
+        "B": 2,
+        "N": 2048,
+        "D": 480,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.197919,
+        "evolution_flashlib_ms": 0.672447,
+        "evolution_tflops": 20.3443,
+        "evolution_flashlib_equiv_tflops": 5.9879,
+        "evolution_speedup": 3.3976,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_1d49_d480_smallk_boundary_b2_n2816_k256_d480",
+        "B": 2,
+        "N": 2816,
+        "D": 480,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.178015,
+        "evolution_flashlib_ms": 0.332511,
+        "evolution_tflops": 7.7753,
+        "evolution_flashlib_equiv_tflops": 4.1626,
+        "evolution_speedup": 1.8679,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_9ca0_d480_splitd_large_n_b2_n4096_k512_d480",
+        "B": 2,
+        "N": 4096,
+        "D": 480,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.185087,
+        "evolution_flashlib_ms": 0.447807,
+        "evolution_tflops": 21.7548,
+        "evolution_flashlib_equiv_tflops": 8.9917,
+        "evolution_speedup": 2.4194,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480",
+        "B": 3,
+        "N": 1024,
+        "D": 480,
+        "K": 4096,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.297632,
+        "evolution_flashlib_ms": 1.92259,
+        "evolution_tflops": 40.5857,
+        "evolution_flashlib_equiv_tflops": 6.283,
+        "evolution_speedup": 6.4596,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480",
+        "B": 3,
+        "N": 3200,
+        "D": 480,
+        "K": 256,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.18192,
+        "evolution_flashlib_ms": 0.334224,
+        "evolution_tflops": 12.9689,
+        "evolution_flashlib_equiv_tflops": 7.059,
+        "evolution_speedup": 1.8372,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480",
+        "B": 4,
+        "N": 1664,
+        "D": 480,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.18536,
+        "evolution_flashlib_ms": 0.539839,
+        "evolution_tflops": 17.6497,
+        "evolution_flashlib_equiv_tflops": 6.0602,
+        "evolution_speedup": 2.9124,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "post_d895_d480_b4_n8192_k1024_d480",
+        "B": 4,
+        "N": 8192,
+        "D": 480,
+        "K": 1024,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.24,
+        "evolution_flashlib_ms": 0.733983,
+        "evolution_tflops": 134.2177,
+        "evolution_flashlib_equiv_tflops": 43.8869,
+        "evolution_speedup": 3.0583,
+    },
+    {
+        "source": "post_d895_plus_ledgers_124",
+        "label": "adjacent_c44f_d480_boundary_b5_n2048_k512_d480",
+        "B": 5,
+        "N": 2048,
+        "D": 480,
+        "K": 512,
+        "dtype": "bfloat16",
+        "route": "gap_pad_to_supported_seed_v1",
+        "evolution_kernel_ms": 0.185136,
+        "evolution_flashlib_ms": 0.501759,
+        "evolution_tflops": 27.1863,
+        "evolution_flashlib_equiv_tflops": 10.031,
+        "evolution_speedup": 2.7102,
+    },
+]
diff --git a/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200.py b/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200.py
new file mode 100644
index 00000000..72cb364a
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200.py
@@ -0,0 +1,227 @@
+from __future__ import annotations
+
+from typing import Any
+
+import torch
+import triton
+import triton.language as tl
+
+
+def _next_pow2(v: int) -> int:
+    if v <= 1:
+        return 1
+    return 1 << (v - 1).bit_length()
+
+
+def _pad_d(dim: int) -> int:
+    return max(16, _next_pow2(int(dim)))
+
+
+def h200_small_d_config(n_points: int, n_clusters: int, dim: int, dtype: Any) -> dict[str, int]:
+    """Flash-KMeans H200 fp16/bf16 small-D heuristic.
+
+    This is copied from flash-kmeans' H200 heuristic and intentionally ignores
+    the local GPU name. The benchmark uses it as the default Triton baseline
+    even on B200/B300 so the comparison is stable and matches the MR audit.
+    """
+
+    if dtype not in {torch.float16, torch.bfloat16}:
+        raise ValueError(f"H200 baseline in this benchmark expects fp16/bf16, got {dtype}")
+    if dim > 512:
+        raise ValueError(f"H200 small-D Triton baseline supports D <= 512, got D={dim}")
+
+    block_n = 128
+    block_k = 64
+    num_warps = 4
+    num_stages = 1
+
+    if dim >= 512:
+        block_n = 128
+        block_k = 64
+        num_warps = 8
+        num_stages = 1
+    elif dim >= 256:
+        block_n = 128
+        block_k = 64
+        num_warps = 4
+        num_stages = 2
+    else:
+        if n_clusters >= 4096:
+            block_k = 128
+            if dim >= 128:
+                num_warps = 8
+                num_stages = 2
+            else:
+                num_warps = 4
+                num_stages = 4
+        else:
+            block_k = 64
+            num_warps = 4
+            num_stages = 1
+
+    if dim <= 64 and n_clusters >= 4096:
+        block_n = 64
+        block_k = 128
+        num_warps = 4
+        num_stages = 4
+
+    if n_points < 65536:
+        block_n = 64
+
+    return {
+        "kernel": "triton_h200_small_d",
+        "BLOCK_N": int(block_n),
+        "BLOCK_K": int(block_k),
+        "D_PAD": int(_pad_d(dim)),
+        "num_warps": int(num_warps),
+        "num_stages": int(num_stages),
+    }
+
+
+@triton.jit
+def _euclid_assign_kernel(
+    x_ptr,
+    c_ptr,
+    x_sq_ptr,
+    c_sq_ptr,
+    out_ptr,
+    B: tl.constexpr,
+    N: tl.constexpr,
+    K: tl.constexpr,
+    D: tl.constexpr,
+    stride_x_b: tl.constexpr,
+    stride_x_n: tl.constexpr,
+    stride_x_d: tl.constexpr,
+    stride_c_b: tl.constexpr,
+    stride_c_k: tl.constexpr,
+    stride_c_d: tl.constexpr,
+    stride_xsq_b: tl.constexpr,
+    stride_xsq_n: tl.constexpr,
+    stride_csq_b: tl.constexpr,
+    stride_csq_k: tl.constexpr,
+    stride_out_b: tl.constexpr,
+    stride_out_n: tl.constexpr,
+    BLOCK_N: tl.constexpr,
+    BLOCK_K: tl.constexpr,
+    D_PAD: tl.constexpr,
+):
+    pid_n = tl.program_id(0)
+    pid_b = tl.program_id(1).to(tl.int64)
+
+    n_start = pid_n * BLOCK_N
+    n_offsets = (n_start + tl.arange(0, BLOCK_N)).to(tl.int64)
+    n_mask = n_offsets < N
+    offs_d = tl.arange(0, D_PAD).to(tl.int64)
+    d_mask = offs_d < D
+
+    x_ptrs = (
+        x_ptr
+        + pid_b * stride_x_b
+        + n_offsets[:, None] * stride_x_n
+        + offs_d[None, :] * stride_x_d
+    )
+    x_tile = tl.load(x_ptrs, mask=n_mask[:, None] & d_mask[None, :], other=0.0)
+
+    xsq_ptrs = x_sq_ptr + pid_b * stride_xsq_b + n_offsets * stride_xsq_n
+    x_sq_tile = tl.load(xsq_ptrs, mask=n_mask, other=0.0).to(tl.float32)
+
+    best_dist = tl.full((BLOCK_N,), 3.4e38, tl.float32)
+    best_idx = tl.zeros((BLOCK_N,), tl.int32)
+
+    for k_start in range(0, K, BLOCK_K):
+        k_offsets = (k_start + tl.arange(0, BLOCK_K)).to(tl.int64)
+        k_mask = k_offsets < K
+
+        c_ptrs = (
+            c_ptr
+            + pid_b * stride_c_b
+            + k_offsets[None, :] * stride_c_k
+            + offs_d[:, None] * stride_c_d
+        )
+        c_tile = tl.load(c_ptrs, mask=k_mask[None, :] & d_mask[:, None], other=0.0)
+
+        csq_ptrs = c_sq_ptr + pid_b * stride_csq_b + k_offsets * stride_csq_k
+        c_sq_tile = tl.load(csq_ptrs, mask=k_mask, other=0.0).to(tl.float32)
+
+        cross = tl.dot(x_tile, c_tile).to(tl.float32)
+        dist = x_sq_tile[:, None] + c_sq_tile[None, :] - 2.0 * cross
+        dist = tl.maximum(dist, 0.0)
+        dist = tl.where(k_mask[None, :], dist, 3.4e38)
+
+        curr_min = tl.min(dist, axis=1)
+        curr_idx = tl.argmin(dist, axis=1)
+        update = curr_min < best_dist
+        best_dist = tl.where(update, curr_min, best_dist)
+        best_idx = tl.where(update, k_start + curr_idx, best_idx)
+
+    out_ptrs = out_ptr + pid_b * stride_out_b + n_offsets * stride_out_n
+    tl.store(out_ptrs, best_idx, mask=n_mask)
+
+
+def euclid_assign_triton_h200(
+    x: torch.Tensor,
+    centroids: torch.Tensor,
+    x_sq: torch.Tensor,
+    c_sq: torch.Tensor,
+    *,
+    out: torch.Tensor | None = None,
+) -> tuple[torch.Tensor, dict[str, int]]:
+    """Run Flash-KMeans' Triton Euclidean assign with forced H200 heuristic."""
+
+    if x.ndim != 3 or centroids.ndim != 3:
+        raise ValueError("x and centroids must have shapes [B, N, D] and [B, K, D]")
+    if x.dtype not in {torch.float16, torch.bfloat16}:
+        raise ValueError(f"Triton H200 baseline expects fp16/bf16 inputs, got {x.dtype}")
+    if x.device != centroids.device:
+        raise ValueError("x and centroids must be on the same device")
+    if not x.is_cuda or not centroids.is_cuda:
+        raise ValueError("x and centroids must be CUDA tensors")
+    if not x.is_contiguous() or not centroids.is_contiguous():
+        raise ValueError("x and centroids must be contiguous")
+
+    bsz, n_points, dim = (int(v) for v in x.shape)
+    n_clusters = int(centroids.shape[1])
+    if int(centroids.shape[0]) != bsz or int(centroids.shape[2]) != dim:
+        raise ValueError("x and centroids must have matching B and D dimensions")
+    if out is None:
+        out = torch.empty((bsz, n_points), dtype=torch.int32, device=x.device)
+    if tuple(out.shape) != (bsz, n_points) or out.dtype is not torch.int32:
+        raise ValueError("out must have shape [B, N] and dtype torch.int32")
+
+    cfg = h200_small_d_config(n_points, n_clusters, dim, x.dtype)
+    stride_x_b, stride_x_n, stride_x_d = x.stride()
+    stride_c_b, stride_c_k, stride_c_d = centroids.stride()
+    stride_xsq_b, stride_xsq_n = x_sq.stride()
+    stride_csq_b, stride_csq_k = c_sq.stride()
+    stride_out_b, stride_out_n = out.stride()
+
+    grid = lambda meta: (triton.cdiv(n_points, meta["BLOCK_N"]), bsz)
+    _euclid_assign_kernel[grid](
+        x,
+        centroids,
+        x_sq,
+        c_sq,
+        out,
+        bsz,
+        n_points,
+        n_clusters,
+        dim,
+        stride_x_b,
+        stride_x_n,
+        stride_x_d,
+        stride_c_b,
+        stride_c_k,
+        stride_c_d,
+        stride_xsq_b,
+        stride_xsq_n,
+        stride_csq_b,
+        stride_csq_k,
+        stride_out_b,
+        stride_out_n,
+        BLOCK_N=cfg["BLOCK_N"],
+        BLOCK_K=cfg["BLOCK_K"],
+        D_PAD=cfg["D_PAD"],
+        num_warps=cfg["num_warps"],
+        num_stages=cfg["num_stages"],
+    )
+    return out, cfg
diff --git a/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200_raw_adapter.py b/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200_raw_adapter.py
new file mode 100644
index 00000000..b78efbc9
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/flash_kmeans_triton_h200_raw_adapter.py
@@ -0,0 +1,251 @@
+"""Fair raw-input runtime adapter around the frozen 07cf Triton assignment."""
+
+from __future__ import annotations
+
+from contextlib import contextmanager
+from dataclasses import dataclass, field
+from threading import Condition, RLock
+from typing import Any
+
+from flash_kmeans_triton_h200 import euclid_assign_triton_h200
+
+BASELINE_NAME = "triton_h200_07cf_raw_adapter_v1"
+BASELINE_COMMIT = "07cf2a27928aacf6790c950a265d8b8dc83c87cf"
+PREPROCESS_IMPL = "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm"
+
+
+def _record_stream(stream: Any, *tensors: Any) -> None:
+    """Keep caller and scratch storage allocator-safe after async submission."""
+
+    seen: set[int] = set()
+    for tensor in tensors:
+        identity = id(tensor)
+        if identity in seen:
+            continue
+        seen.add(identity)
+        record_stream = getattr(tensor, "record_stream", None)
+        if callable(record_stream):
+            record_stream(stream)
+
+
+@dataclass
+class _Slot:
+    x_sq: Any
+    c_sq: Any
+    norm_plan: Any
+    lock: RLock = field(default_factory=RLock, repr=False)
+
+
+class TritonH20007cfRawAdapter:
+    """Init-once raw-input adapter around the frozen 07cf assignment kernel.
+
+    The adapter intentionally reuses the candidate's exported pair-row-norm
+    implementation. The frozen 07cf assignment consumes both norm fields,
+    while a candidate route may elide fields that it does not bind; this lane
+    therefore compares complete raw-input operators, not assignment-only
+    stages. Scratch and prepared norm launches are isolated by shape and CUDA
+    stream. Each public call allocates its output before preprocessing, matching
+    ``FlashKMeansAssignRuntime.compute`` ordering and return semantics.
+    """
+
+    def __init__(self, *, device_index: int, arch: str) -> None:
+        self.device_index = int(device_index)
+        self.arch = str(arch)
+        self._slots: dict[tuple[Any, ...], _Slot] = {}
+        self._cache_lock = RLock()
+        self._lifecycle = Condition(RLock())
+        self._active_computes = 0
+        self._clearing = False
+        self._hits = 0
+        self._misses = 0
+
+    @contextmanager
+    def _compute_lifecycle(self):
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            self._active_computes += 1
+        try:
+            yield
+        finally:
+            with self._lifecycle:
+                self._active_computes -= 1
+                if self._active_computes == 0:
+                    self._lifecycle.notify_all()
+
+    def cache_info(self) -> dict[str, int]:
+        with self._cache_lock:
+            return {
+                "size": len(self._slots),
+                "hits": self._hits,
+                "misses": self._misses,
+            }
+
+    def clear(self, *, synchronize: bool = True) -> None:
+        """Exclusively release scratch after admitted submissions finish."""
+
+        import torch
+
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            try:
+                self._clearing = True
+                while self._active_computes:
+                    self._lifecycle.wait()
+                if synchronize:
+                    with torch.cuda.device(self.device_index):
+                        torch.cuda.synchronize()
+                with self._cache_lock:
+                    self._slots.clear()
+                    self._hits = 0
+                    self._misses = 0
+            finally:
+                self._clearing = False
+                self._lifecycle.notify_all()
+
+    def _resolve_stream(self, x: Any, centroids: Any, stream: Any) -> tuple[Any, tuple[Any, ...]]:
+        import torch
+
+        if not all(isinstance(item, torch.Tensor) and item.is_cuda for item in (x, centroids)):
+            raise TypeError("07cf raw adapter inputs must be CUDA torch.Tensor objects")
+        if x.dtype is not torch.bfloat16 or centroids.dtype is not torch.bfloat16:
+            raise TypeError("07cf raw adapter inputs must have bfloat16 dtype")
+        if x.ndim != 3 or centroids.ndim != 3 or not x.is_contiguous() or not centroids.is_contiguous():
+            raise ValueError("07cf raw adapter inputs must be contiguous [B, rows, D] tensors")
+        bsz, n_points, dim = map(int, x.shape)
+        c_bsz, n_clusters, c_dim = map(int, centroids.shape)
+        if (bsz, dim) != (c_bsz, c_dim) or x.device != centroids.device:
+            raise ValueError("07cf raw adapter inputs must have matching batch, feature, and device")
+        input_device_index = x.device.index
+        if input_device_index is None:
+            input_device_index = torch.cuda.current_device()
+        input_device_index = int(input_device_index)
+        if input_device_index != self.device_index:
+            raise ValueError(
+                f"07cf raw adapter targets CUDA device {self.device_index}, got input device {input_device_index}"
+            )
+        with torch.cuda.device(self.device_index):
+            resolved_stream = torch.cuda.current_stream(self.device_index) if stream is None else stream
+        stream_device = getattr(resolved_stream, "device", None)
+        stream_device_index = getattr(stream_device, "index", stream_device)
+        if stream_device_index is not None and int(stream_device_index) != self.device_index:
+            raise ValueError(
+                f"07cf raw adapter stream device {stream_device_index} does not match input device {self.device_index}"
+            )
+        stream_handle = int(resolved_stream.cuda_stream)
+        key = (
+            self.device_index,
+            self.arch,
+            bsz,
+            n_points,
+            n_clusters,
+            dim,
+            str(x.dtype),
+            stream_handle,
+        )
+        return resolved_stream, key
+
+    def _locked_slot(
+        self,
+        key: tuple[Any, ...],
+        x: Any,
+        centroids: Any,
+        *,
+        stream: Any,
+    ) -> tuple[_Slot, bool]:
+        import torch
+        from flashlib_cake_kmeans._row_norm import prepare_bf16_pair_row_norm
+
+        # Miss preparation is serialized under the cache lock. This is a cold
+        # path and prevents two threads from compiling/publishing duplicate
+        # launch plans for the same shape/stream key.
+        with self._cache_lock:
+            slot = self._slots.get(key)
+            cache_hit = slot is not None
+            if slot is None:
+                with torch.cuda.device(self.device_index), torch.cuda.stream(stream):
+                    bsz, n_points, _ = map(int, x.shape)
+                    n_clusters = int(centroids.shape[1])
+                    x_sq = torch.empty((bsz, n_points), dtype=torch.float32, device=x.device)
+                    c_sq = torch.empty((bsz, n_clusters), dtype=torch.float32, device=x.device)
+                    norm_plan = prepare_bf16_pair_row_norm(
+                        x,
+                        centroids,
+                        x_sq,
+                        c_sq,
+                        compute_x=True,
+                        compute_c=True,
+                        arch=self.arch,
+                        stream=stream,
+                    )
+                slot = _Slot(x_sq=x_sq, c_sq=c_sq, norm_plan=norm_plan)
+                self._slots[key] = slot
+                self._misses += 1
+            else:
+                self._hits += 1
+        slot.lock.acquire()
+        return slot, cache_hit
+
+    def compute(
+        self,
+        x: Any,
+        centroids: Any,
+        *,
+        stream: Any = None,
+        return_info: bool = False,
+    ):
+        import torch
+
+        with self._compute_lifecycle():
+            resolved_stream, key = self._resolve_stream(x, centroids, stream)
+            with torch.cuda.device(self.device_index), torch.cuda.stream(resolved_stream):
+                bsz, n_points, _ = map(int, x.shape)
+                out = torch.empty((bsz, n_points), dtype=torch.int32, device=x.device)
+            slot, cache_hit = self._locked_slot(
+                key,
+                x,
+                centroids,
+                stream=resolved_stream,
+            )
+            try:
+                with torch.cuda.device(self.device_index), torch.cuda.stream(resolved_stream):
+                    _record_stream(resolved_stream, x, centroids, slot.x_sq, slot.c_sq, out)
+                    try:
+                        slot.norm_plan.rebind(
+                            x,
+                            centroids,
+                            slot.x_sq,
+                            slot.c_sq,
+                            stream=resolved_stream,
+                        )
+                        slot.norm_plan.launch(stream=resolved_stream)
+                    finally:
+                        # The prepared driver launch must not keep caller-owned
+                        # x/centroids alive after enqueue returns.
+                        slot.norm_plan.release_bound_callers(
+                            slot.x_sq,
+                            stream=resolved_stream,
+                        )
+                    produced_out, config = euclid_assign_triton_h200(
+                        x,
+                        centroids,
+                        slot.x_sq,
+                        slot.c_sq,
+                        out=out,
+                    )
+                    if produced_out is not out:
+                        raise RuntimeError("frozen 07cf assignment did not preserve the adapter-owned output")
+            finally:
+                slot.lock.release()
+        if not return_info:
+            return out
+        return out, {
+            "triton_h200_07cf_config": config,
+            "runtime_cache_hit": cache_hit,
+            "norm_launch_count": 1,
+            "norm_compute_fields": ("x_sq", "c_sq"),
+            "assignment_launch_count": 1,
+            "runtime_launch_count": 2,
+            "stream_handle": int(resolved_stream.cuda_stream),
+        }
diff --git a/cake_exports/kmeans/benchmarks/shape_records.json b/cake_exports/kmeans/benchmarks/shape_records.json
new file mode 100644
index 00000000..cd982b94
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/shape_records.json
@@ -0,0 +1,4458 @@
+[
+  {
+    "label": "d895_expanded_heldout_neighborhood_d80_b2_n2176_k1024_d80",
+    "params": {
+      "B": 2,
+      "D": 80,
+      "K": 1024,
+      "N": 2176,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.7696,
+      "evolution_flashlib_ms": 0.402944,
+      "evolution_kernel_ms": 0.176928,
+      "evolution_speedup": 2.2774,
+      "evolution_tflops": 4.0301,
+      "route": "lowdim_e50c_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_miss_fallback_d128_b1_n1408_k512_d128",
+    "params": {
+      "B": 1,
+      "D": 128,
+      "K": 512,
+      "N": 1408,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.53,
+      "evolution_flashlib_ms": 0.348175,
+      "evolution_kernel_ms": 0.144544,
+      "evolution_speedup": 2.4088,
+      "evolution_tflops": 1.2768,
+      "route": "aligned_v10_fallback",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_forced_fallback_d128_b1_n1664_k256_d128",
+    "params": {
+      "B": 1,
+      "D": 128,
+      "K": 256,
+      "N": 1664,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.3924,
+      "evolution_flashlib_ms": 0.277904,
+      "evolution_kernel_ms": 0.142032,
+      "evolution_speedup": 1.9566,
+      "evolution_tflops": 0.7678,
+      "route": "aligned_v10_fallback",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_boundary_d144_b1_n128_k256_d144",
+    "params": {
+      "B": 1,
+      "D": 144,
+      "K": 256,
+      "N": 128,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.0205,
+      "evolution_flashlib_ms": 0.459647,
+      "evolution_kernel_ms": 0.1664,
+      "evolution_speedup": 2.7623,
+      "evolution_tflops": 0.0567,
+      "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_tail_divisibility_d176_b1_n1152_k512_d176",
+    "params": {
+      "B": 1,
+      "D": 176,
+      "K": 512,
+      "N": 1152,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.5253,
+      "evolution_flashlib_ms": 0.395232,
+      "evolution_kernel_ms": 0.174944,
+      "evolution_speedup": 2.2592,
+      "evolution_tflops": 1.1868,
+      "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_overlap_d192_b1_n1024_k768_d192",
+    "params": {
+      "B": 1,
+      "D": 192,
+      "K": 768,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.6618,
+      "evolution_flashlib_ms": 0.45632,
+      "evolution_kernel_ms": 0.17168,
+      "evolution_speedup": 2.658,
+      "evolution_tflops": 1.759,
+      "route": "d192_paired_repeated_mma_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_random_legal_d320_b1_n1280_k512_d320",
+    "params": {
+      "B": 1,
+      "D": 320,
+      "K": 512,
+      "N": 1280,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.826,
+      "evolution_flashlib_ms": 0.507759,
+      "evolution_kernel_ms": 0.152496,
+      "evolution_speedup": 3.3297,
+      "evolution_tflops": 2.7504,
+      "route": "highd_splitd_single_tile_6fcf_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_request_specific_d448_b1_n1280_k1024_d448",
+    "params": {
+      "B": 1,
+      "D": 448,
+      "K": 1024,
+      "N": 1280,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.7411,
+      "evolution_flashlib_ms": 0.674512,
+      "evolution_kernel_ms": 0.173743,
+      "evolution_speedup": 3.8822,
+      "evolution_tflops": 6.7594,
+      "route": "highd_splitd_single_tile_6fcf_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_request_specific_d512_splitk_b1_n512_k8192_d512",
+    "params": {
+      "B": 1,
+      "D": 512,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1375,
+      "evolution_flashlib_ms": 31.230383,
+      "evolution_kernel_ms": 0.257392,
+      "evolution_speedup": 121.3339,
+      "evolution_tflops": 16.6865,
+      "route": "flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_paired_b2_n4096_k1024_d16",
+    "params": {
+      "B": 2,
+      "D": 16,
+      "K": 1024,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.8529,
+      "evolution_flashlib_ms": 0.314751,
+      "evolution_kernel_ms": 0.175568,
+      "evolution_speedup": 1.7928,
+      "evolution_tflops": 1.529,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_fallback_b3_n2432_k512_d16",
+    "params": {
+      "B": 3,
+      "D": 16,
+      "K": 512,
+      "N": 2432,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.4098,
+      "evolution_flashlib_ms": 0.291712,
+      "evolution_kernel_ms": 0.127456,
+      "evolution_speedup": 2.2887,
+      "evolution_tflops": 0.9379,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_small_b4_n1024_k512_d16",
+    "params": {
+      "B": 4,
+      "D": 16,
+      "K": 512,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1836,
+      "evolution_flashlib_ms": 0.365599,
+      "evolution_kernel_ms": 0.141568,
+      "evolution_speedup": 2.5825,
+      "evolution_tflops": 0.474,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_large_b8_n32768_k512_d16",
+    "params": {
+      "B": 8,
+      "D": 16,
+      "K": 512,
+      "N": 32768,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 13.0308,
+      "evolution_flashlib_ms": 0.3296,
+      "evolution_kernel_ms": 0.234416,
+      "evolution_speedup": 1.406,
+      "evolution_tflops": 18.322,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_hugek_b1_n512_k8192_d32",
+    "params": {
+      "B": 1,
+      "D": 32,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1923,
+      "evolution_flashlib_ms": 1.396063,
+      "evolution_kernel_ms": 0.224064,
+      "evolution_speedup": 6.2306,
+      "evolution_tflops": 1.198,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_paired_b2_n4096_k1024_d32",
+    "params": {
+      "B": 2,
+      "D": 32,
+      "K": 1024,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.6899,
+      "evolution_flashlib_ms": 0.317696,
+      "evolution_kernel_ms": 0.176672,
+      "evolution_speedup": 1.7982,
+      "evolution_tflops": 3.0388,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
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+      "evolution_flashlib_ms": 0.649151,
+      "evolution_kernel_ms": 0.176655,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 3.6747,
+      "evolution_tflops": 0.3561
+    }
+  },
+  {
+    "label": "post_d895_d480_b1_n512_k8192_d480",
+    "params": {
+      "B": 1,
+      "D": 480,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "seed": 248003,
+      "source": "high_k_low_n"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 0.1226,
+      "evolution_flashlib_ms": 32.836689,
+      "evolution_kernel_ms": 0.278559,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 117.8803,
+      "evolution_tflops": 14.4548
+    }
+  },
+  {
+    "label": "adjacent_a2f8_d480_highk_request_b1_n896_k4096_d480",
+    "params": {
+      "B": 1,
+      "D": 480,
+      "K": 4096,
+      "N": 896,
+      "dtype": "bfloat16",
+      "seed": 1028480,
+      "source": "request_specific"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 0.1098,
+      "evolution_flashlib_ms": 32.096809,
+      "evolution_kernel_ms": 0.274432,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 116.9572,
+      "evolution_tflops": 12.8382
+    }
+  },
+  {
+    "label": "adjacent_5600_d480_random_b1_n1536_k1024_d480",
+    "params": {
+      "B": 1,
+      "D": 480,
+      "K": 1024,
+      "N": 1536,
+      "dtype": "bfloat16",
+      "seed": 5604801,
+      "source": "random_legal"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 2.1001,
+      "evolution_flashlib_ms": 0.718975,
+      "evolution_kernel_ms": 0.199488,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 3.6041,
+      "evolution_tflops": 7.5691
+    }
+  },
+  {
+    "label": "adjacent_8f09_d480_highk_low_n_b2_n640_k4096_d480",
+    "params": {
+      "B": 2,
+      "D": 480,
+      "K": 4096,
+      "N": 640,
+      "dtype": "bfloat16",
+      "seed": 8094801,
+      "source": "request_specific"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 2.5174,
+      "evolution_flashlib_ms": 1.999325,
+      "evolution_kernel_ms": 0.284192,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 7.0351,
+      "evolution_tflops": 17.7104
+    }
+  },
+  {
+    "label": "post_d895_d480_b2_n2048_k1024_d480",
+    "params": {
+      "B": 2,
+      "D": 480,
+      "K": 1024,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "seed": 248001,
+      "source": "new_high_gap"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 5.9879,
+      "evolution_flashlib_ms": 0.672447,
+      "evolution_kernel_ms": 0.197919,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 3.3976,
+      "evolution_tflops": 20.3443
+    }
+  },
+  {
+    "label": "adjacent_1d49_d480_smallk_boundary_b2_n2816_k256_d480",
+    "params": {
+      "B": 2,
+      "D": 480,
+      "K": 256,
+      "N": 2816,
+      "dtype": "bfloat16",
+      "seed": 1494801,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 4.1626,
+      "evolution_flashlib_ms": 0.332511,
+      "evolution_kernel_ms": 0.178015,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 1.8679,
+      "evolution_tflops": 7.7753
+    }
+  },
+  {
+    "label": "adjacent_9ca0_d480_splitd_large_n_b2_n4096_k512_d480",
+    "params": {
+      "B": 2,
+      "D": 480,
+      "K": 512,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "seed": 948005,
+      "source": "random_legal"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 8.9917,
+      "evolution_flashlib_ms": 0.447807,
+      "evolution_kernel_ms": 0.185087,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 2.4194,
+      "evolution_tflops": 21.7548
+    }
+  },
+  {
+    "label": "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480",
+    "params": {
+      "B": 3,
+      "D": 480,
+      "K": 4096,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "seed": 9548001,
+      "source": "heldout_neighborhood"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 6.283,
+      "evolution_flashlib_ms": 1.92259,
+      "evolution_kernel_ms": 0.297632,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 6.4596,
+      "evolution_tflops": 40.5857
+    }
+  },
+  {
+    "label": "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480",
+    "params": {
+      "B": 3,
+      "D": 480,
+      "K": 256,
+      "N": 3200,
+      "dtype": "bfloat16",
+      "seed": 9004801,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 7.059,
+      "evolution_flashlib_ms": 0.334224,
+      "evolution_kernel_ms": 0.18192,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 1.8372,
+      "evolution_tflops": 12.9689
+    }
+  },
+  {
+    "label": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480",
+    "params": {
+      "B": 4,
+      "D": 480,
+      "K": 512,
+      "N": 1664,
+      "dtype": "bfloat16",
+      "seed": 6848001,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 6.0602,
+      "evolution_flashlib_ms": 0.539839,
+      "evolution_kernel_ms": 0.18536,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 2.9124,
+      "evolution_tflops": 17.6497
+    }
+  },
+  {
+    "label": "post_d895_d480_b4_n8192_k1024_d480",
+    "params": {
+      "B": 4,
+      "D": 480,
+      "K": 1024,
+      "N": 8192,
+      "dtype": "bfloat16",
+      "seed": 248002,
+      "source": "new_high_gap"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 43.8869,
+      "evolution_flashlib_ms": 0.733983,
+      "evolution_kernel_ms": 0.24,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 3.0583,
+      "evolution_tflops": 134.2177
+    }
+  },
+  {
+    "label": "adjacent_c44f_d480_boundary_b5_n2048_k512_d480",
+    "params": {
+      "B": 5,
+      "D": 480,
+      "K": 512,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "seed": 4448001,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 10.031,
+      "evolution_flashlib_ms": 0.501759,
+      "evolution_kernel_ms": 0.185136,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 2.7102,
+      "evolution_tflops": 27.1863
+    }
+  }
+]
diff --git a/cake_exports/kmeans/benchmarks/workload.py b/cake_exports/kmeans/benchmarks/workload.py
new file mode 100644
index 00000000..dff45603
--- /dev/null
+++ b/cake_exports/kmeans/benchmarks/workload.py
@@ -0,0 +1,29 @@
+"""Workload adapter for semantic correctness and per-shape performance.
+
+Replace this template or pass ``--benchmark-adapter`` to the Cake exporter.
+The exported repository never needs Weave IR: this module calls its public
+Python API and provides an independent reference implementation.
+"""
+
+from __future__ import annotations
+
+from typing import Any
+
+CONFIGURED = False
+SHAPES: list[dict[str, Any]] = []
+
+
+def make_case(package: Any, shape: dict[str, Any]) -> dict[str, Any]:
+    """Return run/reference/compare callables and optional work estimates.
+
+    Required keys in the returned mapping:
+      run: zero-argument callable invoking the exported semantic API
+      reference: zero-argument callable computing independent expected output
+      compare: callable(actual, expected) returning bool or {"passed": bool, ...}
+
+    Optional keys:
+      flops: useful floating-point operations for TFLOPS reporting
+      bytes: useful bytes moved for GB/s reporting
+      metrics: static metadata copied into the result
+    """
+    raise NotImplementedError("configure benchmarks/workload.py before running shape benchmarks")
diff --git a/cake_exports/kmeans/pyproject.toml b/cake_exports/kmeans/pyproject.toml
new file mode 100644
index 00000000..331d7bb4
--- /dev/null
+++ b/cake_exports/kmeans/pyproject.toml
@@ -0,0 +1,40 @@
+[build-system]
+requires = ["setuptools>=68", "wheel"]
+build-backend = "setuptools.build_meta"
+
+[project]
+name = "kmeans"
+version = "0.1.0"
+requires-python = ">=3.11"
+dependencies = [
+    "cuda-python",
+    "torch",
+]
+
+[project.optional-dependencies]
+test = [
+    "pytest",
+]
+benchmark = [
+    "cupti-python",
+    "cuda-pathfinder",
+    "nvidia-cuda-cupti",
+    "pytest",
+    "triton",
+]
+tvm-ffi = [
+    "cake-std==0.1.13.dev20260704+g7b8dbc8",
+]
+
+[tool.pytest.ini_options]
+markers = [
+    "export_validation_shape: one declared contract shape counted by the fail-closed publication gate",
+    "gpu: requires a CUDA GPU",
+]
+
+[tool.setuptools.packages.find]
+where = ["src"]
+
+[tool.setuptools.package-data]
+"flashlib_cake_kmeans" = ["*.json", "*.cu", "cuda/*.cu"]
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/__init__.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/__init__.py
new file mode 100644
index 00000000..54f0018b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/__init__.py
@@ -0,0 +1,1455 @@
+from .kernels import (
+    KERNELS,
+    ExportedKernel,
+    get_kernel,
+    dispatch_kernel_0000,
+    dispatch_kernel_0001,
+    dispatch_kernel_0002,
+    dispatch_kernel_0003,
+    dispatch_kernel_0004,
+    dispatch_kernel_0005,
+    dispatch_kernel_0006,
+    dispatch_kernel_0007,
+    dispatch_kernel_0008,
+    dispatch_kernel_0009,
+    dispatch_kernel_0010,
+    dispatch_kernel_0011,
+    dispatch_kernel_0012,
+    dispatch_kernel_0013,
+    dispatch_kernel_0014,
+    dispatch_kernel_0015,
+    dispatch_kernel_0016,
+    dispatch_kernel_0017,
+    dispatch_kernel_0018,
+    dispatch_kernel_0019,
+    dispatch_kernel_0020,
+    dispatch_kernel_0021,
+    dispatch_kernel_0022,
+    dispatch_kernel_0023,
+    dispatch_kernel_0024,
+    dispatch_kernel_0025,
+    dispatch_kernel_0026,
+    dispatch_kernel_0027,
+    dispatch_kernel_0028,
+    dispatch_kernel_0029,
+    dispatch_kernel_0030,
+    dispatch_kernel_0031,
+    dispatch_kernel_0032,
+    dispatch_kernel_0033,
+    dispatch_kernel_0034,
+    dispatch_kernel_0035,
+    dispatch_kernel_0036,
+    dispatch_kernel_0037,
+    dispatch_kernel_0038,
+    dispatch_kernel_0039,
+    dispatch_kernel_0040,
+    dispatch_kernel_0041,
+    dispatch_kernel_0042,
+    dispatch_kernel_0043,
+    dispatch_kernel_0044,
+    dispatch_kernel_0045,
+    dispatch_kernel_0046,
+    dispatch_kernel_0047,
+    dispatch_kernel_0048,
+    dispatch_kernel_0049,
+    dispatch_kernel_0050,
+    dispatch_kernel_0051,
+    dispatch_kernel_0052,
+    dispatch_kernel_0053,
+    dispatch_kernel_0054,
+    dispatch_kernel_0055,
+    dispatch_kernel_0056,
+    dispatch_kernel_0057,
+    dispatch_kernel_0058,
+    dispatch_kernel_0059,
+    dispatch_kernel_0060,
+    dispatch_kernel_0061,
+    dispatch_kernel_0062,
+    dispatch_kernel_0063,
+    dispatch_kernel_0064,
+    dispatch_kernel_0065,
+    dispatch_kernel_0066,
+    dispatch_kernel_0067,
+    dispatch_kernel_0068,
+    dispatch_kernel_0069,
+    dispatch_kernel_0070,
+    dispatch_kernel_0071,
+    dispatch_kernel_0072,
+    dispatch_kernel_0073,
+    dispatch_kernel_0074,
+    dispatch_kernel_0075,
+    dispatch_kernel_0076,
+    dispatch_kernel_0077,
+    dispatch_kernel_0078,
+    dispatch_kernel_0079,
+    dispatch_kernel_0080,
+    dispatch_kernel_0081,
+    dispatch_kernel_0082,
+    dispatch_kernel_0083,
+    dispatch_kernel_0084,
+    dispatch_kernel_0085,
+    dispatch_kernel_0086,
+    dispatch_kernel_0087,
+    dispatch_kernel_0088,
+    dispatch_kernel_0089,
+    dispatch_kernel_0090,
+    dispatch_kernel_0091,
+    dispatch_kernel_0092,
+    dispatch_kernel_0093,
+    dispatch_kernel_0094,
+    dispatch_kernel_0095,
+    dispatch_kernel_0096,
+    dispatch_kernel_0097,
+    dispatch_kernel_0098,
+    dispatch_kernel_0099,
+    dispatch_kernel_0100,
+    dispatch_kernel_0101,
+    dispatch_kernel_0102,
+    dispatch_kernel_0103,
+    dispatch_kernel_0104,
+    dispatch_kernel_0105,
+    dispatch_kernel_0106,
+    dispatch_kernel_0107,
+    dispatch_kernel_0108,
+    dispatch_kernel_0109,
+    dispatch_kernel_0110,
+    dispatch_kernel_0111,
+    dispatch_kernel_0112,
+    dispatch_kernel_0113,
+    dispatch_kernel_0114,
+    dispatch_kernel_0115,
+    dispatch_kernel_0116,
+    dispatch_kernel_0117,
+    dispatch_kernel_0118,
+    dispatch_kernel_0119,
+    dispatch_kernel_0120,
+    dispatch_kernel_0121,
+    dispatch_kernel_0122,
+    dispatch_kernel_0123,
+    dispatch_kernel_0124,
+    dispatch_kernel_0125,
+    dispatch_kernel_0126,
+    dispatch_kernel_0127,
+    dispatch_kernel_0128,
+    dispatch_kernel_0129,
+    dispatch_kernel_0130,
+    dispatch_kernel_0131,
+    dispatch_kernel_0132,
+    dispatch_kernel_0133,
+    dispatch_kernel_0134,
+    dispatch_kernel_0135,
+    dispatch_kernel_0136,
+    dispatch_kernel_0137,
+    dispatch_kernel_0138,
+    dispatch_kernel_0139,
+    dispatch_kernel_0140,
+    dispatch_kernel_0141,
+    dispatch_kernel_0142,
+    dispatch_kernel_0143,
+    dispatch_kernel_0144,
+    dispatch_kernel_0145,
+    dispatch_kernel_0146,
+    dispatch_kernel_0147,
+    dispatch_kernel_0148,
+    dispatch_kernel_0149,
+    dispatch_kernel_0150,
+    dispatch_kernel_0151,
+    dispatch_kernel_0152,
+    dispatch_kernel_0153,
+    dispatch_kernel_0154,
+    dispatch_kernel_0155,
+    dispatch_kernel_0156,
+    dispatch_kernel_0157,
+    dispatch_kernel_0158,
+    dispatch_kernel_0159,
+    dispatch_kernel_0160,
+    dispatch_kernel_0161,
+    dispatch_kernel_0162,
+    dispatch_kernel_0163,
+    dispatch_kernel_0164,
+    dispatch_kernel_0165,
+    dispatch_kernel_0166,
+    dispatch_kernel_0167,
+    dispatch_kernel_0168,
+    dispatch_kernel_0169,
+    dispatch_kernel_0170,
+    dispatch_kernel_0171,
+    dispatch_kernel_0172,
+    dispatch_kernel_0173,
+    dispatch_kernel_0174,
+    dispatch_kernel_0175,
+    dispatch_kernel_0176,
+    dispatch_kernel_0177,
+    dispatch_kernel_0178,
+    dispatch_kernel_0179,
+    dispatch_kernel_0180,
+    dispatch_kernel_0181,
+    dispatch_kernel_0182,
+    dispatch_kernel_0183,
+    dispatch_kernel_0184,
+    dispatch_kernel_0185,
+    dispatch_kernel_0186,
+    dispatch_kernel_0187,
+    dispatch_kernel_0188,
+    dispatch_kernel_0189,
+    dispatch_kernel_0190,
+    dispatch_kernel_0191,
+    dispatch_kernel_0192,
+    dispatch_kernel_0193,
+    dispatch_kernel_0194,
+    dispatch_kernel_0195,
+    dispatch_kernel_0196,
+    dispatch_kernel_0197,
+    dispatch_kernel_0198,
+    dispatch_kernel_0199,
+    dispatch_kernel_0200,
+    dispatch_kernel_0201,
+    dispatch_kernel_0202,
+    dispatch_kernel_0203,
+    dispatch_kernel_0204,
+    dispatch_kernel_0205,
+    dispatch_kernel_0206,
+    dispatch_kernel_0207,
+    dispatch_kernel_0208,
+    dispatch_kernel_0209,
+    dispatch_kernel_0210,
+    dispatch_kernel_0211,
+    dispatch_kernel_0212,
+    dispatch_kernel_0213,
+    dispatch_kernel_0214,
+    dispatch_kernel_0215,
+    dispatch_kernel_0216,
+    dispatch_kernel_0217,
+    dispatch_kernel_0218,
+    dispatch_kernel_0219,
+    dispatch_kernel_0220,
+    dispatch_kernel_0221,
+    dispatch_kernel_0222,
+    dispatch_kernel_0223,
+    dispatch_kernel_0224,
+    dispatch_kernel_0225,
+    dispatch_kernel_0226,
+    dispatch_kernel_0227,
+    dispatch_kernel_0228,
+    dispatch_kernel_0229,
+    dispatch_kernel_0230,
+    dispatch_kernel_0231,
+    dispatch_kernel_0232,
+    dispatch_kernel_0233,
+    dispatch_kernel_0234,
+    dispatch_kernel_0235,
+    dispatch_kernel_0236,
+    dispatch_kernel_0237,
+    dispatch_kernel_0238,
+    dispatch_kernel_0239,
+    dispatch_kernel_0240,
+    dispatch_kernel_0241,
+    dispatch_kernel_0242,
+    dispatch_kernel_0243,
+    dispatch_kernel_0244,
+    dispatch_kernel_0245,
+    dispatch_kernel_0246,
+    dispatch_kernel_0247,
+    dispatch_kernel_0248,
+    dispatch_kernel_0249,
+    dispatch_kernel_0250,
+    dispatch_kernel_0251,
+    dispatch_kernel_0252,
+    dispatch_kernel_0253,
+    dispatch_kernel_0254,
+    dispatch_kernel_0255,
+    dispatch_kernel_0256,
+    dispatch_kernel_0257,
+    dispatch_kernel_0258,
+    dispatch_kernel_0259,
+    dispatch_kernel_0260,
+    dispatch_kernel_0261,
+    dispatch_kernel_0262,
+    dispatch_kernel_0263,
+    dispatch_kernel_0264,
+    dispatch_kernel_0265,
+    dispatch_kernel_0266,
+    dispatch_kernel_0267,
+    dispatch_kernel_0268,
+    dispatch_kernel_0269,
+    dispatch_kernel_0270,
+    dispatch_kernel_0271,
+    dispatch_kernel_0272,
+    dispatch_kernel_0273,
+    dispatch_kernel_0274,
+    dispatch_kernel_0275,
+    dispatch_kernel_0276,
+    dispatch_kernel_0277,
+    dispatch_kernel_0278,
+    dispatch_kernel_0279,
+    dispatch_kernel_0280,
+    dispatch_kernel_0281,
+    dispatch_kernel_0282,
+    dispatch_kernel_0283,
+    dispatch_kernel_0284,
+    dispatch_kernel_0285,
+    dispatch_kernel_0286,
+    dispatch_kernel_0287,
+    dispatch_kernel_0288,
+    dispatch_kernel_0289,
+    dispatch_kernel_0290,
+    dispatch_kernel_0291,
+    dispatch_kernel_0292,
+    dispatch_kernel_0293,
+    dispatch_kernel_0294,
+    dispatch_kernel_0295,
+    dispatch_kernel_0296,
+    dispatch_kernel_0297,
+    dispatch_kernel_0298,
+    dispatch_kernel_0299,
+    dispatch_kernel_0300,
+    dispatch_kernel_0301,
+    dispatch_kernel_0302,
+    dispatch_kernel_0303,
+    dispatch_kernel_0304,
+    dispatch_kernel_0305,
+    dispatch_kernel_0306,
+    dispatch_kernel_0307,
+    dispatch_kernel_0308,
+    dispatch_kernel_0309,
+    dispatch_kernel_0310,
+    dispatch_kernel_0311,
+    dispatch_kernel_0312,
+    dispatch_kernel_0313,
+    dispatch_kernel_0314,
+    dispatch_kernel_0315,
+    dispatch_kernel_0316,
+    dispatch_kernel_0317,
+    dispatch_kernel_0318,
+    dispatch_kernel_0319,
+    dispatch_kernel_0320,
+    dispatch_kernel_0321,
+    dispatch_kernel_0322,
+    dispatch_kernel_0323,
+    dispatch_kernel_0324,
+    dispatch_kernel_0325,
+    dispatch_kernel_0326,
+    dispatch_kernel_0327,
+    dispatch_kernel_0328,
+    dispatch_kernel_0329,
+    dispatch_kernel_0330,
+    dispatch_kernel_0331,
+    dispatch_kernel_0332,
+    dispatch_kernel_0333,
+    dispatch_kernel_0334,
+    dispatch_kernel_0335,
+    dispatch_kernel_0336,
+    dispatch_kernel_0337,
+    dispatch_kernel_0338,
+    dispatch_kernel_0339,
+    dispatch_kernel_0340,
+    dispatch_kernel_0341,
+    dispatch_kernel_0342,
+    dispatch_kernel_0343,
+    dispatch_kernel_0344,
+    dispatch_kernel_0345,
+    dispatch_kernel_0346,
+    dispatch_kernel_0347,
+    dispatch_kernel_0348,
+    dispatch_kernel_0349,
+    dispatch_kernel_0350,
+    dispatch_kernel_0351,
+    dispatch_kernel_0352,
+    dispatch_kernel_0353,
+    dispatch_kernel_0354,
+    dispatch_kernel_0355,
+    dispatch_kernel_0356,
+    dispatch_kernel_0357,
+    launch_dispatch_kernel_0000,
+    launch_dispatch_kernel_0001,
+    launch_dispatch_kernel_0002,
+    launch_dispatch_kernel_0003,
+    launch_dispatch_kernel_0004,
+    launch_dispatch_kernel_0005,
+    launch_dispatch_kernel_0006,
+    launch_dispatch_kernel_0007,
+    launch_dispatch_kernel_0008,
+    launch_dispatch_kernel_0009,
+    launch_dispatch_kernel_0010,
+    launch_dispatch_kernel_0011,
+    launch_dispatch_kernel_0012,
+    launch_dispatch_kernel_0013,
+    launch_dispatch_kernel_0014,
+    launch_dispatch_kernel_0015,
+    launch_dispatch_kernel_0016,
+    launch_dispatch_kernel_0017,
+    launch_dispatch_kernel_0018,
+    launch_dispatch_kernel_0019,
+    launch_dispatch_kernel_0020,
+    launch_dispatch_kernel_0021,
+    launch_dispatch_kernel_0022,
+    launch_dispatch_kernel_0023,
+    launch_dispatch_kernel_0024,
+    launch_dispatch_kernel_0025,
+    launch_dispatch_kernel_0026,
+    launch_dispatch_kernel_0027,
+    launch_dispatch_kernel_0028,
+    launch_dispatch_kernel_0029,
+    launch_dispatch_kernel_0030,
+    launch_dispatch_kernel_0031,
+    launch_dispatch_kernel_0032,
+    launch_dispatch_kernel_0033,
+    launch_dispatch_kernel_0034,
+    launch_dispatch_kernel_0035,
+    launch_dispatch_kernel_0036,
+    launch_dispatch_kernel_0037,
+    launch_dispatch_kernel_0038,
+    launch_dispatch_kernel_0039,
+    launch_dispatch_kernel_0040,
+    launch_dispatch_kernel_0041,
+    launch_dispatch_kernel_0042,
+    launch_dispatch_kernel_0043,
+    launch_dispatch_kernel_0044,
+    launch_dispatch_kernel_0045,
+    launch_dispatch_kernel_0046,
+    launch_dispatch_kernel_0047,
+    launch_dispatch_kernel_0048,
+    launch_dispatch_kernel_0049,
+    launch_dispatch_kernel_0050,
+    launch_dispatch_kernel_0051,
+    launch_dispatch_kernel_0052,
+    launch_dispatch_kernel_0053,
+    launch_dispatch_kernel_0054,
+    launch_dispatch_kernel_0055,
+    launch_dispatch_kernel_0056,
+    launch_dispatch_kernel_0057,
+    launch_dispatch_kernel_0058,
+    launch_dispatch_kernel_0059,
+    launch_dispatch_kernel_0060,
+    launch_dispatch_kernel_0061,
+    launch_dispatch_kernel_0062,
+    launch_dispatch_kernel_0063,
+    launch_dispatch_kernel_0064,
+    launch_dispatch_kernel_0065,
+    launch_dispatch_kernel_0066,
+    launch_dispatch_kernel_0067,
+    launch_dispatch_kernel_0068,
+    launch_dispatch_kernel_0069,
+    launch_dispatch_kernel_0070,
+    launch_dispatch_kernel_0071,
+    launch_dispatch_kernel_0072,
+    launch_dispatch_kernel_0073,
+    launch_dispatch_kernel_0074,
+    launch_dispatch_kernel_0075,
+    launch_dispatch_kernel_0076,
+    launch_dispatch_kernel_0077,
+    launch_dispatch_kernel_0078,
+    launch_dispatch_kernel_0079,
+    launch_dispatch_kernel_0080,
+    launch_dispatch_kernel_0081,
+    launch_dispatch_kernel_0082,
+    launch_dispatch_kernel_0083,
+    launch_dispatch_kernel_0084,
+    launch_dispatch_kernel_0085,
+    launch_dispatch_kernel_0086,
+    launch_dispatch_kernel_0087,
+    launch_dispatch_kernel_0088,
+    launch_dispatch_kernel_0089,
+    launch_dispatch_kernel_0090,
+    launch_dispatch_kernel_0091,
+    launch_dispatch_kernel_0092,
+    launch_dispatch_kernel_0093,
+    launch_dispatch_kernel_0094,
+    launch_dispatch_kernel_0095,
+    launch_dispatch_kernel_0096,
+    launch_dispatch_kernel_0097,
+    launch_dispatch_kernel_0098,
+    launch_dispatch_kernel_0099,
+    launch_dispatch_kernel_0100,
+    launch_dispatch_kernel_0101,
+    launch_dispatch_kernel_0102,
+    launch_dispatch_kernel_0103,
+    launch_dispatch_kernel_0104,
+    launch_dispatch_kernel_0105,
+    launch_dispatch_kernel_0106,
+    launch_dispatch_kernel_0107,
+    launch_dispatch_kernel_0108,
+    launch_dispatch_kernel_0109,
+    launch_dispatch_kernel_0110,
+    launch_dispatch_kernel_0111,
+    launch_dispatch_kernel_0112,
+    launch_dispatch_kernel_0113,
+    launch_dispatch_kernel_0114,
+    launch_dispatch_kernel_0115,
+    launch_dispatch_kernel_0116,
+    launch_dispatch_kernel_0117,
+    launch_dispatch_kernel_0118,
+    launch_dispatch_kernel_0119,
+    launch_dispatch_kernel_0120,
+    launch_dispatch_kernel_0121,
+    launch_dispatch_kernel_0122,
+    launch_dispatch_kernel_0123,
+    launch_dispatch_kernel_0124,
+    launch_dispatch_kernel_0125,
+    launch_dispatch_kernel_0126,
+    launch_dispatch_kernel_0127,
+    launch_dispatch_kernel_0128,
+    launch_dispatch_kernel_0129,
+    launch_dispatch_kernel_0130,
+    launch_dispatch_kernel_0131,
+    launch_dispatch_kernel_0132,
+    launch_dispatch_kernel_0133,
+    launch_dispatch_kernel_0134,
+    launch_dispatch_kernel_0135,
+    launch_dispatch_kernel_0136,
+    launch_dispatch_kernel_0137,
+    launch_dispatch_kernel_0138,
+    launch_dispatch_kernel_0139,
+    launch_dispatch_kernel_0140,
+    launch_dispatch_kernel_0141,
+    launch_dispatch_kernel_0142,
+    launch_dispatch_kernel_0143,
+    launch_dispatch_kernel_0144,
+    launch_dispatch_kernel_0145,
+    launch_dispatch_kernel_0146,
+    launch_dispatch_kernel_0147,
+    launch_dispatch_kernel_0148,
+    launch_dispatch_kernel_0149,
+    launch_dispatch_kernel_0150,
+    launch_dispatch_kernel_0151,
+    launch_dispatch_kernel_0152,
+    launch_dispatch_kernel_0153,
+    launch_dispatch_kernel_0154,
+    launch_dispatch_kernel_0155,
+    launch_dispatch_kernel_0156,
+    launch_dispatch_kernel_0157,
+    launch_dispatch_kernel_0158,
+    launch_dispatch_kernel_0159,
+    launch_dispatch_kernel_0160,
+    launch_dispatch_kernel_0161,
+    launch_dispatch_kernel_0162,
+    launch_dispatch_kernel_0163,
+    launch_dispatch_kernel_0164,
+    launch_dispatch_kernel_0165,
+    launch_dispatch_kernel_0166,
+    launch_dispatch_kernel_0167,
+    launch_dispatch_kernel_0168,
+    launch_dispatch_kernel_0169,
+    launch_dispatch_kernel_0170,
+    launch_dispatch_kernel_0171,
+    launch_dispatch_kernel_0172,
+    launch_dispatch_kernel_0173,
+    launch_dispatch_kernel_0174,
+    launch_dispatch_kernel_0175,
+    launch_dispatch_kernel_0176,
+    launch_dispatch_kernel_0177,
+    launch_dispatch_kernel_0178,
+    launch_dispatch_kernel_0179,
+    launch_dispatch_kernel_0180,
+    launch_dispatch_kernel_0181,
+    launch_dispatch_kernel_0182,
+    launch_dispatch_kernel_0183,
+    launch_dispatch_kernel_0184,
+    launch_dispatch_kernel_0185,
+    launch_dispatch_kernel_0186,
+    launch_dispatch_kernel_0187,
+    launch_dispatch_kernel_0188,
+    launch_dispatch_kernel_0189,
+    launch_dispatch_kernel_0190,
+    launch_dispatch_kernel_0191,
+    launch_dispatch_kernel_0192,
+    launch_dispatch_kernel_0193,
+    launch_dispatch_kernel_0194,
+    launch_dispatch_kernel_0195,
+    launch_dispatch_kernel_0196,
+    launch_dispatch_kernel_0197,
+    launch_dispatch_kernel_0198,
+    launch_dispatch_kernel_0199,
+    launch_dispatch_kernel_0200,
+    launch_dispatch_kernel_0201,
+    launch_dispatch_kernel_0202,
+    launch_dispatch_kernel_0203,
+    launch_dispatch_kernel_0204,
+    launch_dispatch_kernel_0205,
+    launch_dispatch_kernel_0206,
+    launch_dispatch_kernel_0207,
+    launch_dispatch_kernel_0208,
+    launch_dispatch_kernel_0209,
+    launch_dispatch_kernel_0210,
+    launch_dispatch_kernel_0211,
+    launch_dispatch_kernel_0212,
+    launch_dispatch_kernel_0213,
+    launch_dispatch_kernel_0214,
+    launch_dispatch_kernel_0215,
+    launch_dispatch_kernel_0216,
+    launch_dispatch_kernel_0217,
+    launch_dispatch_kernel_0218,
+    launch_dispatch_kernel_0219,
+    launch_dispatch_kernel_0220,
+    launch_dispatch_kernel_0221,
+    launch_dispatch_kernel_0222,
+    launch_dispatch_kernel_0223,
+    launch_dispatch_kernel_0224,
+    launch_dispatch_kernel_0225,
+    launch_dispatch_kernel_0226,
+    launch_dispatch_kernel_0227,
+    launch_dispatch_kernel_0228,
+    launch_dispatch_kernel_0229,
+    launch_dispatch_kernel_0230,
+    launch_dispatch_kernel_0231,
+    launch_dispatch_kernel_0232,
+    launch_dispatch_kernel_0233,
+    launch_dispatch_kernel_0234,
+    launch_dispatch_kernel_0235,
+    launch_dispatch_kernel_0236,
+    launch_dispatch_kernel_0237,
+    launch_dispatch_kernel_0238,
+    launch_dispatch_kernel_0239,
+    launch_dispatch_kernel_0240,
+    launch_dispatch_kernel_0241,
+    launch_dispatch_kernel_0242,
+    launch_dispatch_kernel_0243,
+    launch_dispatch_kernel_0244,
+    launch_dispatch_kernel_0245,
+    launch_dispatch_kernel_0246,
+    launch_dispatch_kernel_0247,
+    launch_dispatch_kernel_0248,
+    launch_dispatch_kernel_0249,
+    launch_dispatch_kernel_0250,
+    launch_dispatch_kernel_0251,
+    launch_dispatch_kernel_0252,
+    launch_dispatch_kernel_0253,
+    launch_dispatch_kernel_0254,
+    launch_dispatch_kernel_0255,
+    launch_dispatch_kernel_0256,
+    launch_dispatch_kernel_0257,
+    launch_dispatch_kernel_0258,
+    launch_dispatch_kernel_0259,
+    launch_dispatch_kernel_0260,
+    launch_dispatch_kernel_0261,
+    launch_dispatch_kernel_0262,
+    launch_dispatch_kernel_0263,
+    launch_dispatch_kernel_0264,
+    launch_dispatch_kernel_0265,
+    launch_dispatch_kernel_0266,
+    launch_dispatch_kernel_0267,
+    launch_dispatch_kernel_0268,
+    launch_dispatch_kernel_0269,
+    launch_dispatch_kernel_0270,
+    launch_dispatch_kernel_0271,
+    launch_dispatch_kernel_0272,
+    launch_dispatch_kernel_0273,
+    launch_dispatch_kernel_0274,
+    launch_dispatch_kernel_0275,
+    launch_dispatch_kernel_0276,
+    launch_dispatch_kernel_0277,
+    launch_dispatch_kernel_0278,
+    launch_dispatch_kernel_0279,
+    launch_dispatch_kernel_0280,
+    launch_dispatch_kernel_0281,
+    launch_dispatch_kernel_0282,
+    launch_dispatch_kernel_0283,
+    launch_dispatch_kernel_0284,
+    launch_dispatch_kernel_0285,
+    launch_dispatch_kernel_0286,
+    launch_dispatch_kernel_0287,
+    launch_dispatch_kernel_0288,
+    launch_dispatch_kernel_0289,
+    launch_dispatch_kernel_0290,
+    launch_dispatch_kernel_0291,
+    launch_dispatch_kernel_0292,
+    launch_dispatch_kernel_0293,
+    launch_dispatch_kernel_0294,
+    launch_dispatch_kernel_0295,
+    launch_dispatch_kernel_0296,
+    launch_dispatch_kernel_0297,
+    launch_dispatch_kernel_0298,
+    launch_dispatch_kernel_0299,
+    launch_dispatch_kernel_0300,
+    launch_dispatch_kernel_0301,
+    launch_dispatch_kernel_0302,
+    launch_dispatch_kernel_0303,
+    launch_dispatch_kernel_0304,
+    launch_dispatch_kernel_0305,
+    launch_dispatch_kernel_0306,
+    launch_dispatch_kernel_0307,
+    launch_dispatch_kernel_0308,
+    launch_dispatch_kernel_0309,
+    launch_dispatch_kernel_0310,
+    launch_dispatch_kernel_0311,
+    launch_dispatch_kernel_0312,
+    launch_dispatch_kernel_0313,
+    launch_dispatch_kernel_0314,
+    launch_dispatch_kernel_0315,
+    launch_dispatch_kernel_0316,
+    launch_dispatch_kernel_0317,
+    launch_dispatch_kernel_0318,
+    launch_dispatch_kernel_0319,
+    launch_dispatch_kernel_0320,
+    launch_dispatch_kernel_0321,
+    launch_dispatch_kernel_0322,
+    launch_dispatch_kernel_0323,
+    launch_dispatch_kernel_0324,
+    launch_dispatch_kernel_0325,
+    launch_dispatch_kernel_0326,
+    launch_dispatch_kernel_0327,
+    launch_dispatch_kernel_0328,
+    launch_dispatch_kernel_0329,
+    launch_dispatch_kernel_0330,
+    launch_dispatch_kernel_0331,
+    launch_dispatch_kernel_0332,
+    launch_dispatch_kernel_0333,
+    launch_dispatch_kernel_0334,
+    launch_dispatch_kernel_0335,
+    launch_dispatch_kernel_0336,
+    launch_dispatch_kernel_0337,
+    launch_dispatch_kernel_0338,
+    launch_dispatch_kernel_0339,
+    launch_dispatch_kernel_0340,
+    launch_dispatch_kernel_0341,
+    launch_dispatch_kernel_0342,
+    launch_dispatch_kernel_0343,
+    launch_dispatch_kernel_0344,
+    launch_dispatch_kernel_0345,
+    launch_dispatch_kernel_0346,
+    launch_dispatch_kernel_0347,
+    launch_dispatch_kernel_0348,
+    launch_dispatch_kernel_0349,
+    launch_dispatch_kernel_0350,
+    launch_dispatch_kernel_0351,
+    launch_dispatch_kernel_0352,
+    launch_dispatch_kernel_0353,
+    launch_dispatch_kernel_0354,
+    launch_dispatch_kernel_0355,
+    launch_dispatch_kernel_0356,
+    launch_dispatch_kernel_0357,
+)
+from .tvm_ffi import register_tvm_ffi, tvm_ffi_function_names
+
+__all__ = [
+    'KERNELS',
+    'ExportedKernel',
+    'get_kernel',
+    'dispatch_kernel_0000',
+    'dispatch_kernel_0001',
+    'dispatch_kernel_0002',
+    'dispatch_kernel_0003',
+    'dispatch_kernel_0004',
+    'dispatch_kernel_0005',
+    'dispatch_kernel_0006',
+    'dispatch_kernel_0007',
+    'dispatch_kernel_0008',
+    'dispatch_kernel_0009',
+    'dispatch_kernel_0010',
+    'dispatch_kernel_0011',
+    'dispatch_kernel_0012',
+    'dispatch_kernel_0013',
+    'dispatch_kernel_0014',
+    'dispatch_kernel_0015',
+    'dispatch_kernel_0016',
+    'dispatch_kernel_0017',
+    'dispatch_kernel_0018',
+    'dispatch_kernel_0019',
+    'dispatch_kernel_0020',
+    'dispatch_kernel_0021',
+    'dispatch_kernel_0022',
+    'dispatch_kernel_0023',
+    'dispatch_kernel_0024',
+    'dispatch_kernel_0025',
+    'dispatch_kernel_0026',
+    'dispatch_kernel_0027',
+    'dispatch_kernel_0028',
+    'dispatch_kernel_0029',
+    'dispatch_kernel_0030',
+    'dispatch_kernel_0031',
+    'dispatch_kernel_0032',
+    'dispatch_kernel_0033',
+    'dispatch_kernel_0034',
+    'dispatch_kernel_0035',
+    'dispatch_kernel_0036',
+    'dispatch_kernel_0037',
+    'dispatch_kernel_0038',
+    'dispatch_kernel_0039',
+    'dispatch_kernel_0040',
+    'dispatch_kernel_0041',
+    'dispatch_kernel_0042',
+    'dispatch_kernel_0043',
+    'dispatch_kernel_0044',
+    'dispatch_kernel_0045',
+    'dispatch_kernel_0046',
+    'dispatch_kernel_0047',
+    'dispatch_kernel_0048',
+    'dispatch_kernel_0049',
+    'dispatch_kernel_0050',
+    'dispatch_kernel_0051',
+    'dispatch_kernel_0052',
+    'dispatch_kernel_0053',
+    'dispatch_kernel_0054',
+    'dispatch_kernel_0055',
+    'dispatch_kernel_0056',
+    'dispatch_kernel_0057',
+    'dispatch_kernel_0058',
+    'dispatch_kernel_0059',
+    'dispatch_kernel_0060',
+    'dispatch_kernel_0061',
+    'dispatch_kernel_0062',
+    'dispatch_kernel_0063',
+    'dispatch_kernel_0064',
+    'dispatch_kernel_0065',
+    'dispatch_kernel_0066',
+    'dispatch_kernel_0067',
+    'dispatch_kernel_0068',
+    'dispatch_kernel_0069',
+    'dispatch_kernel_0070',
+    'dispatch_kernel_0071',
+    'dispatch_kernel_0072',
+    'dispatch_kernel_0073',
+    'dispatch_kernel_0074',
+    'dispatch_kernel_0075',
+    'dispatch_kernel_0076',
+    'dispatch_kernel_0077',
+    'dispatch_kernel_0078',
+    'dispatch_kernel_0079',
+    'dispatch_kernel_0080',
+    'dispatch_kernel_0081',
+    'dispatch_kernel_0082',
+    'dispatch_kernel_0083',
+    'dispatch_kernel_0084',
+    'dispatch_kernel_0085',
+    'dispatch_kernel_0086',
+    'dispatch_kernel_0087',
+    'dispatch_kernel_0088',
+    'dispatch_kernel_0089',
+    'dispatch_kernel_0090',
+    'dispatch_kernel_0091',
+    'dispatch_kernel_0092',
+    'dispatch_kernel_0093',
+    'dispatch_kernel_0094',
+    'dispatch_kernel_0095',
+    'dispatch_kernel_0096',
+    'dispatch_kernel_0097',
+    'dispatch_kernel_0098',
+    'dispatch_kernel_0099',
+    'dispatch_kernel_0100',
+    'dispatch_kernel_0101',
+    'dispatch_kernel_0102',
+    'dispatch_kernel_0103',
+    'dispatch_kernel_0104',
+    'dispatch_kernel_0105',
+    'dispatch_kernel_0106',
+    'dispatch_kernel_0107',
+    'dispatch_kernel_0108',
+    'dispatch_kernel_0109',
+    'dispatch_kernel_0110',
+    'dispatch_kernel_0111',
+    'dispatch_kernel_0112',
+    'dispatch_kernel_0113',
+    'dispatch_kernel_0114',
+    'dispatch_kernel_0115',
+    'dispatch_kernel_0116',
+    'dispatch_kernel_0117',
+    'dispatch_kernel_0118',
+    'dispatch_kernel_0119',
+    'dispatch_kernel_0120',
+    'dispatch_kernel_0121',
+    'dispatch_kernel_0122',
+    'dispatch_kernel_0123',
+    'dispatch_kernel_0124',
+    'dispatch_kernel_0125',
+    'dispatch_kernel_0126',
+    'dispatch_kernel_0127',
+    'dispatch_kernel_0128',
+    'dispatch_kernel_0129',
+    'dispatch_kernel_0130',
+    'dispatch_kernel_0131',
+    'dispatch_kernel_0132',
+    'dispatch_kernel_0133',
+    'dispatch_kernel_0134',
+    'dispatch_kernel_0135',
+    'dispatch_kernel_0136',
+    'dispatch_kernel_0137',
+    'dispatch_kernel_0138',
+    'dispatch_kernel_0139',
+    'dispatch_kernel_0140',
+    'dispatch_kernel_0141',
+    'dispatch_kernel_0142',
+    'dispatch_kernel_0143',
+    'dispatch_kernel_0144',
+    'dispatch_kernel_0145',
+    'dispatch_kernel_0146',
+    'dispatch_kernel_0147',
+    'dispatch_kernel_0148',
+    'dispatch_kernel_0149',
+    'dispatch_kernel_0150',
+    'dispatch_kernel_0151',
+    'dispatch_kernel_0152',
+    'dispatch_kernel_0153',
+    'dispatch_kernel_0154',
+    'dispatch_kernel_0155',
+    'dispatch_kernel_0156',
+    'dispatch_kernel_0157',
+    'dispatch_kernel_0158',
+    'dispatch_kernel_0159',
+    'dispatch_kernel_0160',
+    'dispatch_kernel_0161',
+    'dispatch_kernel_0162',
+    'dispatch_kernel_0163',
+    'dispatch_kernel_0164',
+    'dispatch_kernel_0165',
+    'dispatch_kernel_0166',
+    'dispatch_kernel_0167',
+    'dispatch_kernel_0168',
+    'dispatch_kernel_0169',
+    'dispatch_kernel_0170',
+    'dispatch_kernel_0171',
+    'dispatch_kernel_0172',
+    'dispatch_kernel_0173',
+    'dispatch_kernel_0174',
+    'dispatch_kernel_0175',
+    'dispatch_kernel_0176',
+    'dispatch_kernel_0177',
+    'dispatch_kernel_0178',
+    'dispatch_kernel_0179',
+    'dispatch_kernel_0180',
+    'dispatch_kernel_0181',
+    'dispatch_kernel_0182',
+    'dispatch_kernel_0183',
+    'dispatch_kernel_0184',
+    'dispatch_kernel_0185',
+    'dispatch_kernel_0186',
+    'dispatch_kernel_0187',
+    'dispatch_kernel_0188',
+    'dispatch_kernel_0189',
+    'dispatch_kernel_0190',
+    'dispatch_kernel_0191',
+    'dispatch_kernel_0192',
+    'dispatch_kernel_0193',
+    'dispatch_kernel_0194',
+    'dispatch_kernel_0195',
+    'dispatch_kernel_0196',
+    'dispatch_kernel_0197',
+    'dispatch_kernel_0198',
+    'dispatch_kernel_0199',
+    'dispatch_kernel_0200',
+    'dispatch_kernel_0201',
+    'dispatch_kernel_0202',
+    'dispatch_kernel_0203',
+    'dispatch_kernel_0204',
+    'dispatch_kernel_0205',
+    'dispatch_kernel_0206',
+    'dispatch_kernel_0207',
+    'dispatch_kernel_0208',
+    'dispatch_kernel_0209',
+    'dispatch_kernel_0210',
+    'dispatch_kernel_0211',
+    'dispatch_kernel_0212',
+    'dispatch_kernel_0213',
+    'dispatch_kernel_0214',
+    'dispatch_kernel_0215',
+    'dispatch_kernel_0216',
+    'dispatch_kernel_0217',
+    'dispatch_kernel_0218',
+    'dispatch_kernel_0219',
+    'dispatch_kernel_0220',
+    'dispatch_kernel_0221',
+    'dispatch_kernel_0222',
+    'dispatch_kernel_0223',
+    'dispatch_kernel_0224',
+    'dispatch_kernel_0225',
+    'dispatch_kernel_0226',
+    'dispatch_kernel_0227',
+    'dispatch_kernel_0228',
+    'dispatch_kernel_0229',
+    'dispatch_kernel_0230',
+    'dispatch_kernel_0231',
+    'dispatch_kernel_0232',
+    'dispatch_kernel_0233',
+    'dispatch_kernel_0234',
+    'dispatch_kernel_0235',
+    'dispatch_kernel_0236',
+    'dispatch_kernel_0237',
+    'dispatch_kernel_0238',
+    'dispatch_kernel_0239',
+    'dispatch_kernel_0240',
+    'dispatch_kernel_0241',
+    'dispatch_kernel_0242',
+    'dispatch_kernel_0243',
+    'dispatch_kernel_0244',
+    'dispatch_kernel_0245',
+    'dispatch_kernel_0246',
+    'dispatch_kernel_0247',
+    'dispatch_kernel_0248',
+    'dispatch_kernel_0249',
+    'dispatch_kernel_0250',
+    'dispatch_kernel_0251',
+    'dispatch_kernel_0252',
+    'dispatch_kernel_0253',
+    'dispatch_kernel_0254',
+    'dispatch_kernel_0255',
+    'dispatch_kernel_0256',
+    'dispatch_kernel_0257',
+    'dispatch_kernel_0258',
+    'dispatch_kernel_0259',
+    'dispatch_kernel_0260',
+    'dispatch_kernel_0261',
+    'dispatch_kernel_0262',
+    'dispatch_kernel_0263',
+    'dispatch_kernel_0264',
+    'dispatch_kernel_0265',
+    'dispatch_kernel_0266',
+    'dispatch_kernel_0267',
+    'dispatch_kernel_0268',
+    'dispatch_kernel_0269',
+    'dispatch_kernel_0270',
+    'dispatch_kernel_0271',
+    'dispatch_kernel_0272',
+    'dispatch_kernel_0273',
+    'dispatch_kernel_0274',
+    'dispatch_kernel_0275',
+    'dispatch_kernel_0276',
+    'dispatch_kernel_0277',
+    'dispatch_kernel_0278',
+    'dispatch_kernel_0279',
+    'dispatch_kernel_0280',
+    'dispatch_kernel_0281',
+    'dispatch_kernel_0282',
+    'dispatch_kernel_0283',
+    'dispatch_kernel_0284',
+    'dispatch_kernel_0285',
+    'dispatch_kernel_0286',
+    'dispatch_kernel_0287',
+    'dispatch_kernel_0288',
+    'dispatch_kernel_0289',
+    'dispatch_kernel_0290',
+    'dispatch_kernel_0291',
+    'dispatch_kernel_0292',
+    'dispatch_kernel_0293',
+    'dispatch_kernel_0294',
+    'dispatch_kernel_0295',
+    'dispatch_kernel_0296',
+    'dispatch_kernel_0297',
+    'dispatch_kernel_0298',
+    'dispatch_kernel_0299',
+    'dispatch_kernel_0300',
+    'dispatch_kernel_0301',
+    'dispatch_kernel_0302',
+    'dispatch_kernel_0303',
+    'dispatch_kernel_0304',
+    'dispatch_kernel_0305',
+    'dispatch_kernel_0306',
+    'dispatch_kernel_0307',
+    'dispatch_kernel_0308',
+    'dispatch_kernel_0309',
+    'dispatch_kernel_0310',
+    'dispatch_kernel_0311',
+    'dispatch_kernel_0312',
+    'dispatch_kernel_0313',
+    'dispatch_kernel_0314',
+    'dispatch_kernel_0315',
+    'dispatch_kernel_0316',
+    'dispatch_kernel_0317',
+    'dispatch_kernel_0318',
+    'dispatch_kernel_0319',
+    'dispatch_kernel_0320',
+    'dispatch_kernel_0321',
+    'dispatch_kernel_0322',
+    'dispatch_kernel_0323',
+    'dispatch_kernel_0324',
+    'dispatch_kernel_0325',
+    'dispatch_kernel_0326',
+    'dispatch_kernel_0327',
+    'dispatch_kernel_0328',
+    'dispatch_kernel_0329',
+    'dispatch_kernel_0330',
+    'dispatch_kernel_0331',
+    'dispatch_kernel_0332',
+    'dispatch_kernel_0333',
+    'dispatch_kernel_0334',
+    'dispatch_kernel_0335',
+    'dispatch_kernel_0336',
+    'dispatch_kernel_0337',
+    'dispatch_kernel_0338',
+    'dispatch_kernel_0339',
+    'dispatch_kernel_0340',
+    'dispatch_kernel_0341',
+    'dispatch_kernel_0342',
+    'dispatch_kernel_0343',
+    'dispatch_kernel_0344',
+    'dispatch_kernel_0345',
+    'dispatch_kernel_0346',
+    'dispatch_kernel_0347',
+    'dispatch_kernel_0348',
+    'dispatch_kernel_0349',
+    'dispatch_kernel_0350',
+    'dispatch_kernel_0351',
+    'dispatch_kernel_0352',
+    'dispatch_kernel_0353',
+    'dispatch_kernel_0354',
+    'dispatch_kernel_0355',
+    'dispatch_kernel_0356',
+    'dispatch_kernel_0357',
+    'launch_dispatch_kernel_0000',
+    'launch_dispatch_kernel_0001',
+    'launch_dispatch_kernel_0002',
+    'launch_dispatch_kernel_0003',
+    'launch_dispatch_kernel_0004',
+    'launch_dispatch_kernel_0005',
+    'launch_dispatch_kernel_0006',
+    'launch_dispatch_kernel_0007',
+    'launch_dispatch_kernel_0008',
+    'launch_dispatch_kernel_0009',
+    'launch_dispatch_kernel_0010',
+    'launch_dispatch_kernel_0011',
+    'launch_dispatch_kernel_0012',
+    'launch_dispatch_kernel_0013',
+    'launch_dispatch_kernel_0014',
+    'launch_dispatch_kernel_0015',
+    'launch_dispatch_kernel_0016',
+    'launch_dispatch_kernel_0017',
+    'launch_dispatch_kernel_0018',
+    'launch_dispatch_kernel_0019',
+    'launch_dispatch_kernel_0020',
+    'launch_dispatch_kernel_0021',
+    'launch_dispatch_kernel_0022',
+    'launch_dispatch_kernel_0023',
+    'launch_dispatch_kernel_0024',
+    'launch_dispatch_kernel_0025',
+    'launch_dispatch_kernel_0026',
+    'launch_dispatch_kernel_0027',
+    'launch_dispatch_kernel_0028',
+    'launch_dispatch_kernel_0029',
+    'launch_dispatch_kernel_0030',
+    'launch_dispatch_kernel_0031',
+    'launch_dispatch_kernel_0032',
+    'launch_dispatch_kernel_0033',
+    'launch_dispatch_kernel_0034',
+    'launch_dispatch_kernel_0035',
+    'launch_dispatch_kernel_0036',
+    'launch_dispatch_kernel_0037',
+    'launch_dispatch_kernel_0038',
+    'launch_dispatch_kernel_0039',
+    'launch_dispatch_kernel_0040',
+    'launch_dispatch_kernel_0041',
+    'launch_dispatch_kernel_0042',
+    'launch_dispatch_kernel_0043',
+    'launch_dispatch_kernel_0044',
+    'launch_dispatch_kernel_0045',
+    'launch_dispatch_kernel_0046',
+    'launch_dispatch_kernel_0047',
+    'launch_dispatch_kernel_0048',
+    'launch_dispatch_kernel_0049',
+    'launch_dispatch_kernel_0050',
+    'launch_dispatch_kernel_0051',
+    'launch_dispatch_kernel_0052',
+    'launch_dispatch_kernel_0053',
+    'launch_dispatch_kernel_0054',
+    'launch_dispatch_kernel_0055',
+    'launch_dispatch_kernel_0056',
+    'launch_dispatch_kernel_0057',
+    'launch_dispatch_kernel_0058',
+    'launch_dispatch_kernel_0059',
+    'launch_dispatch_kernel_0060',
+    'launch_dispatch_kernel_0061',
+    'launch_dispatch_kernel_0062',
+    'launch_dispatch_kernel_0063',
+    'launch_dispatch_kernel_0064',
+    'launch_dispatch_kernel_0065',
+    'launch_dispatch_kernel_0066',
+    'launch_dispatch_kernel_0067',
+    'launch_dispatch_kernel_0068',
+    'launch_dispatch_kernel_0069',
+    'launch_dispatch_kernel_0070',
+    'launch_dispatch_kernel_0071',
+    'launch_dispatch_kernel_0072',
+    'launch_dispatch_kernel_0073',
+    'launch_dispatch_kernel_0074',
+    'launch_dispatch_kernel_0075',
+    'launch_dispatch_kernel_0076',
+    'launch_dispatch_kernel_0077',
+    'launch_dispatch_kernel_0078',
+    'launch_dispatch_kernel_0079',
+    'launch_dispatch_kernel_0080',
+    'launch_dispatch_kernel_0081',
+    'launch_dispatch_kernel_0082',
+    'launch_dispatch_kernel_0083',
+    'launch_dispatch_kernel_0084',
+    'launch_dispatch_kernel_0085',
+    'launch_dispatch_kernel_0086',
+    'launch_dispatch_kernel_0087',
+    'launch_dispatch_kernel_0088',
+    'launch_dispatch_kernel_0089',
+    'launch_dispatch_kernel_0090',
+    'launch_dispatch_kernel_0091',
+    'launch_dispatch_kernel_0092',
+    'launch_dispatch_kernel_0093',
+    'launch_dispatch_kernel_0094',
+    'launch_dispatch_kernel_0095',
+    'launch_dispatch_kernel_0096',
+    'launch_dispatch_kernel_0097',
+    'launch_dispatch_kernel_0098',
+    'launch_dispatch_kernel_0099',
+    'launch_dispatch_kernel_0100',
+    'launch_dispatch_kernel_0101',
+    'launch_dispatch_kernel_0102',
+    'launch_dispatch_kernel_0103',
+    'launch_dispatch_kernel_0104',
+    'launch_dispatch_kernel_0105',
+    'launch_dispatch_kernel_0106',
+    'launch_dispatch_kernel_0107',
+    'launch_dispatch_kernel_0108',
+    'launch_dispatch_kernel_0109',
+    'launch_dispatch_kernel_0110',
+    'launch_dispatch_kernel_0111',
+    'launch_dispatch_kernel_0112',
+    'launch_dispatch_kernel_0113',
+    'launch_dispatch_kernel_0114',
+    'launch_dispatch_kernel_0115',
+    'launch_dispatch_kernel_0116',
+    'launch_dispatch_kernel_0117',
+    'launch_dispatch_kernel_0118',
+    'launch_dispatch_kernel_0119',
+    'launch_dispatch_kernel_0120',
+    'launch_dispatch_kernel_0121',
+    'launch_dispatch_kernel_0122',
+    'launch_dispatch_kernel_0123',
+    'launch_dispatch_kernel_0124',
+    'launch_dispatch_kernel_0125',
+    'launch_dispatch_kernel_0126',
+    'launch_dispatch_kernel_0127',
+    'launch_dispatch_kernel_0128',
+    'launch_dispatch_kernel_0129',
+    'launch_dispatch_kernel_0130',
+    'launch_dispatch_kernel_0131',
+    'launch_dispatch_kernel_0132',
+    'launch_dispatch_kernel_0133',
+    'launch_dispatch_kernel_0134',
+    'launch_dispatch_kernel_0135',
+    'launch_dispatch_kernel_0136',
+    'launch_dispatch_kernel_0137',
+    'launch_dispatch_kernel_0138',
+    'launch_dispatch_kernel_0139',
+    'launch_dispatch_kernel_0140',
+    'launch_dispatch_kernel_0141',
+    'launch_dispatch_kernel_0142',
+    'launch_dispatch_kernel_0143',
+    'launch_dispatch_kernel_0144',
+    'launch_dispatch_kernel_0145',
+    'launch_dispatch_kernel_0146',
+    'launch_dispatch_kernel_0147',
+    'launch_dispatch_kernel_0148',
+    'launch_dispatch_kernel_0149',
+    'launch_dispatch_kernel_0150',
+    'launch_dispatch_kernel_0151',
+    'launch_dispatch_kernel_0152',
+    'launch_dispatch_kernel_0153',
+    'launch_dispatch_kernel_0154',
+    'launch_dispatch_kernel_0155',
+    'launch_dispatch_kernel_0156',
+    'launch_dispatch_kernel_0157',
+    'launch_dispatch_kernel_0158',
+    'launch_dispatch_kernel_0159',
+    'launch_dispatch_kernel_0160',
+    'launch_dispatch_kernel_0161',
+    'launch_dispatch_kernel_0162',
+    'launch_dispatch_kernel_0163',
+    'launch_dispatch_kernel_0164',
+    'launch_dispatch_kernel_0165',
+    'launch_dispatch_kernel_0166',
+    'launch_dispatch_kernel_0167',
+    'launch_dispatch_kernel_0168',
+    'launch_dispatch_kernel_0169',
+    'launch_dispatch_kernel_0170',
+    'launch_dispatch_kernel_0171',
+    'launch_dispatch_kernel_0172',
+    'launch_dispatch_kernel_0173',
+    'launch_dispatch_kernel_0174',
+    'launch_dispatch_kernel_0175',
+    'launch_dispatch_kernel_0176',
+    'launch_dispatch_kernel_0177',
+    'launch_dispatch_kernel_0178',
+    'launch_dispatch_kernel_0179',
+    'launch_dispatch_kernel_0180',
+    'launch_dispatch_kernel_0181',
+    'launch_dispatch_kernel_0182',
+    'launch_dispatch_kernel_0183',
+    'launch_dispatch_kernel_0184',
+    'launch_dispatch_kernel_0185',
+    'launch_dispatch_kernel_0186',
+    'launch_dispatch_kernel_0187',
+    'launch_dispatch_kernel_0188',
+    'launch_dispatch_kernel_0189',
+    'launch_dispatch_kernel_0190',
+    'launch_dispatch_kernel_0191',
+    'launch_dispatch_kernel_0192',
+    'launch_dispatch_kernel_0193',
+    'launch_dispatch_kernel_0194',
+    'launch_dispatch_kernel_0195',
+    'launch_dispatch_kernel_0196',
+    'launch_dispatch_kernel_0197',
+    'launch_dispatch_kernel_0198',
+    'launch_dispatch_kernel_0199',
+    'launch_dispatch_kernel_0200',
+    'launch_dispatch_kernel_0201',
+    'launch_dispatch_kernel_0202',
+    'launch_dispatch_kernel_0203',
+    'launch_dispatch_kernel_0204',
+    'launch_dispatch_kernel_0205',
+    'launch_dispatch_kernel_0206',
+    'launch_dispatch_kernel_0207',
+    'launch_dispatch_kernel_0208',
+    'launch_dispatch_kernel_0209',
+    'launch_dispatch_kernel_0210',
+    'launch_dispatch_kernel_0211',
+    'launch_dispatch_kernel_0212',
+    'launch_dispatch_kernel_0213',
+    'launch_dispatch_kernel_0214',
+    'launch_dispatch_kernel_0215',
+    'launch_dispatch_kernel_0216',
+    'launch_dispatch_kernel_0217',
+    'launch_dispatch_kernel_0218',
+    'launch_dispatch_kernel_0219',
+    'launch_dispatch_kernel_0220',
+    'launch_dispatch_kernel_0221',
+    'launch_dispatch_kernel_0222',
+    'launch_dispatch_kernel_0223',
+    'launch_dispatch_kernel_0224',
+    'launch_dispatch_kernel_0225',
+    'launch_dispatch_kernel_0226',
+    'launch_dispatch_kernel_0227',
+    'launch_dispatch_kernel_0228',
+    'launch_dispatch_kernel_0229',
+    'launch_dispatch_kernel_0230',
+    'launch_dispatch_kernel_0231',
+    'launch_dispatch_kernel_0232',
+    'launch_dispatch_kernel_0233',
+    'launch_dispatch_kernel_0234',
+    'launch_dispatch_kernel_0235',
+    'launch_dispatch_kernel_0236',
+    'launch_dispatch_kernel_0237',
+    'launch_dispatch_kernel_0238',
+    'launch_dispatch_kernel_0239',
+    'launch_dispatch_kernel_0240',
+    'launch_dispatch_kernel_0241',
+    'launch_dispatch_kernel_0242',
+    'launch_dispatch_kernel_0243',
+    'launch_dispatch_kernel_0244',
+    'launch_dispatch_kernel_0245',
+    'launch_dispatch_kernel_0246',
+    'launch_dispatch_kernel_0247',
+    'launch_dispatch_kernel_0248',
+    'launch_dispatch_kernel_0249',
+    'launch_dispatch_kernel_0250',
+    'launch_dispatch_kernel_0251',
+    'launch_dispatch_kernel_0252',
+    'launch_dispatch_kernel_0253',
+    'launch_dispatch_kernel_0254',
+    'launch_dispatch_kernel_0255',
+    'launch_dispatch_kernel_0256',
+    'launch_dispatch_kernel_0257',
+    'launch_dispatch_kernel_0258',
+    'launch_dispatch_kernel_0259',
+    'launch_dispatch_kernel_0260',
+    'launch_dispatch_kernel_0261',
+    'launch_dispatch_kernel_0262',
+    'launch_dispatch_kernel_0263',
+    'launch_dispatch_kernel_0264',
+    'launch_dispatch_kernel_0265',
+    'launch_dispatch_kernel_0266',
+    'launch_dispatch_kernel_0267',
+    'launch_dispatch_kernel_0268',
+    'launch_dispatch_kernel_0269',
+    'launch_dispatch_kernel_0270',
+    'launch_dispatch_kernel_0271',
+    'launch_dispatch_kernel_0272',
+    'launch_dispatch_kernel_0273',
+    'launch_dispatch_kernel_0274',
+    'launch_dispatch_kernel_0275',
+    'launch_dispatch_kernel_0276',
+    'launch_dispatch_kernel_0277',
+    'launch_dispatch_kernel_0278',
+    'launch_dispatch_kernel_0279',
+    'launch_dispatch_kernel_0280',
+    'launch_dispatch_kernel_0281',
+    'launch_dispatch_kernel_0282',
+    'launch_dispatch_kernel_0283',
+    'launch_dispatch_kernel_0284',
+    'launch_dispatch_kernel_0285',
+    'launch_dispatch_kernel_0286',
+    'launch_dispatch_kernel_0287',
+    'launch_dispatch_kernel_0288',
+    'launch_dispatch_kernel_0289',
+    'launch_dispatch_kernel_0290',
+    'launch_dispatch_kernel_0291',
+    'launch_dispatch_kernel_0292',
+    'launch_dispatch_kernel_0293',
+    'launch_dispatch_kernel_0294',
+    'launch_dispatch_kernel_0295',
+    'launch_dispatch_kernel_0296',
+    'launch_dispatch_kernel_0297',
+    'launch_dispatch_kernel_0298',
+    'launch_dispatch_kernel_0299',
+    'launch_dispatch_kernel_0300',
+    'launch_dispatch_kernel_0301',
+    'launch_dispatch_kernel_0302',
+    'launch_dispatch_kernel_0303',
+    'launch_dispatch_kernel_0304',
+    'launch_dispatch_kernel_0305',
+    'launch_dispatch_kernel_0306',
+    'launch_dispatch_kernel_0307',
+    'launch_dispatch_kernel_0308',
+    'launch_dispatch_kernel_0309',
+    'launch_dispatch_kernel_0310',
+    'launch_dispatch_kernel_0311',
+    'launch_dispatch_kernel_0312',
+    'launch_dispatch_kernel_0313',
+    'launch_dispatch_kernel_0314',
+    'launch_dispatch_kernel_0315',
+    'launch_dispatch_kernel_0316',
+    'launch_dispatch_kernel_0317',
+    'launch_dispatch_kernel_0318',
+    'launch_dispatch_kernel_0319',
+    'launch_dispatch_kernel_0320',
+    'launch_dispatch_kernel_0321',
+    'launch_dispatch_kernel_0322',
+    'launch_dispatch_kernel_0323',
+    'launch_dispatch_kernel_0324',
+    'launch_dispatch_kernel_0325',
+    'launch_dispatch_kernel_0326',
+    'launch_dispatch_kernel_0327',
+    'launch_dispatch_kernel_0328',
+    'launch_dispatch_kernel_0329',
+    'launch_dispatch_kernel_0330',
+    'launch_dispatch_kernel_0331',
+    'launch_dispatch_kernel_0332',
+    'launch_dispatch_kernel_0333',
+    'launch_dispatch_kernel_0334',
+    'launch_dispatch_kernel_0335',
+    'launch_dispatch_kernel_0336',
+    'launch_dispatch_kernel_0337',
+    'launch_dispatch_kernel_0338',
+    'launch_dispatch_kernel_0339',
+    'launch_dispatch_kernel_0340',
+    'launch_dispatch_kernel_0341',
+    'launch_dispatch_kernel_0342',
+    'launch_dispatch_kernel_0343',
+    'launch_dispatch_kernel_0344',
+    'launch_dispatch_kernel_0345',
+    'launch_dispatch_kernel_0346',
+    'launch_dispatch_kernel_0347',
+    'launch_dispatch_kernel_0348',
+    'launch_dispatch_kernel_0349',
+    'launch_dispatch_kernel_0350',
+    'launch_dispatch_kernel_0351',
+    'launch_dispatch_kernel_0352',
+    'launch_dispatch_kernel_0353',
+    'launch_dispatch_kernel_0354',
+    'launch_dispatch_kernel_0355',
+    'launch_dispatch_kernel_0356',
+    'launch_dispatch_kernel_0357',
+    'register_tvm_ffi',
+    'tvm_ffi_function_names',
+]
+
+# Semantic exports generated from export_plan.package_exports.
+from .interface import FlashKMeansAssignRuntime as FlashKMeansAssignRuntime
+from .interface import PreparedFlashKMeansAssign as PreparedFlashKMeansAssign
+from .interface import init as init
+from .interface import prepare_flash_kmeans_assign as prepare_flash_kmeans_assign
+from .interface import flash_kmeans_assign_prepared as flash_kmeans_assign_prepared
+from .interface import flash_kmeans_assign as flash_kmeans_assign
+__all__ = [*globals().get('__all__', []), 'FlashKMeansAssignRuntime', 'PreparedFlashKMeansAssign', 'init', 'prepare_flash_kmeans_assign', 'flash_kmeans_assign_prepared', 'flash_kmeans_assign']
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_benchmark.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_benchmark.py
new file mode 100644
index 00000000..fd0e6677
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_benchmark.py
@@ -0,0 +1,648 @@
+from __future__ import annotations
+
+import bisect
+import contextlib
+import ctypes
+import importlib
+import importlib.metadata
+import math
+import statistics
+import sys
+from collections.abc import Callable
+from dataclasses import dataclass
+from pathlib import Path
+from typing import Any
+
+
+@dataclass(frozen=True)
+class BenchResult:
+    """Strict CUPTI timing plus explicitly non-official host diagnostics.
+
+    Cold-L2 flushing completes before host timestamps begin, so synchronized
+    E2E isolates semantic call start through candidate completion. ``times_ms``
+    remains the official correlated GPU span.
+    """
+
+    times_ms: list[float]
+    backend: str = "cupti"
+    kernel_sum_times_ms: list[float] | None = None
+    inter_kernel_gap_times_ms: list[float] | None = None
+    active_union_times_ms: list[float] | None = None
+    activity_counts: list[int] | None = None
+    launch_activity_counts: list[int] | None = None
+    kernel_activity_counts: list[int] | None = None
+    submission_times_ms: list[float] | None = None
+    synchronized_e2e_times_ms: list[float] | None = None
+    cold_first_call_host_enqueue_ms: float | None = None
+    cold_first_call_synchronized_e2e_ms: float | None = None
+
+    def __post_init__(self) -> None:
+        if self.backend != "cupti":
+            raise ValueError(f"exported benchmark timing backend must be 'cupti', got {self.backend!r}")
+
+    @property
+    def median_ms(self) -> float:
+        return float(statistics.median(self.times_ms))
+
+    @property
+    def min_ms(self) -> float:
+        return float(min(self.times_ms))
+
+    @property
+    def mean_ms(self) -> float:
+        return float(statistics.fmean(self.times_ms))
+
+    @property
+    def median_gpu_span_ms(self) -> float:
+        return self.median_ms
+
+    @property
+    def median_kernel_sum_ms(self) -> float | None:
+        if self.kernel_sum_times_ms is None:
+            return None
+        return float(statistics.median(self.kernel_sum_times_ms))
+
+    @property
+    def median_inter_kernel_gap_ms(self) -> float | None:
+        if self.inter_kernel_gap_times_ms is None:
+            return None
+        return float(statistics.median(self.inter_kernel_gap_times_ms))
+
+    @property
+    def median_active_union_ms(self) -> float | None:
+        if self.active_union_times_ms is None:
+            return None
+        return float(statistics.median(self.active_union_times_ms))
+
+    @property
+    def median_activity_count(self) -> float | None:
+        if self.activity_counts is None:
+            return None
+        return float(statistics.median(self.activity_counts))
+
+    @property
+    def median_launch_activity_count(self) -> float | None:
+        if self.launch_activity_counts is None:
+            return None
+        return float(statistics.median(self.launch_activity_counts))
+
+    @property
+    def median_kernel_activity_count(self) -> float | None:
+        if self.kernel_activity_counts is None:
+            return None
+        return float(statistics.median(self.kernel_activity_counts))
+
+    @property
+    def median_submission_ms(self) -> float | None:
+        if self.submission_times_ms is None:
+            return None
+        return float(statistics.median(self.submission_times_ms))
+
+    @property
+    def median_host_enqueue_ms(self) -> float | None:
+        return self.median_submission_ms
+
+    @property
+    def host_enqueue_times_ms(self) -> list[float] | None:
+        return self.submission_times_ms
+
+    @property
+    def median_synchronized_e2e_ms(self) -> float | None:
+        if self.synchronized_e2e_times_ms is None:
+            return None
+        return float(statistics.median(self.synchronized_e2e_times_ms))
+
+
+@dataclass(frozen=True)
+class HostCallTiming:
+    """Diagnostic host brackets for one call; never an official GPU timing."""
+
+    host_enqueue_ms: float
+    synchronized_e2e_ms: float
+
+
+@dataclass(frozen=True)
+class _CuptiTiming:
+    gpu_span_ms: list[float]
+    kernel_sum_ms: list[float]
+    inter_kernel_gap_ms: list[float]
+    active_union_ms: list[float]
+    activity_count: list[int]
+    launch_activity_count: list[int]
+    kernel_activity_count: list[int]
+
+
+class _L2Flusher:
+    def __init__(self) -> None:
+        import torch
+
+        l2_size = int(torch.cuda.get_device_properties(0).L2_cache_size)
+        if l2_size <= 0:
+            raise RuntimeError("CUDA device did not report a positive L2 cache size")
+        self._buffer = torch.empty(2 * l2_size, dtype=torch.int8, device="cuda")
+
+    def flush(self) -> None:
+        self._buffer.zero_()
+
+
+_CUPTI: Any | None = None
+
+
+def _extend_cuda_namespace_for_pathfinder() -> None:
+    try:
+        import cuda
+    except ImportError:
+        return
+    cuda_paths = getattr(cuda, "__path__", None)
+    if cuda_paths is None:
+        return
+    known = {str(path) for path in cuda_paths}
+    for entry in sys.path:
+        if not entry:
+            continue
+        cuda_root = Path(entry) / "cuda"
+        if (cuda_root / "pathfinder").is_dir() and str(cuda_root) not in known:
+            cuda_paths.append(str(cuda_root))
+            known.add(str(cuda_root))
+
+
+def _preload_cupti_library() -> None:
+    # cupti-python imports cuda.pathfinder even when libcupti was found through
+    # the nvidia-cuda-cupti distribution.  Extend the split CUDA namespace
+    # before either loading path so the later extension import is reliable.
+    _extend_cuda_namespace_for_pathfinder()
+    try:
+        distribution = importlib.metadata.distribution("nvidia-cuda-cupti")
+        major = importlib.metadata.version("cupti-python").split(".", 1)[0]
+        packaged = next(
+            (
+                distribution.locate_file(path)
+                for path in distribution.files or ()
+                if str(path).endswith(f"/libcupti.so.{major}")
+            ),
+            None,
+        )
+        if packaged is not None and Path(packaged).is_file():
+            ctypes.CDLL(str(packaged), mode=ctypes.RTLD_GLOBAL)
+            return
+    except (importlib.metadata.PackageNotFoundError, OSError):
+        pass
+    try:
+        pathfinder = importlib.import_module("cuda.pathfinder")
+    except ImportError:
+        return
+    loader = getattr(pathfinder, "load_nvidia_dynamic_lib", None)
+    if loader is None:
+        return
+    loaded = loader("cupti")
+    loaded_path = str(getattr(loaded, "abs_path", ""))
+    try:
+        major = importlib.metadata.version("cupti-python").split(".", 1)[0]
+    except importlib.metadata.PackageNotFoundError:
+        return
+    expected = f"libcupti.so.{major}" if major.isdigit() else None
+    if expected and loaded_path:
+        name = Path(loaded_path).name
+        if name.startswith("libcupti.so.") and name != expected:
+            raise ImportError(f"incompatible CUPTI library {loaded_path}; cupti-python expects {expected}")
+
+
+def require_cupti() -> Any:
+    global _CUPTI
+    if _CUPTI is not None:
+        return _CUPTI
+    try:
+        _preload_cupti_library()
+        from cupti import cupti
+    except ImportError as exc:
+        raise RuntimeError(
+            "CUPTI timing is required; install the exported repository with its benchmark extra: "
+            "python -m pip install -e '.[benchmark]'"
+        ) from exc
+    _CUPTI = cupti
+    return _CUPTI
+
+
+def measure_host_call(fn: Callable[[], Any]) -> tuple[Any, HostCallTiming]:
+    """Run one call and return explicitly labeled host diagnostics.
+
+    The enqueue bracket ends when ``fn`` returns.  The synchronized bracket
+    ends after ``torch.cuda.synchronize()``.  A function that synchronizes
+    internally will therefore have a blocking enqueue bracket; callers should
+    not interpret either value as GPU-only execution time.
+    """
+    import torch
+
+    cupti = require_cupti()
+    start = cupti.get_timestamp()
+    value = fn()
+    submitted = cupti.get_timestamp()
+    torch.cuda.synchronize()
+    completed = cupti.get_timestamp()
+    return value, HostCallTiming(
+        host_enqueue_ms=(submitted - start) / 1e6,
+        synchronized_e2e_ms=(completed - start) / 1e6,
+    )
+
+
+def _finite_timing(value: Any, *, name: str, positive: bool) -> float:
+    number = float(value)
+    if not math.isfinite(number) or (number <= 0.0 if positive else number < 0.0):
+        relation = "positive" if positive else "non-negative"
+        raise ValueError(f"{name} must be finite and {relation}, got {value!r}")
+    return number
+
+
+def _percentile(values: list[float], fraction: float) -> float:
+    if not values:
+        raise ValueError("percentile requires at least one value")
+    ordered = sorted(values)
+    rank = (len(ordered) - 1) * float(fraction)
+    lower = math.floor(rank)
+    upper = math.ceil(rank)
+    if lower == upper:
+        return ordered[lower]
+    weight = rank - lower
+    return ordered[lower] * (1.0 - weight) + ordered[upper] * weight
+
+
+def _timing_distribution(values: Any, *, name: str, positive: bool) -> dict[str, Any]:
+    if not isinstance(values, list) or not values:
+        raise ValueError(f"{name} must contain at least one timing sample")
+    samples = [_finite_timing(value, name=name, positive=positive) for value in values]
+    return {
+        "sample_count": len(samples),
+        "min": min(samples),
+        "median": float(statistics.median(samples)),
+        "p90": _percentile(samples, 0.90),
+        "max": max(samples),
+    }
+
+
+def _host_call_payload(timing: HostCallTiming, *, name: str) -> dict[str, Any]:
+    host_enqueue_ms = _finite_timing(timing.host_enqueue_ms, name=f"{name}.host_enqueue_ms", positive=False)
+    synchronized_e2e_ms = _finite_timing(
+        timing.synchronized_e2e_ms,
+        name=f"{name}.synchronized_e2e_ms",
+        positive=True,
+    )
+    if host_enqueue_ms > synchronized_e2e_ms:
+        raise ValueError(f"{name}.host_enqueue_ms cannot exceed synchronized_e2e_ms")
+    return {
+        "timing_class": "cupti_timestamp_host_diagnostic",
+        "host_enqueue_ms": host_enqueue_ms,
+        "synchronized_e2e_ms": synchronized_e2e_ms,
+    }
+
+
+def _hot_compute_payload(timing: BenchResult, *, name: str, cache_state: str) -> dict[str, Any]:
+    if timing.backend != "cupti":
+        raise ValueError(f"{name} must use CUPTI")
+    gpu_span = _timing_distribution(timing.times_ms, name=f"{name}.gpu_span_ms", positive=True)
+    host_enqueue = _timing_distribution(
+        timing.submission_times_ms,
+        name=f"{name}.host_enqueue_ms",
+        positive=False,
+    )
+    synchronized_e2e = _timing_distribution(
+        timing.synchronized_e2e_times_ms,
+        name=f"{name}.synchronized_e2e_ms",
+        positive=True,
+    )
+    sample_counts = {
+        gpu_span["sample_count"],
+        host_enqueue["sample_count"],
+        synchronized_e2e["sample_count"],
+    }
+    if len(sample_counts) != 1:
+        raise ValueError(f"{name} CUPTI/host timing sample counts must match")
+    for index, (enqueue_sample, e2e_sample) in enumerate(
+        zip(timing.submission_times_ms, timing.synchronized_e2e_times_ms, strict=True)
+    ):
+        if float(enqueue_sample) > float(e2e_sample):
+            raise ValueError(f"{name} host enqueue sample {index} cannot exceed its synchronized E2E sample")
+    return {
+        "timing_backend": "cupti",
+        "cache_state": cache_state,
+        "sample_count": gpu_span["sample_count"],
+        "gpu_span_ms": gpu_span,
+        "host_enqueue_ms": host_enqueue,
+        "synchronized_e2e_ms": synchronized_e2e,
+    }
+
+
+def runtime_lifecycle_metrics(
+    *,
+    api: str,
+    measurement_session_id: str,
+    timing_boundary: str,
+    output_policy: str,
+    init: HostCallTiming | None,
+    init_sample_id: str | None,
+    first_compute: HostCallTiming,
+    first_cache_state: str,
+    hot_compute: BenchResult,
+    hot_cache_state: str,
+    amortization_call_counts: tuple[int, ...] = (1, 10, 100, 1000),
+    code_cache_state: str = "process_order_dependent",
+) -> dict[str, Any]:
+    """Normalize init-once, first-signature, and repeated public-call evidence.
+
+    ``first_compute`` is intentionally a CUPTI-timestamp host diagnostic: route
+    selection, compilation, allocation, launch, and completion all belong to
+    its synchronized E2E bracket, but it is not mislabeled as GPU-only time.
+    ``hot_compute`` retains strict correlated CUPTI activity timing.
+    """
+
+    for field_name, value in (
+        ("api", api),
+        ("measurement_session_id", measurement_session_id),
+        ("timing_boundary", timing_boundary),
+        ("output_policy", output_policy),
+        ("first_cache_state", first_cache_state),
+        ("hot_cache_state", hot_cache_state),
+        ("code_cache_state", code_cache_state),
+    ):
+        if not isinstance(value, str) or not value.strip():
+            raise ValueError(f"runtime lifecycle {field_name} must be a non-empty string")
+    if (
+        not amortization_call_counts
+        or any(isinstance(value, bool) or not isinstance(value, int) or value <= 0 for value in amortization_call_counts)
+        or tuple(amortization_call_counts) != tuple(sorted(set(amortization_call_counts)))
+    ):
+        raise ValueError("amortization_call_counts must be strictly increasing positive integers")
+
+    init_payload = _host_call_payload(init, name="init_once") if init is not None else None
+    if init_payload is not None:
+        if not isinstance(init_sample_id, str) or not init_sample_id.strip():
+            raise ValueError("init_sample_id is required when init timing is present")
+        init_payload = {"sample_id": init_sample_id, **init_payload}
+    elif init_sample_id is not None:
+        raise ValueError("init_sample_id requires init timing")
+    first_payload = {
+        "cache_state": first_cache_state,
+        "code_cache_state": code_cache_state,
+        **_host_call_payload(first_compute, name="first_compute"),
+        "gpu_span_ms": None,
+        "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
+    }
+    hot_payload = _hot_compute_payload(hot_compute, name="hot_compute", cache_state=hot_cache_state)
+
+    first_enqueue = first_payload["host_enqueue_ms"]
+    first_e2e = first_payload["synchronized_e2e_ms"]
+    hot_enqueue = hot_payload["host_enqueue_ms"]["median"]
+    hot_e2e = hot_payload["synchronized_e2e_ms"]["median"]
+    init_enqueue = init_payload["host_enqueue_ms"] if init_payload is not None else 0.0
+    init_e2e = init_payload["synchronized_e2e_ms"] if init_payload is not None else 0.0
+    amortized: list[dict[str, Any]] = []
+    for call_count in amortization_call_counts:
+        repeated = call_count - 1
+        after_init_enqueue = (first_enqueue + repeated * hot_enqueue) / call_count
+        after_init_e2e = (first_e2e + repeated * hot_e2e) / call_count
+        amortized.append(
+            {
+                "public_call_count": call_count,
+                "after_init_host_enqueue_ms_per_call": after_init_enqueue,
+                "after_init_synchronized_e2e_ms_per_call": after_init_e2e,
+                "including_init_host_enqueue_ms_per_call": (
+                    (init_enqueue + first_enqueue + repeated * hot_enqueue) / call_count
+                ),
+                "including_init_synchronized_e2e_ms_per_call": (
+                    (init_e2e + first_e2e + repeated * hot_e2e) / call_count
+                ),
+            }
+        )
+
+    return {
+        "schema": "loom-public-runtime-lifecycle-v1",
+        "api": api,
+        "measurement_session_id": measurement_session_id,
+        "timing_boundary": timing_boundary,
+        "output_policy": output_policy,
+        "init_once": init_payload,
+        "first_compute": first_payload,
+        "hot_compute": hot_payload,
+        "amortization": {
+            "model": "observed_first_call_plus_repeated_hot_median",
+            "init_attribution": "one_init_sample_per_validation_shard_runtime",
+            "missing_init_policy": "zero_for_api_without_explicit_init",
+            "call_counts": amortized,
+        },
+    }
+
+
+def compare_runtime_lifecycles(candidate: dict[str, Any], baseline: dict[str, Any]) -> dict[str, Any]:
+    """Compare two normalized public-API lifecycle records."""
+
+    for name, lifecycle in (("candidate", candidate), ("baseline", baseline)):
+        if not isinstance(lifecycle, dict) or lifecycle.get("schema") != "loom-public-runtime-lifecycle-v1":
+            raise ValueError(f"{name} runtime lifecycle has an invalid schema")
+    candidate_hot = candidate["hot_compute"]
+    baseline_hot = baseline["hot_compute"]
+    candidate_rows = candidate["amortization"]["call_counts"]
+    baseline_rows = baseline["amortization"]["call_counts"]
+    candidate_counts = [row["public_call_count"] for row in candidate_rows]
+    baseline_counts = [row["public_call_count"] for row in baseline_rows]
+    if candidate_counts != baseline_counts:
+        raise ValueError("candidate and baseline amortization call counts must match")
+
+    amortized: list[dict[str, Any]] = []
+    for candidate_row, baseline_row in zip(candidate_rows, baseline_rows, strict=True):
+        candidate_after_init = candidate_row["after_init_synchronized_e2e_ms_per_call"]
+        baseline_after_init = baseline_row["after_init_synchronized_e2e_ms_per_call"]
+        candidate_including_init = candidate_row["including_init_synchronized_e2e_ms_per_call"]
+        baseline_including_init = baseline_row["including_init_synchronized_e2e_ms_per_call"]
+        amortized.append(
+            {
+                "public_call_count": candidate_row["public_call_count"],
+                "after_init_synchronized_e2e_speedup": baseline_after_init / candidate_after_init,
+                "including_init_synchronized_e2e_speedup": baseline_including_init / candidate_including_init,
+            }
+        )
+
+    return {
+        "schema": "loom-public-runtime-lifecycle-comparison-v1",
+        "speedup_convention": "baseline_latency_divided_by_candidate_latency",
+        "hot_synchronized_e2e_speedup": (
+            baseline_hot["synchronized_e2e_ms"]["median"]
+            / candidate_hot["synchronized_e2e_ms"]["median"]
+        ),
+        "hot_gpu_span_speedup": (
+            baseline_hot["gpu_span_ms"]["median"] / candidate_hot["gpu_span_ms"]["median"]
+        ),
+        "amortized": amortized,
+    }
+
+
+def _complete_l2_flush_before_bracket(flusher: Any, synchronize: Callable[[], None]) -> None:
+    """Finish cold-L2 preconditioning before host latency timestamps begin."""
+    if flusher is None:
+        return
+    flusher.flush()
+    synchronize()
+
+
+def _correlate(
+    cpu_brackets: list[tuple[int, int, int]],
+    launches: list[tuple[int, int, int]],
+    kernels: list[tuple[int, int, int]],
+) -> _CuptiTiming:
+    if not launches or not kernels:
+        raise RuntimeError("CUPTI collected no launch/kernel activities")
+    launches.sort(key=lambda item: item[0])
+    launch_starts = [item[0] for item in launches]
+    kernels.sort(key=lambda item: item[0])
+    kernel_indices_by_correlation: dict[int, list[int]] = {}
+    for index, (_start, _end, correlation_id) in enumerate(kernels):
+        kernel_indices_by_correlation.setdefault(correlation_id, []).append(index)
+
+    gpu_span_ms: list[float] = []
+    kernel_sum_ms: list[float] = []
+    inter_kernel_gap_ms: list[float] = []
+    active_union_ms: list[float] = []
+    activity_count: list[int] = []
+    launch_activity_count: list[int] = []
+    kernel_activity_count: list[int] = []
+    for bracket_start, bracket_end, _completed in cpu_brackets:
+        lo = bisect.bisect_left(launch_starts, bracket_start)
+        hi = bisect.bisect_right(launch_starts, bracket_end)
+        correlation_ids = {launches[index][2] for index in range(lo, hi)}
+        launch_activity_count.append(
+            sum(
+                1
+                for index in range(lo, hi)
+                if kernel_indices_by_correlation.get(launches[index][2])
+            )
+        )
+        selected_indices = {
+            index
+            for correlation_id in correlation_ids
+            for index in kernel_indices_by_correlation.get(correlation_id, ())
+        }
+        if not selected_indices:
+            raise RuntimeError("CUPTI could not correlate a benchmark iteration with GPU kernel activity")
+        spans = [(kernels[index][0], kernels[index][1]) for index in selected_indices]
+        span_ns = max(end for _, end in spans) - min(start for start, _ in spans)
+        sum_ns = sum(end - start for start, end in spans)
+        covered_ns = 0
+        current_start, current_end = sorted(spans)[0]
+        for start, end in sorted(spans)[1:]:
+            if start <= current_end:
+                current_end = max(current_end, end)
+            else:
+                covered_ns += current_end - current_start
+                current_start, current_end = start, end
+        covered_ns += current_end - current_start
+        gpu_span_ms.append(span_ns / 1e6)
+        kernel_sum_ms.append(sum_ns / 1e6)
+        active_union_ms.append(covered_ns / 1e6)
+        inter_kernel_gap_ms.append((span_ns - covered_ns) / 1e6)
+        activity_count.append(len(selected_indices))
+        kernel_activity_count.append(len(selected_indices))
+    return _CuptiTiming(
+        gpu_span_ms=gpu_span_ms,
+        kernel_sum_ms=kernel_sum_ms,
+        inter_kernel_gap_ms=inter_kernel_gap_ms,
+        active_union_ms=active_union_ms,
+        activity_count=activity_count,
+        launch_activity_count=launch_activity_count,
+        kernel_activity_count=kernel_activity_count,
+    )
+
+
+def bench_gpu_time(
+    fn: Callable[[], Any],
+    *,
+    warmup_iters: int = 5,
+    bench_iters: int = 20,
+    cold_l2: bool = True,
+    cold_first_call: HostCallTiming | None = None,
+) -> BenchResult:
+    """Measure a zero-argument GPU workload with strict CUPTI activity tracing.
+
+    L2 is flushed before every warmup and measured iteration. This function
+    never falls back to wall-clock or CUDA-event timing.
+    """
+    if warmup_iters < 0 or bench_iters <= 0:
+        raise ValueError("warmup_iters must be non-negative and bench_iters must be positive")
+
+    import torch
+
+    cupti = require_cupti()
+    flusher = _L2Flusher() if cold_l2 else None
+    for _ in range(warmup_iters):
+        if flusher is not None:
+            flusher.flush()
+        fn()
+    torch.cuda.synchronize()
+
+    launch_kinds = {int(cupti.ActivityKind.RUNTIME), int(cupti.ActivityKind.DRIVER)}
+    kernel_kinds = {int(cupti.ActivityKind.CONCURRENT_KERNEL)}
+    launches: list[tuple[int, int, int]] = []
+    kernels: list[tuple[int, int, int]] = []
+
+    def _buffer_requested():
+        return 8 * 1024 * 1024, 0
+
+    def _buffer_completed(activities: list[Any]) -> None:
+        for activity in activities:
+            record = (activity.start, activity.end, activity.correlation_id)
+            kind = int(activity.kind)
+            if kind in launch_kinds:
+                launches.append(record)
+            elif kind in kernel_kinds:
+                kernels.append(record)
+
+    kinds = [
+        cupti.ActivityKind.RUNTIME,
+        cupti.ActivityKind.DRIVER,
+        cupti.ActivityKind.CONCURRENT_KERNEL,
+        cupti.ActivityKind.MEMCPY,
+        cupti.ActivityKind.MEMSET,
+    ]
+    enabled: list[Any] = []
+    cpu_brackets: list[tuple[int, int, int]] = []
+    watchdog = sys.modules.get("loom.runtime.cuda_watchdog")
+    suspend_polling = getattr(watchdog, "suspend_polling", None)
+    polling_guard = suspend_polling() if callable(suspend_polling) else contextlib.nullcontext()
+    with polling_guard:
+        cupti.activity_register_callbacks(_buffer_requested, _buffer_completed)
+        try:
+            for kind in kinds:
+                cupti.activity_enable(kind)
+                enabled.append(kind)
+
+            for _ in range(bench_iters):
+                _complete_l2_flush_before_bracket(flusher, torch.cuda.synchronize)
+                start = cupti.get_timestamp()
+                fn()
+                submitted = cupti.get_timestamp()
+                torch.cuda.synchronize()
+                completed = cupti.get_timestamp()
+                cpu_brackets.append((start, submitted, completed))
+            cupti.activity_flush_all(1)
+        finally:
+            for kind in reversed(enabled):
+                cupti.activity_disable(kind)
+            cupti.finalize()
+
+    timing = _correlate(cpu_brackets, launches, kernels)
+    return BenchResult(
+        times_ms=timing.gpu_span_ms,
+        kernel_sum_times_ms=timing.kernel_sum_ms,
+        inter_kernel_gap_times_ms=timing.inter_kernel_gap_ms,
+        active_union_times_ms=timing.active_union_ms,
+        activity_counts=timing.activity_count,
+        launch_activity_counts=timing.launch_activity_count,
+        kernel_activity_counts=timing.kernel_activity_count,
+        submission_times_ms=[(submitted - start) / 1e6 for start, submitted, _ in cpu_brackets],
+        synchronized_e2e_times_ms=[
+            (completed - start) / 1e6 for start, _, completed in cpu_brackets
+        ],
+        cold_first_call_host_enqueue_ms=(
+            cold_first_call.host_enqueue_ms if cold_first_call is not None else None
+        ),
+        cold_first_call_synchronized_e2e_ms=(
+            cold_first_call.synchronized_e2e_ms if cold_first_call is not None else None
+        ),
+    )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/__init__.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1.py
new file mode 100644
index 00000000..ca0579f3
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1.py
@@ -0,0 +1,142 @@
+"""Clean-room Flash-KMeans Euclidean assignment D160 padded-tail candidate.
+
+Minimum architecture: sm_100a. This candidate uses a Weave BF16 pack/zero-fill
+producer to pad logical D=160 tensors to D=192 scratch, then reuses the
+Blackwell tcgen05/TMEM D192 three-chunk score/argmin path. It is not intended
+for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1 as _d192
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = _d192.BLOCK_N
+BLOCK_K = _d192.BLOCK_K
+FEAT_D = 160
+FEAT_D_PAD = _d192.FEAT_D
+FEAT_D_PAD_VECS = FEAT_D_PAD // 8
+PACK_THREADS = 256
+PACK_GRID_CAP = 4096
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+pack_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    return _d192._cuda_include_dirs()
+
+def _create_padded_tensor_map_3d(data_ptr: int, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D_PAD, FEAT_D_PAD)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d(data_ptr, global_height, shared_height, FEAT_D_PAD, FEAT_D_PAD).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_tmaps(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> tuple[Any, Any]:
+    cache_key = (int(x_pad.data_ptr()), int(c_pad.data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_PAD)
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_d160_padded_b23d_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_padded_tensor_map_3d(x_pad.data_ptr(), bsz * n_points, BLOCK_N)
+    tmap_c = _create_padded_tensor_map_3d(c_pad.data_ptr(), bsz * n_clusters, BLOCK_K)
+    inputs['_flash_kmeans_assign_cleanroom_d160_padded_b23d_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _scratch_buffers(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    import torch
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), bsz, n_points, n_clusters, int(inputs['D']))
+    cache = inputs.setdefault('_flash_kmeans_assign_cleanroom_d160_padded_b23d_v1_scratch', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    x_pad = torch.empty((bsz, n_points, FEAT_D_PAD), dtype=inputs['x'].dtype, device=inputs['x'].device)
+    c_pad = torch.empty((bsz, n_clusters, FEAT_D_PAD), dtype=inputs['centroids'].dtype, device=inputs['centroids'].device)
+    cache[cache_key] = (x_pad, c_pad)
+    inputs.pop('_flash_kmeans_assign_cleanroom_d160_padded_b23d_v1_tmaps', None)
+    return (x_pad, c_pad)
+
+def _compiled_pack_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0357"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1", 0, 256]}'))
+
+def _launch_pack(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    total_x_pad = bsz * n_points * FEAT_D_PAD
+    total_c_pad = bsz * n_clusters * FEAT_D_PAD
+    work_items = max(total_x_pad, total_c_pad)
+    grid_x = min((work_items + PACK_THREADS - 1) // PACK_THREADS, PACK_GRID_CAP)
+    cubin, kernel_name, smem_bytes, threads = _compiled_pack_kernel()
+    args = [inputs['x'], inputs['centroids'], x_pad, c_pad, bsz, n_points, dim, n_clusters, total_x_pad, total_c_pad]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(grid_x, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _launch_d192_main_on_padded(inputs: dict[str, Any], tmap_x: Any, tmap_c: Any) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    cubin, kernel_name, smem_bytes, threads = _d192._compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(_d192.flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1 requires bfloat16, got ', format(dtype, '')]))
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    x_pad, c_pad = _scratch_buffers(inputs)
+    _launch_pack(inputs, x_pad, c_pad)
+    tmap_x, tmap_c = _make_tmaps(inputs, x_pad, c_pad)
+    _launch_d192_main_on_padded(inputs, tmap_x, tmap_c)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=1, N: int=2048, K: int=2048, D: int=160, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(16001)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 16001}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1.py
new file mode 100644
index 00000000..8fa679f0
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1.py
@@ -0,0 +1,91 @@
+"""Clean-room Flash-KMeans Euclidean assignment D192 repeated-MMA single-tile candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for the D-specific repeated-MMA score tile producer and is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D = 192
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D * 2
+X_FEAT_CHUNK_BYTES = BLOCK_N * 64 * 2
+C_FEAT_CHUNK_BYTES = BLOCK_K * 64 * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 149504, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_d192_single_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, dim)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, dim)
+    inputs['_flash_kmeans_assign_cleanroom_d192_single_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0344"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1", 149504, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=2, N: int=1024, K: int=512, D: int=192, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1.py
new file mode 100644
index 00000000..6fadc933
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1.py
@@ -0,0 +1,106 @@
+"""Clean-room Flash-KMeans Euclidean assignment D192 repeated-MMA paired-tile candidate.
+
+Minimum architecture: sm_100a. This candidate dispatches between a D-specific repeated-MMA single point-tile path and a D-specific repeated-MMA paired point-tile tcgen05/TMEM path. It is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1 as _single
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 16
+CSQ_STAGE_VEC = 4
+FEAT_D = 192
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D * 2
+X_FEAT_CHUNK_BYTES = BLOCK_N * 64 * 2
+C_FEAT_CHUNK_BYTES = BLOCK_K * 64 * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+X1_OFFSET = X_TILE_BYTES
+C_OFFSET = 2 * X_TILE_BYTES
+CSQ_OFFSET = 2 * X_TILE_BYTES + C_TILE_BYTES
+PAIRED_GRID_CAP = 2516
+flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 198656, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_d192_splitd_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, dim)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, dim)
+    inputs['_flash_kmeans_assign_cleanroom_d192_splitd_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0343"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1", 198656, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 198656, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _use_single_tile_path(*, n_points: int, n_clusters: int) -> bool:
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    return num_n_tiles % 2 != 0 or (num_n_tiles <= 8 and k_tiles <= 2)
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if _use_single_tile_path(n_points=n_points, n_clusters=n_clusters):
+        return _single.launch_for_eval(inputs)
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    num_n_tiles = n_points // BLOCK_N
+    if num_n_tiles % 2 != 0:
+        raise ValueError('flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 requires an even number of BLOCK_N point tiles')
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    k_tiles = n_clusters // BLOCK_K
+    total_tiles = bsz * (num_n_tiles // 2)
+    grid = (min(total_tiles, PAIRED_GRID_CAP), 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=2, N: int=1024, K: int=512, D: int=192, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1.py
new file mode 100644
index 00000000..68271344
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1.py
@@ -0,0 +1,91 @@
+"""Clean-room Flash-KMeans Euclidean assignment D256 repeated-MMA single-tile candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for the D-specific repeated-MMA score tile producer and is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D = 256
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D * 2
+X_FEAT_CHUNK_BYTES = BLOCK_N * 64 * 2
+C_FEAT_CHUNK_BYTES = BLOCK_K * 64 * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 198656, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_d256_single_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, dim)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, dim)
+    inputs['_flash_kmeans_assign_cleanroom_d256_single_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0342"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1", 198656, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=2, N: int=1024, K: int=512, D: int=256, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_b23d_v2.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_b23d_v2.py
new file mode 100644
index 00000000..d02c4154
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_b23d_v2.py
@@ -0,0 +1,90 @@
+"""Flash-KMeans Euclidean assignment D160/D192/D256 repeated-MMA bucket seed.
+
+Minimum architecture: sm_100a. This wrapper routes contract evaluation to
+D-specific Weave tcgen05/TMEM seeds only; it does not call external runtime
+fallbacks. The seed modules are not intended for sm_120a/sm_121a where ptxas
+rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_d160_padded_b23d_v1 as _d160
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 as _d192
+from . import flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1 as _d256
+BLOCK_N = _d192.BLOCK_N
+BLOCK_K = _d192.BLOCK_K
+SUPPORTED_DIMS = (160, 192, 256)
+D160_BUCKET_SHAPES: list[dict[str, Any]] = [{'label': 'd160_paired_b1_n2048_k2048_d160', 'params': {'B': 1, 'N': 2048, 'D': 160, 'K': 2048, 'dtype': 'bfloat16', 'seed': 16001}}, {'label': 'd160_fallback_b2_n2432_k1024_d160', 'params': {'B': 2, 'N': 2432, 'D': 160, 'K': 1024, 'dtype': 'bfloat16', 'seed': 16002}}]
+BUCKET_SHAPES: list[dict[str, Any]] = [*D160_BUCKET_SHAPES, {'label': 'd192_small_b1_n1024_k512_d192', 'params': {'B': 1, 'N': 1024, 'D': 192, 'K': 512, 'dtype': 'bfloat16', 'seed': 19201}}, {'label': 'd192_paired_b1_n2048_k2048_d192', 'params': {'B': 1, 'N': 2048, 'D': 192, 'K': 2048, 'dtype': 'bfloat16', 'seed': 19202}}, {'label': 'd192_random_b2_n4096_k768_d192', 'params': {'B': 2, 'N': 4096, 'D': 192, 'K': 768, 'dtype': 'bfloat16', 'seed': 19204}}, {'label': 'd256_small_b1_n1024_k512_d256', 'params': {'B': 1, 'N': 1024, 'D': 256, 'K': 512, 'dtype': 'bfloat16', 'seed': 25601}}, {'label': 'd256_paired_b1_n2048_k2048_d256', 'params': {'B': 1, 'N': 2048, 'D': 256, 'K': 2048, 'dtype': 'bfloat16', 'seed': 25602}}, {'label': 'd256_fallback_b2_n2432_k1024_d256', 'params': {'B': 2, 'N': 2432, 'D': 256, 'K': 1024, 'dtype': 'bfloat16', 'seed': 25603}}, {'label': 'd256_large_b4_n16384_k1024_d256', 'params': {'B': 4, 'N': 16384, 'D': 256, 'K': 1024, 'dtype': 'bfloat16', 'seed': 25604}}, {'label': 'd256_hugek_b1_n1024_k8192_d256', 'params': {'B': 1, 'N': 1024, 'D': 256, 'K': 8192, 'dtype': 'bfloat16', 'seed': 25605}}]
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    dim = int(inputs['D'])
+    module = _module_for_dim(dim)
+    route_kind = _route_kind(inputs)
+    outputs = module.launch_for_eval(inputs)
+    normalized = _normalize_outputs(outputs, inputs)
+    selected_route = ''.join(['d', format(dim, ''), '_', format(route_kind, ''), '_repeated_mma_v2'])
+    normalized['selected_route'] = selected_route
+    normalized['route_trace'] = {'shape_key': _shape_key(inputs), 'selected_route': selected_route, 'selected_entrypoint': ''.join([format(module.__name__, ''), ':launch_for_eval']), 'selected_seed': ''.join(['d', format(dim, ''), '-', format(route_kind, ''), '-repeated-mma-b23d-v2']), 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': ''.join(['guard_d', format(dim, ''), '_', format(route_kind, ''), '_repeated_mma_b23d_v2']), 'guard_condition': ''.join(['dtype == bfloat16 and D == ', format(dim, ''), ' and N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']), 'classification': 'seed-probe', 'dispatcher_kernel_ms': None, 'reason': 'non-128D bucket seed wrapper routes to D-specific Weave tcgen05 candidate'}
+    return normalized
+
+def _module_for_dim(dim: int):
+    if dim == 160:
+        return _d160
+    if dim == 192:
+        return _d192
+    if dim == 256:
+        return _d256
+    raise ValueError(''.join(['non128d split-D seed supports D in ', format(SUPPORTED_DIMS, ''), ', got ', format(dim, '')]))
+
+def _route_kind(inputs: dict[str, Any]) -> str:
+    dim = int(inputs['D'])
+    if dim == 160:
+        return 'padded_single'
+    if dim == 256:
+        return 'single'
+    n_tiles = int(inputs['N']) // BLOCK_N
+    k_tiles = int(inputs['K']) // BLOCK_K
+    if n_tiles % 2 != 0 or (n_tiles <= 8 and k_tiles <= 2):
+        return 'single'
+    return 'paired'
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign non128d split-D route must return cluster_ids or write inputs['out']")
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=1, N: int=2048, K: int=2048, D: int=160, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(16001)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 16001}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1.py
new file mode 100644
index 00000000..5ed326dc
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1.py
@@ -0,0 +1,96 @@
+"""Flash-KMeans Euclidean assignment D192/D256 repeated-MMA bucket seed.
+
+Minimum architecture: sm_100a. This wrapper routes contract evaluation to
+D-specific Weave tcgen05/TMEM seeds only; it does not call external runtime
+fallbacks. The seed modules are not intended for sm_120a/sm_121a where ptxas
+rejects tcgen05 instructions. D160 is listed as a blocked sibling because its
+32-wide BF16 tail currently hangs when lowered as K=32 tcgen05 MMA.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1 as _d192_single
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 as _d192
+from . import flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1 as _d256
+BLOCK_N = _d192.BLOCK_N
+BLOCK_K = _d192.BLOCK_K
+SUPPORTED_DIMS = (192, 256)
+BUCKET_SHAPES: list[dict[str, Any]] = [{'label': 'd192_small_b2_n1024_k512_d192', 'params': {'B': 2, 'N': 1024, 'D': 192, 'K': 512, 'dtype': 'bfloat16', 'seed': 19201}}, {'label': 'd192_paired_b2_n2048_k2048_d192', 'params': {'B': 2, 'N': 2048, 'D': 192, 'K': 2048, 'dtype': 'bfloat16', 'seed': 19202}}, {'label': 'd192_fallback_b1_n2176_k1024_d192', 'params': {'B': 1, 'N': 2176, 'D': 192, 'K': 1024, 'dtype': 'bfloat16', 'seed': 19203}}, {'label': 'd192_large_b4_n32768_k1024_d192', 'params': {'B': 4, 'N': 32768, 'D': 192, 'K': 1024, 'dtype': 'bfloat16', 'seed': 19204}}, {'label': 'd256_small_b1_n1024_k512_d256', 'params': {'B': 1, 'N': 1024, 'D': 256, 'K': 512, 'dtype': 'bfloat16', 'seed': 25601}}, {'label': 'd256_paired_b1_n4096_k4096_d256', 'params': {'B': 1, 'N': 4096, 'D': 256, 'K': 4096, 'dtype': 'bfloat16', 'seed': 25602}}, {'label': 'd256_fallback_b2_n2432_k2048_d256', 'params': {'B': 2, 'N': 2432, 'D': 256, 'K': 2048, 'dtype': 'bfloat16', 'seed': 25603}}, {'label': 'd256_hugek_b1_n512_k8192_d256', 'params': {'B': 1, 'N': 512, 'D': 256, 'K': 8192, 'dtype': 'bfloat16', 'seed': 25604}}]
+D160_BLOCKED_SHAPES: list[dict[str, Any]] = [{'label': 'd160_fallback_b2_n2432_k1024_d160', 'params': {'B': 2, 'N': 2432, 'D': 160, 'K': 1024, 'dtype': 'bfloat16', 'seed': 16002}, 'blocker': 'D160 requires a BF16 32-wide feature tail; the current K=32 tcgen05 path hangs at runtime.'}, {'label': 'd160_paired_b1_n2048_k2048_d160', 'params': {'B': 1, 'N': 2048, 'D': 160, 'K': 2048, 'dtype': 'bfloat16', 'seed': 16001}, 'blocker': 'D160 requires a BF16 32-wide feature tail; the current K=32 tcgen05 path hangs at runtime.'}]
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    dim = int(inputs['D'])
+    module = _module_for_dim(dim)
+    route_kind = _route_kind(inputs)
+    outputs = module.launch_for_eval(inputs)
+    normalized = _normalize_outputs(outputs, inputs)
+    selected_route = ''.join(['d', format(dim, ''), '_', format(route_kind, ''), '_repeated_mma_v1'])
+    selected_entrypoint = _selected_entrypoint(dim, route_kind)
+    normalized['selected_route'] = selected_route
+    normalized['route_trace'] = {'shape_key': _shape_key(inputs), 'selected_route': selected_route, 'selected_entrypoint': selected_entrypoint, 'selected_seed': ''.join(['d', format(dim, ''), '-', format(route_kind, ''), '-repeated-mma-v1']), 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': ''.join(['guard_d', format(dim, ''), '_', format(route_kind, ''), '_repeated_mma_v1']), 'guard_condition': ''.join(['dtype == bfloat16 and D == ', format(dim, ''), ' and N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']), 'classification': 'seed-probe', 'dispatcher_kernel_ms': None, 'reason': 'non-128D bucket seed wrapper routes to D-specific Weave tcgen05 candidate'}
+    return normalized
+
+def _module_for_dim(dim: int):
+    if dim == 192:
+        return _d192
+    if dim == 256:
+        return _d256
+    raise ValueError(''.join(['non128d split-D seed supports D in ', format(SUPPORTED_DIMS, ''), ', got ', format(dim, '')]))
+
+def _selected_entrypoint(dim: int, route_kind: str) -> str:
+    if dim == 192 and route_kind == 'single':
+        return ''.join([format(_d192_single.__name__, ''), ':launch_for_eval'])
+    if dim == 192:
+        return ''.join([format(_d192.__name__, ''), ':launch_for_eval'])
+    if dim == 256:
+        return ''.join([format(_d256.__name__, ''), ':launch_for_eval'])
+    raise ValueError(''.join(['non128d split-D seed supports D in ', format(SUPPORTED_DIMS, ''), ', got ', format(dim, '')]))
+
+def _route_kind(inputs: dict[str, Any]) -> str:
+    if int(inputs['D']) == 256:
+        return 'single'
+    n_tiles = int(inputs['N']) // BLOCK_N
+    k_tiles = int(inputs['K']) // BLOCK_K
+    if n_tiles % 2 != 0 or (n_tiles <= 8 and k_tiles <= 2):
+        return 'single'
+    return 'paired'
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign non128d split-D route must return cluster_ids or write inputs['out']")
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=1, N: int=1024, K: int=512, D: int=192, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v10.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v10.py
new file mode 100644
index 00000000..3483fd2c
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v10.py
@@ -0,0 +1,89 @@
+"""Clean-room Flash-KMeans Euclidean assignment candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for the D=128 score tile producer and is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D = 128
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_cleanroom_tcgen05_v10 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_v10", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 100352, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_v10_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, dim)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, dim)
+    inputs['_flash_kmeans_assign_cleanroom_v10_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0341"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_v10", 100352, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_v10 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(flash_kmeans_assign_cleanroom_tcgen05_v10, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=2, N: int=1024, K: int=512, D: int=128, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v15.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v15.py
new file mode 100644
index 00000000..23284712
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_cleanroom_tcgen05_v15.py
@@ -0,0 +1,106 @@
+"""Clean-room Flash-KMeans Euclidean assignment 16-wide argmin candidate.
+
+Minimum architecture: sm_100a. This candidate dispatches between the v10
+single point-tile path for small grids and a 16-wide argmin variant of the
+paired point-tile tcgen05/TMEM path for large grids. It is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_v10 as _single
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 16
+CSQ_STAGE_VEC = 4
+FEAT_D = 128
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+X1_OFFSET = X_TILE_BYTES
+C_OFFSET = 2 * X_TILE_BYTES
+CSQ_OFFSET = 2 * X_TILE_BYTES + C_TILE_BYTES
+PAIRED_GRID_CAP = 2516
+flash_kmeans_assign_cleanroom_tcgen05_v15 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_v15", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 133120, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_cleanroom_v15_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, dim)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, dim)
+    inputs['_flash_kmeans_assign_cleanroom_v15_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0340"}, "kernel_flash_kmeans_assign_cleanroom_tcgen05_v15", 133120, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_cleanroom_tcgen05_v15", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 133120, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _use_single_tile_path(*, n_points: int, n_clusters: int) -> bool:
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    return num_n_tiles <= 8 and k_tiles <= 2
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if _use_single_tile_path(n_points=n_points, n_clusters=n_clusters):
+        return _single.launch_for_eval(inputs)
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_cleanroom_tcgen05_v15 requires D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    num_n_tiles = n_points // BLOCK_N
+    if num_n_tiles % 2 != 0:
+        raise ValueError('flash_kmeans_assign_cleanroom_tcgen05_v15 requires an even number of BLOCK_N point tiles')
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    k_tiles = n_clusters // BLOCK_K
+    total_tiles = bsz * (num_n_tiles // 2)
+    grid = (min(total_tiles, PAIRED_GRID_CAP), 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_cleanroom(B: int=2, N: int=1024, K: int=512, D: int=128, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_4549_c72b_k1024_overlay_weave_evolve_flash_kmeans_assign_3ae6_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_4549_c72b_k1024_overlay_weave_evolve_flash_kmeans_assign_3ae6_v1.py
new file mode 100644
index 00000000..912bfee9
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_4549_c72b_k1024_overlay_weave_evolve_flash_kmeans_assign_3ae6_v1.py
@@ -0,0 +1,60 @@
+"""Frozen D112 K-owned portfolio composition (minimum architecture: sm_100a).
+
+The c72b dual-issuer tcgen05/TMEM kernel owns exactly K=1024.  The 4549
+direct-handoff portfolio owns K in {256, 512, 768, 4096, 8192}.  Both child
+sources are imported byte-for-byte from their pinned source revisions; this
+module adds only the host ownership guard and auditable route metadata.  Every
+route writes caller-owned ``cluster_ids`` with one Weave compute launch and no
+padding, packing, fallback, or global workspace.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1 as _base
+from . import flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1 as _overlay
+FEAT_D = 112
+BASE_K = (256, 512, 768, 4096, 8192)
+OVERLAY_K = 1024
+SUPPORTED_K = (*BASE_K[:3], OVERLAY_K, *BASE_K[3:])
+ROUTE_ID = 'd112_4549_c72b_k1024_overlay_weave_evolve_flash_kmeans_assign_3ae6_v1'
+SEED_ID = 'd112-4549-c72b-k1024-overlay-weave-evolve-flash-kmeans-assign-3ae6-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+BASE_SOURCE = {'id': 'base_portfolio', 'source_task': 'weave-evolve-flash-kmeans-assign-4549', 'source_kernel_task': 'weave-evolve-flash-kmeans-assign-4549', 'source_revision': '21c48b897873f6a5e631c7fccd320c35d73ae6d5', 'evidence_revision': '713ee91855069de8580152c20ec37b5ab4569c29', 'source_blob': '9d4da373afd9869c2718fffaf62f4230f4bb2482', 'source_sha256': 'ef1b1b574a5ce0516c745a5c28fa381a47e8a5e5c9ad49e35a93bff496c43b64', 'source_path': 'loom/examples/weave/flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1.py', 'entrypoint': ''.join([format(_base.__name__, ''), ':launch_for_eval'])}
+OVERLAY_SOURCE = {'id': 'k1024_overlay', 'source_task': 'weave-evolve-flash-kmeans-assign-c72b', 'source_kernel_task': 'weave-evolve-flash-kmeans-assign-6e1e', 'source_revision': 'a2415111e8f5d268760c97ccc65496173b289741', 'evidence_revision': '048037f7fada3aec532d102d1f1ca16fd1decc8b', 'source_blob': 'cf307b65bed35cd7384fbb78de2bfcf10bc29193', 'source_sha256': '2cf0d0da5e68abe23c22cf5a88315f8aede639095e6b84df40931a423aa94766', 'source_path': 'loom/examples/weave/flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1.py', 'entrypoint': ''.join([format(_overlay.__name__, ''), ':launch_for_eval'])}
+
+def source_for_k(K: int) -> dict[str, str]:
+    """Return the immutable source record for one admitted K regime."""
+    if K == OVERLAY_K:
+        return OVERLAY_SOURCE
+    if K in BASE_K:
+        return BASE_SOURCE
+    raise ValueError('D112 4549/c72b portfolio requires K in (256, 512, 768, 1024, 4096, 8192)')
+
+def supports_shape(*, D: int, N: int, K: int) -> bool:
+    if D != FEAT_D:
+        return False
+    if K == OVERLAY_K:
+        return _overlay.supports_shape(D=D, N=N, K=K)
+    if K in BASE_K:
+        return _base.supports_shape(D=D, N=N, K=K)
+    return False
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(D=D, N=N, K=K):
+        raise ValueError('D112 4549/c72b portfolio requires D=112, an owned N multiple, and K in (256, 512, 768, 1024, 4096, 8192)')
+    source = source_for_k(K)
+    child = _overlay if K == OVERLAY_K else _base
+    caller_out = inputs['out']
+    caller_ptr = int(caller_out.data_ptr())
+    child_outputs = child.launch_for_eval(inputs)
+    cluster_ids = child_outputs.get('cluster_ids', child_outputs.get('out'))
+    if cluster_ids is None:
+        raise ValueError(''.join([format(source['id'], ''), ' did not return cluster_ids or out']))
+    returned_ptr = int(cluster_ids.data_ptr())
+    if returned_ptr != caller_ptr:
+        raise ValueError(''.join([format(source['id'], ''), " did not return caller-owned inputs['out']"]))
+    child_trace = dict(child_outputs.get('route_trace') or {})
+    wrapper_entrypoint = ''.join([format(__name__, ''), ':launch_for_eval'])
+    return {'cluster_ids': cluster_ids, 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': TARGET_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': wrapper_entrypoint, 'selected_seed': SEED_ID, 'selected_source': source['id'], 'selected_source_task': source['source_task'], 'selected_source_kernel_task': source['source_kernel_task'], 'selected_source_revision': source['source_revision'], 'selected_source_evidence_revision': source['evidence_revision'], 'selected_source_blob': source['source_blob'], 'selected_source_sha256': source['source_sha256'], 'selected_source_path': source['source_path'], 'selected_source_entrypoint': source['entrypoint'], 'child_selected_route': child_outputs.get('selected_route'), 'child_route_trace': child_trace, 'dispatch_key': 'K', 'dispatch_value': K, 'owned_k': [OVERLAY_K] if K == OVERLAY_K else list(BASE_K), 'caller_output_data_ptr': caller_ptr, 'returned_output_data_ptr': returned_ptr, 'caller_owned_output': True, 'output_dtype': 'int32', 'compute_kernel_count': 1, 'padding_count': 0, 'pack_count': 0, 'fallback_contract_regions': [], 'residual_contract_regions': [], 'global_workspace': False, 'materialized_padding': False, 'production_route': 'weave_only', 'launch_grid': child_trace.get('launch_grid'), 'producer_to_consumer': child_trace.get('producer_to_consumer'), 'B': B, 'N': N, 'D': D, 'K': K}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_weave_evolve_flash_kmeans_assign_e5e1_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_weave_evolve_flash_kmeans_assign_e5e1_v1.py
new file mode 100644
index 00000000..9c4b70f4
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_weave_evolve_flash_kmeans_assign_e5e1_v1.py
@@ -0,0 +1,61 @@
+"""D112 K1024 direct consumer-scoped MMA handoff (minimum architecture: sm_90a).
+
+Eight CTA ranks own disjoint K/8 spans and two four-warp consumer groups own
+disjoint halves of each span.  TMA writes each group's two canonical 8x112
+centroid stages directly.  The owning consumer group loads those stages with
+``ldmatrix.x2`` into the ``mma.sync`` B fragment, so there is no
+canonical-to-MMA-view materialization.  Independent 128-thread named barriers
+protect stage reuse without a 256-thread per-tile rendezvous.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N, BLOCK_K, FEAT_D, THREADS = (64, 8, 112, 256)
+CLUSTER_CTAS, CONSUMER_GROUPS, PIPELINE_STAGES = (8, 2, 2)
+SUPPORTED_K = (1024,)
+X_ELEMS, C_ELEMS = (BLOCK_N * FEAT_D, BLOCK_K * FEAT_D)
+X_BYTES, C_BYTES = (X_ELEMS * 2, C_ELEMS * 2)
+CENTROID_STAGE_COUNT = CONSUMER_GROUPS * PIPELINE_STAGES
+SCORE_BYTES = CONSUMER_GROUPS * 4 * 16 * BLOCK_K * 4
+LOCAL_KEY_BYTES = BLOCK_N * 8
+GROUP_KEY_BYTES = CONSUMER_GROUPS * LOCAL_KEY_BYTES
+CLUSTER_KEY_BYTES = CLUSTER_CTAS * LOCAL_KEY_BYTES
+U32_MASK = 4294967295
+X_RAW_OFFSET = 0
+C_DIRECT_OFFSET = X_RAW_OFFSET + X_BYTES
+X_MMA_OFFSET = C_DIRECT_OFFSET + CENTROID_STAGE_COUNT * C_BYTES
+SCORE_OFFSET = X_MMA_OFFSET + X_BYTES
+GROUP_KEY_OFFSET = SCORE_OFFSET + SCORE_BYTES
+LOCAL_KEY_OFFSET = GROUP_KEY_OFFSET + GROUP_KEY_BYTES
+CLUSTER_KEY_OFFSET = LOCAL_KEY_OFFSET + LOCAL_KEY_BYTES
+SMEM_BYTES = CLUSTER_KEY_OFFSET + CLUSTER_KEY_BYTES
+ROUTE_ID = 'd112_consumer_scoped_direct_mma_view_handoff_weave_evolve_flash_kmeans_assign_e5e1_v1'
+SEED_ID = 'd112-consumer-scoped-direct-mma-view-handoff-weave-evolve-flash-kmeans-assign-e5e1-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [8, 1, 1], "computed_smem_bytes": 46592, "constants": [], "cta_group": 1, "threads": 256}'))
+cluster_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [8, 1, 1], "computed_smem_bytes": 46592, "constants": [], "cta_group": 1, "threads": 256}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [8, 1, 1], "computed_smem_bytes": 46592, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as dirs
+    return dirs()
+
+def _compiled_cluster() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0356"}, "kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", 46592, 256]}'))
+
+def supports_shape(*, D: int, N: int, K: int) -> bool:
+    return D == FEAT_D and N % BLOCK_N == 0 and (K in SUPPORTED_K)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    import torch
+    from .._dispatch_runtime import CUDAKernel
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(D=D, N=N, K=K):
+        raise ValueError('consumer-scoped direct MMA handoff e5e1 requires D=112, N%64=0, and K=1024')
+    cubin, name, smem, threads = _compiled_cluster()
+    grid = (B * (N // BLOCK_N) * CLUSTER_CTAS, 1, 1)
+    with CUDAKernel(cubin, name) as kernel:
+        kernel.launch_cluster(grid=grid, block=(threads, 1, 1), args=[inputs['x'], inputs['centroids'], inputs['c_sq'], inputs['out'], B, N, D, K, N // BLOCK_N], cluster_dims=(CLUSTER_CTAS, 1, 1), shared_mem=smem, stream=torch.cuda.current_stream(), timeout_ms=120000)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': TARGET_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'route_kind': 'eight_owner_consumer_scoped_direct_mma_view_handoff', 'cluster_ctas': CLUSTER_CTAS, 'consumer_groups_per_owner': CONSUMER_GROUPS, 'centroid_pipeline_stages': PIPELINE_STAGES, 'centroids_per_owner': K // CLUSTER_CTAS, 'centroids_per_consumer_group': K // (CLUSTER_CTAS * CONSUMER_GROUPS), 'producer_ownership': 'ranks 0..7 stage points locally; each four-warp group owns two canonical centroid stages', 'reuse_mechanism': 'direct TMA canonical stages consumed by ldmatrix.x2 with independent 128-thread group barriers', 'producer_to_consumer': 'TMA_to_consumer_scoped_canonical_stage_to_ldmatrix_x2_to_mma_sync_to_argmax_to_onchip_cluster_ids', 'overlap_edge': 'centroid_t_plus_1_direct_TMA -> current_centroid_t_mma_and_argmax', 'stage_storage_bytes': C_BYTES, 'split_k_reduction': 'shared-memory intra-owner key merge followed by on-chip cluster merge; no global workspace', 'launch_grid': grid, 'residual_contract_regions': []}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1.py
new file mode 100644
index 00000000..ced7cfee
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1.py
@@ -0,0 +1,43 @@
+"""D112 K-general direct consumer handoff (minimum architecture: sm_90a).
+
+This additive full-bucket entrypoint retains the admitted e5e1 Weave IR:
+direct canonical centroid stages feed ``ldmatrix.x2`` and ``mma.sync`` before
+the owner-local argmax/key merge writes caller-owned cluster IDs.  The lane is
+compiled and validated explicitly for ``sm_100a``.  Every admitted K is a
+multiple of the eight CTA owners, two consumer groups, and the K8 MMA tile, so
+the same dynamic loop topology covers the complete 14-row D112 bucket.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_weave_evolve_flash_kmeans_assign_e5e1_v1 as _direct
+BLOCK_N = _direct.BLOCK_N
+BLOCK_K = _direct.BLOCK_K
+FEAT_D = _direct.FEAT_D
+THREADS = _direct.THREADS
+CLUSTER_CTAS = _direct.CLUSTER_CTAS
+CONSUMER_GROUPS = _direct.CONSUMER_GROUPS
+PIPELINE_STAGES = _direct.PIPELINE_STAGES
+SUPPORTED_K = (256, 512, 768, 1024, 4096, 8192)
+K_PARTITION_QUANTUM = CLUSTER_CTAS * CONSUMER_GROUPS * BLOCK_K
+ROUTE_ID = 'd112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1'
+SEED_ID = 'd112-direct-handoff-full-bucket-weave-evolve-flash-kmeans-assign-4549-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+cluster_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [8, 1, 1], "computed_smem_bytes": 46592, "constants": [], "cta_group": 1, "threads": 256}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [8, 1, 1], "computed_smem_bytes": 46592, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def supports_shape(*, D: int, N: int, K: int) -> bool:
+    return D == FEAT_D and N % BLOCK_N == 0 and (K in SUPPORTED_K) and (K >= K_PARTITION_QUANTUM) and (K % K_PARTITION_QUANTUM == 0)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    import torch
+    from .._dispatch_runtime import CUDAKernel
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(D=D, N=N, K=K):
+        raise ValueError('D112 direct-handoff full bucket requires D=112, N%64=0, and K in (256, 512, 768, 1024, 4096, 8192)')
+    cubin, name, smem, threads = _direct._compiled_cluster()
+    grid = (B * (N // BLOCK_N) * CLUSTER_CTAS, 1, 1)
+    with CUDAKernel(cubin, name) as kernel:
+        kernel.launch_cluster(grid=grid, block=(threads, 1, 1), args=[inputs['x'], inputs['centroids'], inputs['c_sq'], inputs['out'], B, N, D, K, N // BLOCK_N], cluster_dims=(CLUSTER_CTAS, 1, 1), shared_mem=smem, stream=torch.cuda.current_stream(), timeout_ms=120000)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': TARGET_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'route_kind': 'eight_owner_k_general_consumer_scoped_direct_mma_view_handoff', 'cluster_ctas': CLUSTER_CTAS, 'consumer_groups_per_owner': CONSUMER_GROUPS, 'centroid_pipeline_stages': PIPELINE_STAGES, 'centroids_per_owner': K // CLUSTER_CTAS, 'centroids_per_consumer_group': K // (CLUSTER_CTAS * CONSUMER_GROUPS), 'producer_ownership': 'ranks 0..7 stage points locally; each four-warp group owns two canonical centroid stages', 'reuse_mechanism': 'direct TMA canonical stages consumed by ldmatrix.x2 with independent 128-thread group barriers', 'producer_to_consumer': 'TMA_to_consumer_scoped_canonical_stage_to_ldmatrix_x2_to_mma_sync_to_argmax_to_onchip_cluster_ids', 'overlap_edge': 'centroid_t_plus_1_direct_TMA -> current_centroid_t_mma_and_argmax', 'stage_storage_bytes': _direct.C_BYTES, 'split_k_reduction': 'shared-memory intra-owner key merge followed by on-chip cluster merge; no global workspace', 'launch_grid': grid, 'supported_k': SUPPORTED_K, 'residual_contract_regions': []}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1.py
new file mode 100644
index 00000000..278e2044
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1.py
@@ -0,0 +1,154 @@
+"""Exact-guard D112 c829/f826/4549 portfolio (minimum: sm_100a).
+
+The two assigned B4/D112/K1024 rows select the frozen c829 owner-local
+warp-MMA kernel.  B5/N2944/D112/K512 retains the frozen f826 two-owner
+warp-MMA kernel through the 32b2 portfolio, and every other row in the exact
+14-row D112 bucket retains the frozen 4549 child through that same portfolio.
+The host-only composition adds no padding, packing, workspace, fallback, or
+extra GPU launch.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from dataclasses import dataclass
+from threading import RLock
+from typing import Any, Callable
+from . import flash_kmeans_assign_d112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1 as _retained
+from . import flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1 as _c829
+FEAT_D = 112
+ROUTE_ID = 'd112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1'
+SEED_ID = 'd112-f826-c829-full-bucket-weave-evolve-flash-kmeans-assign-a262-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+SHAPE_KEYS = {(2, 2048, 112, 512): 'post_d895_d112_b2_n2048_k512_d112', (4, 8192, 112, 1024): 'post_d895_d112_b4_n8192_k1024_d112', (1, 512, 112, 8192): 'post_d895_d112_b1_n512_k8192_d112', (1, 256, 112, 256): 'post_d895_d112_b1_n256_k256_d112', (3, 3840, 112, 768): 'adjacent_9ca0_d112_tail_div_b3_n3840_k768_d112', (2, 512, 112, 8192): 'adjacent_3328_d112_highk_low_n_b2_n512_k8192_d112', (5, 2176, 112, 512): 'adjacent_5600_d112_odd_tile_tail_b5_n2176_k512_d112', (4, 3456, 112, 256): 'adjacent_a2f8_d112_lowk_tail_b4_n3456_k256_d112', (1, 384, 112, 4096): 'adjacent_8f09_d112_small_highk_b1_n384_k4096_d112', (3, 768, 112, 8192): 'adjacent_d9d5_d112_highk_request_b3_n768_k8192_d112', (5, 2944, 112, 512): 'adjacent_68cf_d112_tail_b5_n2944_k512_d112', (2, 3200, 112, 768): 'adjacent_c44f_d112_odd_tail_b2_n3200_k768_d112', (1, 1408, 112, 4096): 'adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112', (4, 3712, 112, 1024): 'adjacent_ef00_d112_odd_tail_b4_n3712_k1024_d112'}
+EXACT_C829_KEYS = frozenset({(4, 8192, 112, 1024), (4, 3712, 112, 1024)})
+EXACT_F826_KEY = (5, 2944, 112, 512)
+C829_SOURCE = {'id': 'c829_exact_k1024', 'source_task': 'weave-evolve-flash-kmeans-assign-ab9a', 'implementation_revision': 'e3d609c6c0e68796f1c9273a6e113205c5fcea1e', 'representative_measurement_revision': '2def42e0b313de745896952a8f17d1f3c78680a8', 'timed_source_blob': '6bb66ffdeb5da35094c3e2ee02932ee1cac2432e', 'timed_source_sha256': '3205f28d937bf9ff1616bbb0eb35e8765f13447a9802cb9807dc28d46b1ab27f', 'executable_body_blob': '9d0b7cb69e1274850fc60be2f6f1f78002f2b23f', 'executable_body_sha256': '72cc676d4ddcb32c40cabb01e7f2ff9ffc1138d8449ee49b38ec552c7a54b720', 'final_source_blob': '4ce799909b9b93a64c272c831b55ad4c13186fb3', 'final_source_sha256': '81bf56e0b8cbb8962f9852159096fa1df52c769350fd46412e782c78a7ded010', 'source_path': 'loom/examples/weave/flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1.py', 'entrypoint': ''.join([format(_c829.__name__, ''), ':launch_for_eval'])}
+F826_SOURCE = _decode_capture(_json_loads('{"__dict_items__": [["id", "f826_exact_k512"], ["source_task", "weave-evolve-flash-kmeans-assign-f826"], ["implementation_commit", "124ef2ad24c3ac86c063e69da0cb0c5d7fca0174"], ["implementation_source_blob", "3a1dee841855c15481a740f28ba07142e4fdbb29"], ["implementation_source_sha256", "99c44085f258a699b7e3372115cc82aa969643addae0797bf47c0758cad8cf0f"], ["measurement_source_blob", "a3dcf64c5014d223127bf0a39b13c485cf140c48"], ["measurement_source_sha256", "fd3e97727367d3acbbd3b994a86cb25f563ce3f32544a724dbd09f05a70a88ce"], ["final_source_blob", "f30b546e70bfbc80a94547458d857ead0de5e320"], ["final_source_sha256", "47c2d22bbb00b3061d268fae9c405e62257bde8ba43ba33fc1124d456572cd63"], ["source_path", "loom/examples/weave/flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1.py"], ["entrypoint", "loom.examples.weave.flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1:launch_for_eval"]]}'))
+BASE_4549_SOURCE = _decode_capture(_json_loads('{"__dict_items__": [["id", "base_portfolio"], ["source_task", "weave-evolve-flash-kmeans-assign-4549"], ["source_kernel_task", "weave-evolve-flash-kmeans-assign-4549"], ["source_revision", "21c48b897873f6a5e631c7fccd320c35d73ae6d5"], ["evidence_revision", "713ee91855069de8580152c20ec37b5ab4569c29"], ["source_blob", "9d4da373afd9869c2718fffaf62f4230f4bb2482"], ["source_sha256", "ef1b1b574a5ce0516c745a5c28fa381a47e8a5e5c9ad49e35a93bff496c43b64"], ["source_path", "loom/examples/weave/flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1.py"], ["entrypoint", "loom.examples.weave.flash_kmeans_assign_d112_direct_handoff_full_bucket_weave_evolve_flash_kmeans_assign_4549_v1:launch_for_eval"]]}'))
+RETAINED_PORTFOLIO_SOURCE = {'id': 'portfolio_32b2', 'source_task': 'generalize-auto-tuning-flash-kmeans-assign-32b2', 'source_blob': '2acba116338583b0f55b06b49b1882779b440b09', 'source_sha256': 'ba9da56a4ff50c211d201dcbfbb69d8d1cb31464c2628dd5110be1320b626087', 'source_path': 'loom/examples/weave/flash_kmeans_assign_d112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1.py', 'entrypoint': ''.join([format(_retained.__name__, ''), ':launch_for_eval'])}
+_PREPARE_LOCK = RLock()
+
+def _shape(inputs: dict[str, Any]) -> tuple[int, int, int, int]:
+    return tuple((int(inputs[name]) for name in ('B', 'N', 'D', 'K')))
+
+def _shape_key(key: tuple[int, int, int, int]) -> str:
+    try:
+        return SHAPE_KEYS[key]
+    except KeyError as exc:
+        raise ValueError(''.join(['a262 portfolio rejects unassigned shape ', format(repr(key), '')])) from exc
+
+def supports_shape(*, B: int, D: int, N: int, K: int) -> bool:
+    return (int(B), int(N), int(D), int(K)) in SHAPE_KEYS
+
+def source_for_shape(*, B: int, N: int, D: int, K: int) -> dict[str, Any]:
+    key = (int(B), int(N), int(D), int(K))
+    _shape_key(key)
+    if key in EXACT_C829_KEYS:
+        return dict(C829_SOURCE)
+    return dict(_retained.source_for_shape(B=B, N=N, D=D, K=K))
+
+def _resolve_route(inputs: dict[str, Any], *, force_c829: bool=False, force_f826: bool=False) -> tuple[Callable[[dict[str, Any]], dict[str, Any]], dict[str, Any], str, str]:
+    key = _shape(inputs)
+    _shape_key(key)
+    if force_c829 and force_f826:
+        raise ValueError('only one forced route may be requested')
+    if force_c829 and key not in EXACT_C829_KEYS:
+        raise ValueError('forced c829 requires one of the two exact K1024 keys')
+    if force_f826 and key != EXACT_F826_KEY:
+        raise ValueError('forced f826 requires exact B5/N2944/D112/K512')
+    if key in EXACT_C829_KEYS:
+        return (_c829.launch_for_eval, dict(C829_SOURCE), 'guard_exact_two_k1024_keys_c829_v1', '(B, N, D, K) in {(4, 8192, 112, 1024), (4, 3712, 112, 1024)}')
+    source = source_for_shape(B=key[0], N=key[1], D=key[2], K=key[3])
+    if key == EXACT_F826_KEY:
+        return (_retained.launch_for_eval_forced_f826, source, 'guard_exact_b5_n2944_d112_k512_f826_v1', 'B == 5 and N == 2944 and D == 112 and K == 512')
+    return (_retained.launch_for_eval, source, 'guard_assigned_d112_bucket_retained_4549_v1', 'assigned D112 bucket key excluding the c829 and f826 exact guards')
+
+def _source_value(source: dict[str, Any], suffix: str) -> Any:
+    for prefix in ('final_source', 'source', 'executable_body'):
+        value = source.get(''.join([format(prefix, ''), '_', format(suffix, '')]))
+        if value is not None:
+            return value
+    return None
+
+def _finish_outputs(inputs: dict[str, Any], child_outputs: dict[str, Any], source: dict[str, Any], guard_id: str, guard_condition: str) -> dict[str, Any]:
+    B, N, D, K = _shape(inputs)
+    key = (B, N, D, K)
+    caller_out = inputs['out']
+    cluster_ids = child_outputs.get('cluster_ids', child_outputs.get('out'))
+    if cluster_ids is None:
+        raise ValueError(''.join([format(source['id'], ''), ' did not return cluster_ids or out']))
+    caller_ptr = int(caller_out.data_ptr())
+    returned_ptr = int(cluster_ids.data_ptr())
+    if returned_ptr != caller_ptr:
+        raise ValueError(''.join([format(source['id'], ''), " replaced caller-owned inputs['out']"]))
+    child_trace = dict(child_outputs.get('route_trace') or {})
+    specialized = key in EXACT_C829_KEYS or key == EXACT_F826_KEY
+    return {'cluster_ids': cluster_ids, 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': _shape_key(key), 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': _c829.SEED_ID if key in EXACT_C829_KEYS else child_trace.get('selected_seed'), 'portfolio_id': ROUTE_ID, 'portfolio_seed_id': SEED_ID, 'retained_portfolio': RETAINED_PORTFOLIO_SOURCE['id'], 'selected_source': source['id'], 'selected_source_task': source['source_task'], 'selected_source_revision': source.get('implementation_revision', source.get('implementation_commit', source.get('source_revision'))), 'selected_source_blob': _source_value(source, 'blob'), 'selected_source_sha256': _source_value(source, 'sha256'), 'selected_source_path': source['source_path'], 'selected_source_entrypoint': source['entrypoint'], 'child_selected_route': child_outputs.get('selected_route'), 'child_route_trace': child_trace, 'route_kind': 'specialized' if specialized else 'general', 'route_source': 'shape-specific-seed' if specialized else 'generated-variant', 'guard_id': guard_id, 'guard_condition': guard_condition, 'classification': 'seed-consumed' if specialized else 'route-ok', 'dispatch_key': 'B,N,D,K', 'dispatch_value': [B, N, D, K], 'caller_output_data_ptr': caller_ptr, 'returned_output_data_ptr': returned_ptr, 'caller_owned_output': True, 'output_dtype': 'int32', 'compute_kernel_count': 1, 'padding_count': 0, 'pack_count': 0, 'fallback_contract_regions': [], 'residual_contract_regions': [], 'global_workspace': False, 'materialized_padding': False, 'production_route': 'weave_only', 'launch_grid': child_trace.get('launch_grid'), 'producer_to_consumer': child_trace.get('producer_to_consumer'), 'primitive_family': child_trace.get('primitive_family', 'warp_mma_sync'), 'B': B, 'N': N, 'D': D, 'K': K}}
+
+def _launch(inputs: dict[str, Any], *, force_c829: bool=False, force_f826: bool=False) -> dict[str, Any]:
+    child, source, guard_id, guard_condition = _resolve_route(inputs, force_c829=force_c829, force_f826=force_f826)
+    return _finish_outputs(inputs, child(inputs), source, guard_id, guard_condition)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Launch exactly one frozen child through the caller-owned output ABI."""
+    return _launch(inputs)
+
+def launch_for_eval_forced_c829(inputs: dict[str, Any]) -> dict[str, Any]:
+    return _launch(inputs, force_c829=True)
+
+def launch_for_eval_forced_f826(inputs: dict[str, Any]) -> dict[str, Any]:
+    return _launch(inputs, force_f826=True)
+
+@dataclass(frozen=True)
+class PreparedPortfolioPlan:
+    inputs: dict[str, Any]
+    selected_route: str
+    selected_source: str
+    guard_id: str
+    direct_launcher: Callable[..., dict[str, Any]]
+    launch_count: int
+    device_index: int
+    stream: Any
+    stream_handle: int
+    caller_output_data_ptr: int
+    direct_launcher_token: str
+
+    def launch(self, *, stream: Any=None, timeout_ms: float | None=None) -> dict[str, Any]:
+        import torch
+        with torch.cuda.device(self.device_index):
+            resolved_stream = self.stream if stream is None else stream
+            if int(resolved_stream.cuda_stream) != self.stream_handle:
+                raise RuntimeError('prepared a262 portfolio plan is stream-bound')
+            if int(self.inputs['out'].data_ptr()) != self.caller_output_data_ptr:
+                raise RuntimeError('prepared a262 caller output was replaced')
+            return self.direct_launcher(self.inputs, stream=None, timeout_ms=timeout_ms)
+
+def prepare_launch_plan(inputs: dict[str, Any], *, stream: Any=None, force_c829: bool=False, force_f826: bool=False) -> PreparedPortfolioPlan:
+    """Resolve and capture one stable direct child launch token."""
+    import torch
+    from .._dispatch_runtime import detect_gpu_arch
+    from .._dispatch_runtime import capture_kernel_launches
+    device_index = inputs['x'].device.index
+    if device_index is None:
+        device_index = torch.cuda.current_device()
+    device_index = int(device_index)
+    with torch.cuda.device(device_index):
+        resolved_stream = torch.cuda.current_stream(device_index) if stream is None else stream
+        stream_device = getattr(resolved_stream, 'device', None)
+        stream_device_index = getattr(stream_device, 'index', stream_device)
+        if stream_device_index is not None and int(stream_device_index) != device_index:
+            raise ValueError('prepared a262 stream device does not match inputs')
+        if detect_gpu_arch() not in {'sm_100a', 'sm_103a'}:
+            raise ValueError('a262 prepared routes require sm_100a or sm_103a')
+        child, source, guard_id, guard_condition = _resolve_route(inputs, force_c829=force_c829, force_f826=force_f826)
+        with _PREPARE_LOCK:
+            with capture_kernel_launches(stream=resolved_stream) as captured:
+                child_outputs = child(inputs)
+            prepared_result = _finish_outputs(inputs, child_outputs, source, guard_id, guard_condition)
+            direct_launcher = captured.bind(prepared_result)
+    return PreparedPortfolioPlan(inputs=inputs, selected_route=ROUTE_ID, selected_source=source['id'], guard_id=guard_id, direct_launcher=direct_launcher, launch_count=direct_launcher.launch_count, device_index=device_index, stream=resolved_stream, stream_handle=int(resolved_stream.cuda_stream), caller_output_data_ptr=int(inputs['out'].data_ptr()), direct_launcher_token=''.join([format(type(direct_launcher).__module__, ''), '.', format(type(direct_launcher).__qualname__, ''), '@', format(id(direct_launcher), ''.join(['x']))]))
+
+def launch_prepared(plan: PreparedPortfolioPlan, *, stream: Any=None, timeout_ms: float | None=None) -> dict[str, Any]:
+    if not isinstance(plan, PreparedPortfolioPlan):
+        raise TypeError('plan must be returned by prepare_launch_plan')
+    return plan.launch(stream=stream, timeout_ms=timeout_ms)
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1.py
new file mode 100644
index 00000000..e02905a6
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1.py
@@ -0,0 +1,134 @@
+"""Namespaced D112 portfolio with one exact f826 guard (minimum: sm_100a).
+
+The guard ``B=5, N=2944, D=112, K=512`` selects the validated f826
+two-owner warp-MMA seed.  K=1024 remains on the frozen c72b overlay and every
+other admitted D112 row remains on frozen 4549.  This module is additive: it
+does not alter the production dispatcher or any child kernel schedule.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from dataclasses import dataclass
+from threading import RLock
+from typing import Any, Callable
+from . import flash_kmeans_assign_d112_4549_c72b_k1024_overlay_weave_evolve_flash_kmeans_assign_3ae6_v1 as _frozen
+from . import flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1 as _f826
+FEAT_D = 112
+EXACT_F826_KEY = (5, 2944, 112, 512)
+SUPPORTED_K = _frozen.SUPPORTED_K
+ROUTE_ID = 'd112_f826_exact_portfolio_generalize_auto_tuning_flash_kmeans_assign_8d82_v1'
+SEED_ID = 'd112-overlay-plus-f826-exact-k512-consumption-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+EXACT_SHAPE_KEY = 'adjacent_68cf_d112_tail_b5_n2944_k512_d112'
+EXACT_GUARD_ID = 'guard_exact_b5_n2944_d112_k512_f826_v1'
+EXACT_GUARD_CONDITION = 'B == 5 and N == 2944 and D == 112 and K == 512'
+F826_SOURCE = {'id': 'f826_exact_k512', 'source_task': 'weave-evolve-flash-kmeans-assign-f826', 'implementation_commit': '124ef2ad24c3ac86c063e69da0cb0c5d7fca0174', 'implementation_source_blob': '3a1dee841855c15481a740f28ba07142e4fdbb29', 'implementation_source_sha256': '99c44085f258a699b7e3372115cc82aa969643addae0797bf47c0758cad8cf0f', 'measurement_source_blob': 'a3dcf64c5014d223127bf0a39b13c485cf140c48', 'measurement_source_sha256': 'fd3e97727367d3acbbd3b994a86cb25f563ce3f32544a724dbd09f05a70a88ce', 'final_source_blob': 'f30b546e70bfbc80a94547458d857ead0de5e320', 'final_source_sha256': '47c2d22bbb00b3061d268fae9c405e62257bde8ba43ba33fc1124d456572cd63', 'source_path': 'loom/examples/weave/flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1.py', 'entrypoint': ''.join([format(_f826.__name__, ''), ':launch_for_eval'])}
+_PREPARE_LOCK = RLock()
+
+def _shape(inputs: dict[str, Any]) -> tuple[int, int, int, int]:
+    return tuple((int(inputs[key]) for key in ('B', 'N', 'D', 'K')))
+
+def _is_exact_f826(*, B: int, N: int, D: int, K: int) -> bool:
+    return (B, N, D, K) == EXACT_F826_KEY
+
+def supports_shape(*, D: int, N: int, K: int, B: int | None=None) -> bool:
+    del B
+    return _frozen.supports_shape(D=D, N=N, K=K)
+
+def source_for_shape(*, B: int, N: int, D: int, K: int) -> dict[str, Any]:
+    if _is_exact_f826(B=B, N=N, D=D, K=K):
+        return dict(F826_SOURCE)
+    return dict(_frozen.source_for_k(K))
+
+def _resolve_route(inputs: dict[str, Any], *, force_f826: bool=False) -> tuple[Callable[[dict[str, Any]], dict[str, Any]], dict[str, Any], str, str]:
+    B, N, D, K = _shape(inputs)
+    if not supports_shape(B=B, D=D, N=N, K=K):
+        raise ValueError('8d82 D112 portfolio requires D=112, N%64=0, and K in (256, 512, 768, 1024, 4096, 8192)')
+    exact = _is_exact_f826(B=B, N=N, D=D, K=K)
+    if force_f826 and (not exact):
+        raise ValueError('forced f826 route requires exact B5/N2944/D112/K512')
+    if exact:
+        return (_f826.launch_for_eval, dict(F826_SOURCE), EXACT_GUARD_ID, EXACT_GUARD_CONDITION)
+    source = dict(_frozen.source_for_k(K))
+    return (_frozen.launch_for_eval, source, 'guard_frozen_3ae6_k_ownership', 'K == 1024 selects c72b; other admitted K values select 4549')
+
+def _finish_outputs(inputs: dict[str, Any], child_outputs: dict[str, Any], source: dict[str, Any], guard_id: str, guard_condition: str) -> dict[str, Any]:
+    B, N, D, K = _shape(inputs)
+    caller_out = inputs['out']
+    cluster_ids = child_outputs.get('cluster_ids', child_outputs.get('out'))
+    if cluster_ids is None:
+        raise ValueError(''.join([format(source['id'], ''), ' did not return cluster_ids or out']))
+    caller_ptr = int(caller_out.data_ptr())
+    returned_ptr = int(cluster_ids.data_ptr())
+    if returned_ptr != caller_ptr:
+        raise ValueError(''.join([format(source['id'], ''), " did not retain caller-owned inputs['out']"]))
+    child_trace = dict(child_outputs.get('route_trace') or {})
+    exact = source['id'] == F826_SOURCE['id']
+    return {'cluster_ids': cluster_ids, 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': EXACT_SHAPE_KEY if exact else TARGET_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': _f826.SEED_ID if exact else child_trace.get('selected_seed'), 'expected_seed': _f826.SEED_ID if exact else child_trace.get('selected_seed'), 'portfolio_id': ROUTE_ID, 'portfolio_seed_id': SEED_ID, 'selected_source': source['id'], 'selected_source_task': source['source_task'], 'selected_source_revision': source.get('implementation_commit', source.get('source_revision')), 'selected_source_blob': source.get('final_source_blob', source.get('source_blob')), 'selected_source_sha256': source.get('final_source_sha256', source.get('source_sha256')), 'selected_source_path': source['source_path'], 'selected_source_entrypoint': source['entrypoint'], 'child_selected_route': child_outputs.get('selected_route'), 'child_route_trace': child_trace, 'route_kind': 'specialized' if exact else 'general', 'route_source': 'shape-specific-seed' if exact else 'generated-variant', 'guard_id': guard_id, 'guard_condition': guard_condition, 'classification': 'seed-consumed' if exact else 'route-ok', 'dispatch_key': 'B,N,D,K' if exact else 'K', 'dispatch_value': [B, N, D, K] if exact else K, 'caller_output_data_ptr': caller_ptr, 'returned_output_data_ptr': returned_ptr, 'caller_owned_output': True, 'output_dtype': 'int32', 'compute_kernel_count': 1, 'padding_count': 0, 'pack_count': 0, 'fallback_contract_regions': [], 'residual_contract_regions': [], 'global_workspace': False, 'materialized_padding': False, 'production_route': 'weave_only', 'launch_grid': child_trace.get('launch_grid'), 'producer_to_consumer': child_trace.get('producer_to_consumer'), 'B': B, 'N': N, 'D': D, 'K': K}}
+
+def _launch(inputs: dict[str, Any], *, force_f826: bool=False) -> dict[str, Any]:
+    child, source, guard_id, guard_condition = _resolve_route(inputs, force_f826=force_f826)
+    return _finish_outputs(inputs, child(inputs), source, guard_id, guard_condition)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Launch the guarded namespaced portfolio through its public ABI."""
+    return _launch(inputs)
+
+def launch_for_eval_forced_f826(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Force the exact f826 route for exported-ABI correctness evidence."""
+    return _launch(inputs, force_f826=True)
+
+@dataclass(frozen=True)
+class PreparedPortfolioPlan:
+    inputs: dict[str, Any]
+    selected_route: str
+    selected_source: str
+    guard_id: str
+    direct_launcher: Callable[..., dict[str, Any]]
+    launch_count: int
+    device_index: int
+    stream: Any
+    stream_handle: int
+    caller_output_data_ptr: int
+    direct_launcher_token: str
+
+    def launch(self, *, stream: Any=None, timeout_ms: float | None=None) -> dict[str, Any]:
+        """Submit the captured child launch without re-entering either dispatcher."""
+        import torch
+        with torch.cuda.device(self.device_index):
+            resolved_stream = self.stream if stream is None else stream
+            if int(resolved_stream.cuda_stream) != self.stream_handle:
+                raise RuntimeError('prepared 8d82 portfolio plan is stream-bound')
+            if int(self.inputs['out'].data_ptr()) != self.caller_output_data_ptr:
+                raise RuntimeError('prepared 8d82 portfolio caller output was replaced')
+            return self.direct_launcher(self.inputs, stream=None, timeout_ms=timeout_ms)
+
+def prepare_launch_plan(inputs: dict[str, Any], *, stream: Any=None, force_f826: bool=False) -> PreparedPortfolioPlan:
+    """Resolve the exact route once and capture one stable direct launch token."""
+    import torch
+    from .._dispatch_runtime import detect_gpu_arch
+    from .._dispatch_runtime import capture_kernel_launches
+    device_index = inputs['x'].device.index
+    if device_index is None:
+        device_index = torch.cuda.current_device()
+    device_index = int(device_index)
+    with torch.cuda.device(device_index):
+        resolved_stream = torch.cuda.current_stream(device_index) if stream is None else stream
+        stream_device = getattr(resolved_stream, 'device', None)
+        stream_device_index = getattr(stream_device, 'index', stream_device)
+        if stream_device_index is not None and int(stream_device_index) != device_index:
+            raise ValueError('prepared 8d82 stream device does not match input device')
+        if detect_gpu_arch() not in {'sm_100a', 'sm_103a'}:
+            raise ValueError('8d82 prepared routes require sm_100a or sm_103a')
+        child, source, guard_id, guard_condition = _resolve_route(inputs, force_f826=force_f826)
+        with _PREPARE_LOCK:
+            with capture_kernel_launches(stream=resolved_stream) as captured:
+                child_outputs = child(inputs)
+            prepared_result = _finish_outputs(inputs, child_outputs, source, guard_id, guard_condition)
+            direct_launcher = captured.bind(prepared_result)
+    return PreparedPortfolioPlan(inputs=inputs, selected_route=ROUTE_ID, selected_source=source['id'], guard_id=guard_id, direct_launcher=direct_launcher, launch_count=direct_launcher.launch_count, device_index=device_index, stream=resolved_stream, stream_handle=int(resolved_stream.cuda_stream), caller_output_data_ptr=int(inputs['out'].data_ptr()), direct_launcher_token=''.join([format(type(direct_launcher).__module__, ''), '.', format(type(direct_launcher).__qualname__, ''), '@', format(id(direct_launcher), ''.join(['x']))]))
+
+def launch_prepared(plan: PreparedPortfolioPlan, *, stream: Any=None, timeout_ms: float | None=None) -> dict[str, Any]:
+    if not isinstance(plan, PreparedPortfolioPlan):
+        raise TypeError('plan must be returned by prepare_launch_plan')
+    return plan.launch(stream=stream, timeout_ms=timeout_ms)
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1.py
new file mode 100644
index 00000000..6c47e4ad
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1.py
@@ -0,0 +1,68 @@
+"""D112 K1024 owner-local streamed warp-MMA path (minimum arch: sm_90a).
+
+One ordinary CTA owns one N64 point tile.  Warp 0 loads the point tile once
+and streams alternating K32 centroid slabs.  Four row-owner warps retain the
+same 16 point rows for the full K1024 scan, consume each slab with
+``ldmatrix`` + ``mma.sync``, and write caller-owned cluster IDs directly.
+
+This physical DAG has no K-sharded CTA owners, cluster/DSM handoff, TMEM,
+global workspace, padding, pack kernel, or post-kernel reduction.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 64
+BLOCK_K = 32
+FEAT_D = 112
+FEATURE_TILES = FEAT_D // 16
+LOAD_WARPS = 1
+COMPUTE_WARPS = 4
+THREADS = (LOAD_WARPS + COMPUTE_WARPS) * 32
+K_TILES = 1024 // BLOCK_K
+K_TILE_PAIRS = K_TILES // 2
+X_ELEMS = BLOCK_N * FEAT_D
+C_ELEMS = BLOCK_K * FEAT_D
+X_BYTES = X_ELEMS * 2
+C_BYTES = C_ELEMS * 2
+X_OFFSET = 0
+C0_OFFSET = X_OFFSET + X_BYTES
+C1_OFFSET = C0_OFFSET + C_BYTES
+SMEM_BYTES = C1_OFFSET + C_BYTES
+ROUTE_ID = 'd112_k1024_owner_local_warp_mma_distinct_workfeed_weave_evolve_flash_kmeans_assign_c829_v1'
+SEED_ID = 'd112-k1024-owner-local-warp-mma-distinct-workfeed-weave-evolve-flash-kmeans-assign-c829-v1'
+TARGET_SHAPE = 'post_d895_d112_b4_n8192_k1024_d112'
+CAPABILITY_SHAPE_KEYS = (TARGET_SHAPE, 'adjacent_ef00_d112_odd_tail_b4_n3712_k1024_d112')
+flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 29696, "constants": [], "cta_group": 1, "threads": 160}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 29696, "constants": [], "cta_group": 1, "threads": 160}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as include_dirs
+    return include_dirs()
+
+def _compiled() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0353"}, "kernel_flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1", 29696, 160]}'))
+
+def supports_shape(*, B: int, D: int, N: int, K: int) -> bool:
+    return B == 4 and D == FEAT_D and (N in (8192, 3712)) and (K == 1024)
+
+def _shape_key(*, B: int, N: int, D: int, K: int) -> str:
+    if (B, N, D, K) == (4, 8192, 112, 1024):
+        return CAPABILITY_SHAPE_KEYS[0]
+    if (B, N, D, K) == (4, 3712, 112, 1024):
+        return CAPABILITY_SHAPE_KEYS[1]
+    raise ValueError(''.join(['unassigned D112 K1024 capability shape ', format(repr((B, N, D, K)), '')]))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    import torch
+    from .._dispatch_runtime import CUDAKernel
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(B=B, D=D, N=N, K=K):
+        raise ValueError('c829 owner-local warp-MMA seed admits only B4/D112/K1024 with N in (8192, 3712)')
+    cubin, name, smem, threads = _compiled()
+    grid = (B * (N // BLOCK_N), 1, 1)
+    with CUDAKernel(cubin, name) as kernel:
+        kernel.launch(grid=grid, block=(threads, 1, 1), args=[inputs['x'], inputs['centroids'], inputs['c_sq'], inputs['out'], B, N, D, K, N // BLOCK_N], shared_mem=smem, stream=torch.cuda.current_stream(), timeout_ms=120000)
+    shape_key = _shape_key(B=B, N=N, D=D, K=K)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': shape_key, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'route_kind': 'single_cta_owner_local_k32_streamed_warp_mma', 'primitive_family': 'warp_mma_sync', 'compute_kernel_count': 1, 'cluster_ctas': 1, 'cta_group': 1, 'point_tile': BLOCK_N, 'centroid_tile': BLOCK_K, 'loader_warps': LOAD_WARPS, 'row_owner_warps': COMPUTE_WARPS, 'producer_ownership': 'warp 0 stages one shared point tile and alternating full-K centroid slabs', 'consumer_ownership': 'four row-owner warps retain disjoint 16-row spans for all K1024', 'producer_to_consumer': 'bulk_gmem_to_double_buffered_smem_to_ldmatrix_to_mma_sync_to_owner_local_argmax_to_caller_cluster_ids', 'split_k_reduction': 'none', 'global_workspace': False, 'padding_count': 0, 'pack_count': 0, 'fallback_contract_regions': [], 'residual_contract_regions': [], 'launch_grid': grid, 'num_n_tiles': N // BLOCK_N, 'shared_pool_bytes': SMEM_BYTES, 'shared_storage_bytes': int(ir.computed_smem_bytes)}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1.py
new file mode 100644
index 00000000..d455e7c2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1.py
@@ -0,0 +1,66 @@
+"""D112 K512 two-owner peer-only warp-MMA path (minimum architecture: sm_90a).
+
+Two independent ``cta_group=1`` owners split K512 into disjoint K256 spans.
+Each owner uses two four-warp consumer groups with direct TMA centroid stages,
+``ldmatrix.x2``, and ``mma.sync`` before locally merging packed argmax keys.
+Rank 1 sends one 512-byte key slab to rank 0; rank 0 retains its local slab and
+writes caller-owned ``int32`` cluster IDs without a self-copy or workspace.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N, BLOCK_K, FEAT_D, THREADS = (64, 8, 112, 256)
+CLUSTER_CTAS, CONSUMER_GROUPS, PIPELINE_STAGES = (2, 2, 2)
+SUPPORTED_K = (512,)
+X_ELEMS, C_ELEMS = (BLOCK_N * FEAT_D, BLOCK_K * FEAT_D)
+X_BYTES, C_BYTES = (X_ELEMS * 2, C_ELEMS * 2)
+CENTROID_STAGE_COUNT = CONSUMER_GROUPS * PIPELINE_STAGES
+SCORE_BYTES = CONSUMER_GROUPS * 4 * 16 * BLOCK_K * 4
+LOCAL_KEY_BYTES = BLOCK_N * 8
+GROUP_KEY_BYTES = CONSUMER_GROUPS * LOCAL_KEY_BYTES
+PEER_KEY_BYTES = LOCAL_KEY_BYTES
+U32_MASK = 4294967295
+X_RAW_OFFSET = 0
+C_DIRECT_OFFSET = X_RAW_OFFSET + X_BYTES
+X_MMA_OFFSET = C_DIRECT_OFFSET + CENTROID_STAGE_COUNT * C_BYTES
+SCORE_OFFSET = X_MMA_OFFSET + X_BYTES
+GROUP_KEY_OFFSET = SCORE_OFFSET + SCORE_BYTES
+LOCAL_KEY_OFFSET = GROUP_KEY_OFFSET + GROUP_KEY_BYTES
+PEER_KEY_OFFSET = LOCAL_KEY_OFFSET + LOCAL_KEY_BYTES
+SMEM_BYTES = PEER_KEY_OFFSET + PEER_KEY_BYTES
+ROUTE_ID = 'd112_k512_two_owner_peer_only_mma_weave_evolve_flash_kmeans_assign_f826_v1'
+SEED_ID = 'd112-k512-two-owner-peer-only-mma-weave-evolve-flash-kmeans-assign-f826-v1'
+TARGET_SHAPE = 'adjacent_68cf_d112_tail_b5_n2944_k512_d112'
+flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [2, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 256}'))
+cluster_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [2, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 256}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1", "arg_keys": ["x", "centroids", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles"], "cluster_dims": [2, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as dirs
+    return dirs()
+
+def _compiled_cluster() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0354"}, "kernel_flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1", 43008, 256]}'))
+
+def supports_shape(*, D: int, N: int, K: int) -> bool:
+    return D == FEAT_D and N % BLOCK_N == 0 and (K in SUPPORTED_K)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    import torch
+    from .._dispatch_runtime import CUDAKernel
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(D=D, N=N, K=K):
+        raise ValueError('two-owner peer-only MMA f826 requires D=112, N%64=0, and K=512')
+    caller_out = inputs['out']
+    caller_ptr = int(caller_out.data_ptr())
+    cubin, name, smem, threads = _compiled_cluster()
+    num_n_tiles = N // BLOCK_N
+    grid = (B * num_n_tiles * CLUSTER_CTAS, 1, 1)
+    with CUDAKernel(cubin, name) as kernel:
+        kernel.launch_cluster(grid=grid, block=(threads, 1, 1), args=[inputs['x'], inputs['centroids'], inputs['c_sq'], caller_out, B, N, D, K, num_n_tiles], cluster_dims=(CLUSTER_CTAS, 1, 1), shared_mem=smem, stream=torch.cuda.current_stream(), timeout_ms=120000)
+    returned_ptr = int(caller_out.data_ptr())
+    if returned_ptr != caller_ptr:
+        raise ValueError('two-owner peer-only MMA did not retain caller-owned out')
+    return {'cluster_ids': caller_out, 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': TARGET_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'route_kind': 'd112_k512_two_owner_peer_only_warp_mma', 'cluster_ctas': CLUSTER_CTAS, 'cta_group': 1, 'consumer_groups_per_owner': CONSUMER_GROUPS, 'centroid_pipeline_stages': PIPELINE_STAGES, 'centroids_per_owner': K // CLUSTER_CTAS, 'centroids_per_consumer_group': K // (CLUSTER_CTAS * CONSUMER_GROUPS), 'producer_ownership': 'ranks 0..1 independently own K256; each four-warp group owns two direct canonical centroid stages', 'reuse_mechanism': 'direct TMA canonical stages consumed by ldmatrix.x2 with independent 128-thread group barriers', 'producer_to_consumer': 'D112_TMA_to_ldmatrix_x2_to_mma_sync_to_local_two_group_argmax_to_one_peer_key_handoff_to_caller_cluster_ids', 'split_k_reduction': 'per-owner shared two-group key merge; one rank1-to-rank0 peer slab; rank0 retains local slab', 'remote_producer_count': 1, 'peer_key_transaction_bytes': PEER_KEY_BYTES, 'rank0_self_copy': False, 'caller_output_data_ptr': caller_ptr, 'returned_output_data_ptr': returned_ptr, 'caller_owned_output': True, 'output_dtype': 'int32', 'compute_kernel_count': 1, 'padding_count': 0, 'pack_count': 0, 'global_workspace': False, 'fallback_contract_regions': [], 'residual_contract_regions': [], 'launch_grid': grid, 'B': B, 'N': N, 'D': D, 'K': K, 'num_n_tiles': num_n_tiles}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1.py
new file mode 100644
index 00000000..4100bae3
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1.py
@@ -0,0 +1,87 @@
+"""D112 shared-point dual-independent-issuer tcgen05/TMEM assignment.
+
+Minimum architecture: sm_100a.  A dedicated point producer stages the seven
+native D16 slices of each N128 tile exactly once.  Two independently
+synchronized centroid-owner pipelines consume that shared point tile through
+distinct tcgen05 issuer warps and disjoint K64 TMEM score slots, merge ordered
+argmax keys on chip, and write the caller-owned ``cluster_ids`` tensor.  Every
+issuer owns its operand-ready, score-complete, readback-complete, and recycle
+phase state.  The production launch is Weave-only: there is no D128 adapter,
+DSM point fanout, global workspace, or external fallback.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N, BLOCK_K, FEAT_D, FEAT_CHUNK = (128, 64, 112, 16)
+FEATURE_TILES = FEAT_D // FEAT_CHUNK
+OWNER_SLOTS, COMPUTE_WARPS = (2, 4)
+THREADS = 13 * 32
+X_SLICE_BYTES = BLOCK_N * FEAT_CHUNK * 2
+C_SLICE_BYTES = BLOCK_K * FEAT_CHUNK * 2
+LOCAL_KEY_BYTES = BLOCK_N * 8
+X_BYTES = FEATURE_TILES * X_SLICE_BYTES
+C0_OFFSET = X_BYTES
+C1_OFFSET = C0_OFFSET + C_SLICE_BYTES
+KEY0_OFFSET = C1_OFFSET + C_SLICE_BYTES
+KEY1_OFFSET = KEY0_OFFSET + LOCAL_KEY_BYTES
+SMEM_BYTES = KEY1_OFFSET + LOCAL_KEY_BYTES
+U32_MASK = 4294967295
+TCGEN05_ARCHES = frozenset({'sm_100a', 'sm_103a'})
+ROUTE_ID = 'd112_shared_point_dual_issuer_tcgen05_weave_evolve_flash_kmeans_assign_6e1e_v1'
+SEED_ID = 'd112-shared-point-dual-issuer-tcgen05-weave-evolve-flash-kmeans-assign-6e1e-v1'
+TARGET_SHAPE = 'physical_D112_padded_14'
+CAPABILITY_SHAPE = 'post_d895_d112_b4_n8192_k1024_d112'
+PHYSICAL_DAG = 'one_N128_D112_point_producer->seven_persistent_D16_slices->two_independent_K64_tcgen05_issuers->two_disjoint_TMEM_argmax_consumers->local_packed_key_merge->caller_cluster_ids'
+flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 35840, "constants": [], "cta_group": 1, "threads": 416}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 35840, "constants": [], "cta_group": 1, "threads": 416}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as include_dirs
+    return include_dirs()
+
+def _require_tcgen05_arch() -> str:
+    from .._dispatch_runtime import detect_gpu_arch
+    arch = detect_gpu_arch()
+    if arch not in TCGEN05_ARCHES:
+        supported = ', '.join(sorted(TCGEN05_ARCHES))
+        raise RuntimeError(''.join([format(ROUTE_ID, ''), ' requires tcgen05/TMEM (', format(supported, ''), '); detected ', format(arch, '')]))
+    return arch
+
+def _compiled() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0355"}, "kernel_flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1", 35840, 416]}'))
+
+def supports_shape(*, D: int, N: int, K: int) -> bool:
+    return D == FEAT_D and N % BLOCK_N == 0 and (K % (BLOCK_K * OWNER_SLOTS) == 0)
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    from .._dispatch_runtime import create_tensor_map_3d_32b
+    bsz, n_points, n_clusters = (int(inputs[key]) for key in ('B', 'N', 'K'))
+    return (create_tensor_map_3d_32b(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, FEAT_D, FEAT_CHUNK), create_tensor_map_3d_32b(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, FEAT_D, FEAT_CHUNK))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    import torch
+    from .._dispatch_runtime import CUDAKernel
+    _require_tcgen05_arch()
+    B, N, D, K = (int(inputs[key]) for key in ('B', 'N', 'D', 'K'))
+    if not supports_shape(D=D, N=N, K=K):
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires D=112, N%128=0, and K%128=0']))
+    x_tmap, c_tmap = _make_tmaps(inputs)
+    cubin, name, smem, threads = _compiled()
+    grid = (B * (N // BLOCK_N), 1, 1)
+    with CUDAKernel(cubin, name) as kernel:
+        kernel.launch(grid=grid, block=(threads, 1, 1), args=[x_tmap, c_tmap, inputs['c_sq'], inputs['out'], B, N, D, K, N // BLOCK_N, K // BLOCK_K], shared_mem=smem, stream=torch.cuda.current_stream())
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': {'shape_key': TARGET_SHAPE, 'capability_shape': CAPABILITY_SHAPE, 'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'primitive': 'native_D112_TMA+tcgen05_mma+TMEM', 'physical_dag': PHYSICAL_DAG, 'point_producer': 'warp0 loads seven persistent D16 slices once per N128 tile', 'centroid_ownership': 'slot0 owns even K64 tiles; slot1 owns odd K64 tiles', 'issuer_policy': 'two independent warp issuers with no shared completion barrier', 'issuer_ownership': [{'slot': 0, 'issuer_warp': 3, 'operand_ready': ['x_ready0', 'c_full0'], 'score_complete': 'score_full0', 'readback_complete': 'score_empty0', 'recycle': ['c_empty0', 'x_empty0']}, {'slot': 1, 'issuer_warp': 12, 'operand_ready': ['x_ready1', 'c_full1'], 'score_complete': 'score_full1', 'readback_complete': 'score_empty1', 'recycle': ['c_empty1', 'x_empty1']}], 'score_slots': [{'tmem_cols': [0, 64], 'issuer_warp': 3, 'compute_warps': [4, 5, 6, 7]}, {'tmem_cols': [64, 128], 'issuer_warp': 12, 'compute_warps': [8, 9, 10, 11]}], 'producer_to_consumer': 'shared_seven_D16_point_slices_to_two_independent_K64_tcgen05_issuers_to_disjoint_TMEM_argmax_consumers_to_local_ordered_key_merge_to_cluster_ids', 'output_ownership': 'caller_owned_inputs[out]', 'production_launches': [''.join(['kernel_', format(ir.symbol, '')])], 'fallback_contract_regions': [], 'residual_contract_regions': [], 'global_workspace': False, 'materialized_d128_adapter': False, 'launch_grid': grid}}
+
+def benchmark_shared_point_dual_issuer_tcgen05_6e1e(*, shape_label: str=CAPABILITY_SHAPE, benchmark: bool=True) -> dict[str, Any]:
+    """Registered one-row capability launcher for regression and sanitizer tools."""
+    from .. import _dispatch_runtime as padded
+    shape = next((row for row in padded.padded_bucket_shapes('d112_gap_pad_14') if row['label'] == shape_label))
+    report = padded.evaluate(launch_for_eval, shapes=[shape], correctness=True, benchmark=benchmark, flashlib_baseline=False, benchmark_warmup_ms=20.0, benchmark_ms=100.0)
+    row = report['per_shape'][shape_label]
+    exact = bool(report['correctness']['all_correct']) and row.get('cluster_id_exact_match') is True
+    result: dict[str, Any] = {'passed': exact, 'all_pass': exact, 'shape_label': shape_label, 'selected_route': row.get('selected_route'), 'cluster_id_exact_match': row.get('cluster_id_exact_match'), 'measurement_comparable': bool(row.get('measurement_comparable')) if benchmark else False}
+    if benchmark:
+        result.update({'tflops': float(row['tflops']), 'kernel_ms': float(row['kernel_ms']), 'timing_backend': row.get('timing_backend'), 'timing_backend_requested': row.get('timing_backend_requested'), 'timing_backend_fallback_reason': row.get('timing_backend_fallback_reason'), 'performance_comparable': bool(row.get('measurement_comparable')), 'measured_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval'])})
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d128_splitk_priority_575c_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d128_splitk_priority_575c_v1.py
new file mode 100644
index 00000000..bae39528
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d128_splitk_priority_575c_v1.py
@@ -0,0 +1,37 @@
+"""Exact-D128 no-padding Split-K Flash-KMeans priority seed.
+
+Minimum architecture: sm_100a.  This D=128-only seed reuses the validated
+BLOCK_N=64 G1/R4 tcgen05/TMEM producer and four-lane reducer, but exposes every
+256-centroid tile as a Split-K work item for the five priority K=4096/8192
+rows.  It must not be used on sm_120a/sm_121a, where ptxas rejects tcgen05.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1 as _g1r4
+ROUTE_ID = 'd128_splitk_priority_575c_v1'
+SEED_ID = 'd128-no-padding-splitk-priority-575c-v1'
+TARGET_D = 128
+MIN_K_TILES = 16
+_g1r4.SUPPORTED_DIMS.add(TARGET_D)
+
+def _use_d128_priority_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    return dim == TARGET_D and num_n_tiles <= _g1r4.MAX_POINT_TILES and (k_tiles >= MIN_K_TILES)
+_g1r4._use_blockn64_splitk = _use_d128_priority_splitk
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Launch only the exact D128, no-padding priority Split-K schedule."""
+    if int(inputs['B']) != 1:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires B=1']))
+    if int(inputs['D']) != TARGET_D:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires D=', format(TARGET_D, ''), ', got ', format(inputs['D'], '')]))
+    if int(inputs['N']) not in (512, 1024, 2048):
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires N in {512, 1024, 2048}']))
+    if int(inputs['K']) not in (4096, 8192):
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires K in {4096, 8192}']))
+    outputs = _g1r4.launch_for_eval(inputs)
+    trace = dict(outputs.get('route_trace', {}))
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d128_splitk_priority_575c_v1:launch_for_eval', 'selected_seed': SEED_ID, 'guard_id': 'guard_d128_no_padding_splitk_priority_575c_v1', 'guard_condition': 'B == 1 and D == 128 and N in [512,1024,2048] and K in [4096,8192]', 'reason': 'exact-D128 priority Split-K: one 256-K tile per G1 producer work item plus four-lane reducer'})
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1.py
new file mode 100644
index 00000000..00524c33
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1.py
@@ -0,0 +1,141 @@
+"""Flash-KMeans Euclidean assignment D144/D160/D176 pad-to-D192 seed.
+
+Minimum architecture: sm_100a. This candidate zero-pads non-128D BF16 inputs
+with a Weave pack kernel, then routes assignment to the existing D192
+tcgen05/TMEM split-D seed. It is not intended for sm_120a/sm_121a where ptxas
+rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1 as _d192
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = _d192.BLOCK_N
+BLOCK_K = _d192.BLOCK_K
+FEAT_D_PAD = 192
+FEAT_D_PAD_VECS = FEAT_D_PAD // 8
+SUPPORTED_D = {144, 160, 176}
+PACK_THREADS = 256
+PACK_GRID_CAP = 4096
+_SCRATCH_CACHE: dict[tuple[int, ...], tuple[Any, Any]] = {}
+_ROUTE_INPUT_CACHE: dict[tuple[int, ...], dict[str, Any]] = {}
+flash_kmeans_assign_d160_pad192_pack_f9b2_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d160_pad192_pack_f9b2_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d160_pad192_pack_f9b2_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+pack_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d160_pad192_pack_f9b2_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _compiled_pack_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0352"}, "kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1", 0, 256]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    x_pad, c_pad = _scratch_buffers(inputs)
+    _launch_pack(inputs, x_pad, c_pad)
+    d192_inputs = _route_inputs(inputs, x_pad, c_pad)
+    outputs = _d192.launch_for_eval(d192_inputs)
+    normalized = _normalize_outputs(outputs, inputs)
+    route_kind = _route_kind(n_points=n_points, n_clusters=n_clusters)
+    selected_route = ''.join(['d', format(dim, ''), '_pad192_', format(route_kind, ''), '_repeated_mma_f9b2_v1'])
+    normalized['selected_route'] = selected_route
+    normalized['route_trace'] = {'shape_key': _shape_key(inputs), 'selected_route': selected_route, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': ''.join(['d', format(dim, ''), '-pad192-', format(route_kind, ''), '-repeated-mma-f9b2-v1']), 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': ''.join(['guard_d', format(dim, ''), '_pad192_tail_repair_f9b2_v1']), 'guard_condition': ''.join(['dtype == bfloat16 and D == ', format(dim, ''), ' and N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']), 'classification': 'seed-probe', 'dispatcher_kernel_ms': None, 'residual_contract_regions': ['zero_pad_to_d192_pack'], 'reason': 'D144/D160/D176 tail-safe route pads to D192 before the tcgen05 score producer'}
+    return normalized
+
+def _scratch_buffers(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    import torch
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), bsz, n_points, n_clusters, dim, FEAT_D_PAD)
+    cached = _SCRATCH_CACHE.get(key)
+    if cached is not None:
+        return cached
+    x_pad = torch.empty((bsz, n_points, FEAT_D_PAD), dtype=inputs['x'].dtype, device=inputs['x'].device)
+    c_pad = torch.empty((bsz, n_clusters, FEAT_D_PAD), dtype=inputs['centroids'].dtype, device=inputs['centroids'].device)
+    _SCRATCH_CACHE[key] = (x_pad, c_pad)
+    return (x_pad, c_pad)
+
+def _launch_pack(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    total_x_pad = bsz * n_points * FEAT_D_PAD
+    total_c_pad = bsz * n_clusters * FEAT_D_PAD
+    work_items = max(total_x_pad, total_c_pad)
+    grid_x = min((work_items + PACK_THREADS - 1) // PACK_THREADS, PACK_GRID_CAP)
+    cubin, kernel_name, smem_bytes, threads = _compiled_pack_kernel()
+    args = [inputs['x'], inputs['centroids'], x_pad, c_pad, bsz, n_points, dim, n_clusters, total_x_pad, total_c_pad]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(grid_x, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _route_inputs(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> dict[str, Any]:
+    key = stream_cache_key(inputs, int(x_pad.data_ptr()), int(c_pad.data_ptr()), int(inputs['x_sq'].data_ptr()), int(inputs['c_sq'].data_ptr()), int(inputs['out'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_PAD)
+    cached = _ROUTE_INPUT_CACHE.get(key)
+    if cached is not None:
+        return cached
+    route_inputs = {'label': inputs.get('label'), 'B': int(inputs['B']), 'N': int(inputs['N']), 'D': FEAT_D_PAD, 'K': int(inputs['K']), 'dtype': inputs.get('dtype', 'bfloat16'), 'x': x_pad, 'centroids': c_pad, 'x_sq': inputs['x_sq'], 'c_sq': inputs['c_sq'], 'out': inputs['out'], 'original_D': int(inputs['D'])}
+    _ROUTE_INPUT_CACHE[key] = route_inputs
+    return route_inputs
+
+def _route_kind(*, n_points: int, n_clusters: int) -> str:
+    if _d192._use_single_tile_path(n_points=n_points, n_clusters=n_clusters):
+        return 'single'
+    return 'paired'
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign D160 pad192 route must return cluster_ids or write inputs['out']")
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def compile_and_launch_flash_kmeans_assign_pad192(B: int=1, N: int=2048, K: int=2048, D: int=160, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(16005)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 16005}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4.py
new file mode 100644
index 00000000..ef018cd6
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4.py
@@ -0,0 +1,96 @@
+"""Flash-KMeans exact-D224 high-K ownership-repair candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for an exact D=224 score producer by accumulating seven D=32
+chunks into the same TMEM score tile before the argmin role consumes it. Its
+64B-swizzled TMA maps match the physical 32-element feature chunks; no host
+padding or packing is used on the eval path. It is not
+intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 64
+BLOCK_K = 256
+CHUNK_D = 32
+FEAT_D = 224
+D_CHUNKS = FEAT_D // CHUNK_D
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+ROW16_LOAD_COUNT = 64
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * CHUNK_D * 2
+C_TILE_BYTES = BLOCK_K * CHUNK_D * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d_64b
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d_64b(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, CHUNK_D)
+    tmap_c = create_tensor_map_3d_64b(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, CHUNK_D)
+    inputs['_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0351"}, "kernel_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4", 22528, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4 requires exact D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out'], 'selected_route': 'd224_tmem_abi_repair_d17c_v4', 'route_trace': {'selected_route': 'd224_tmem_abi_repair_d17c_v4', 'selected_seed': 'flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4', 'route_kind': 'shape_specific_seed', 'guard_condition': 'dtype == bfloat16 and D == 224 and N % 64 == 0 and K % 256 == 0'}}
+
+def compile_and_launch_flash_kmeans_assign_splitd_d224(B: int=1, N: int=1024, K: int=512, D: int=224, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(22401)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 22401}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_exactd_a532_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_exactd_a532_v1.py
new file mode 100644
index 00000000..b1eba09b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_exactd_a532_v1.py
@@ -0,0 +1,95 @@
+"""Flash-KMeans Euclidean assignment exact-D288 split-D candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for an exact D=288 score producer by accumulating nine D=32
+chunks into the same TMEM score tile before the argmin role consumes it. Its
+64B-swizzled TMA maps match the physical 32-element feature chunks; no host
+padding or packing is used on the eval path. It is not
+intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+CHUNK_D = 32
+FEAT_D = 288
+D_CHUNKS = FEAT_D // CHUNK_D
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * CHUNK_D * 2
+C_TILE_BYTES = BLOCK_K * CHUNK_D * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_d288_exactd_a532_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_exactd_a532_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_d288_exactd_a532_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d_64b
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d_64b(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, CHUNK_D)
+    tmap_c = create_tensor_map_3d_64b(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, CHUNK_D)
+    inputs['_flash_kmeans_assign_d288_exactd_a532_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0350"}, "kernel_flash_kmeans_assign_d288_exactd_a532_v1", 26624, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_exactd_a532_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != FEAT_D:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_exactd_a532_v1 requires exact D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out'], 'selected_route': 'd288_exactd_a532_v1', 'route_trace': {'selected_route': 'd288_exactd_a532_v1', 'selected_seed': 'flash_kmeans_assign_d288_exactd_a532_v1', 'route_kind': 'shape_specific_seed', 'guard_condition': 'dtype == bfloat16 and D == 288 and N % 128 == 0 and K % 256 == 0'}}
+
+def compile_and_launch_flash_kmeans_assign_splitd_d288(B: int=1, N: int=1024, K: int=512, D: int=256, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(25601)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 25601}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1.py
new file mode 100644
index 00000000..0544a606
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1.py
@@ -0,0 +1,88 @@
+"""Flash-KMeans Euclidean assignment D288 parent/Split-K hybrid seed.
+
+Minimum architecture: sm_100a. This production-dispatchable seed composes the
+validated exact-D288 tcgen05/TMEM parent for ``K <= 2048`` with the validated
+CTA-per-(N tile, K tile) Split-K producer plus its in-timed reduction for
+``K >= 4096``. It is not intended for sm_120a/sm_121a where ptxas rejects
+tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d288_exactd_a532_v1 as _parent
+from . import flash_kmeans_assign_d288_splitk_cta_0438_v1 as _splitk
+BLOCK_N = _parent.BLOCK_N
+BLOCK_K = _parent.BLOCK_K
+SUPPORTED_D = {288}
+BF16_DTYPE_NAMES = _splitk.BF16_DTYPE_NAMES
+ROUTE_ID = 'd288_parent_splitk_hybrid_20260629_v1'
+SEED_ID = 'd288-parent-splitk-hybrid-20260629-v1'
+PARENT_CHILD_ROUTE_ID = 'd288_exactd_a532_v1'
+SPLITK_CHILD_ROUTE_ID = _splitk.ROUTE_ID
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_exactd_a532_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz, n_points, dim, n_clusters, dtype_name = _shape_fields(inputs)
+    _validate_supported_shape(N=n_points, D=dim, K=n_clusters, dtype=dtype_name)
+    if n_clusters <= 2048:
+        child_outputs = _parent.launch_for_eval(inputs)
+        child_route = PARENT_CHILD_ROUTE_ID
+        child_seed = _parent.__name__.rsplit('.', maxsplit=1)[-1]
+        selected_path = 'parent'
+    elif n_clusters >= 4096:
+        child_outputs = _splitk.launch_for_eval(inputs)
+        child_route = SPLITK_CHILD_ROUTE_ID
+        child_seed = _splitk.SEED_ID
+        selected_path = 'splitk'
+    else:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1 supports K <= 2048 through the parent or K >= 4096 through Split-K, got K=', format(n_clusters, '')]))
+    normalized = _normalize_outputs(child_outputs, inputs)
+    normalized['selected_route'] = ROUTE_ID
+    normalized['route_trace'] = _route_trace(inputs, child_route=child_route, child_seed=child_seed, selected_path=selected_path, total_tiles=bsz * (n_points // BLOCK_N))
+    return normalized
+
+def _validate_supported_shape(*, N: int, D: int, K: int, dtype: Any) -> None:
+    dtype_name = str(dtype).replace('torch.', '')
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if D not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1 requires D == 288, got ', format(D, '')]))
+    if N % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(N, '')]))
+    if K % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(K, '')]))
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("D288 parent/Split-K hybrid route must return cluster_ids or write inputs['out']")
+
+def _route_trace(inputs: dict[str, Any], *, child_route: str, child_seed: str, selected_path: str, total_tiles: int) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_d288_parent_splitk_hybrid_20260629_v1', 'guard_condition': 'dtype == bfloat16 and D == 288 and N % 128 == 0 and K % 256 == 0; parent child when K <= 2048, Split-K child with in-timed reduction when K >= 4096', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'child_route': child_route, 'child_seed': child_seed, 'selected_path': selected_path, 'total_tiles': total_tiles, 'reason': 'K-guarded D288 composition of exact-D parent and real CTA Split-K reduction paths'}
+
+def _shape_fields(inputs: dict[str, Any]) -> tuple[int, int, int, int, str]:
+    return (int(inputs['B']), int(inputs['N']), int(inputs['D']), int(inputs['K']), _dtype_name(inputs))
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_splitk_cta_0438_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_splitk_cta_0438_v1.py
new file mode 100644
index 00000000..a884fcf2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d288_splitk_cta_0438_v1.py
@@ -0,0 +1,154 @@
+"""Flash-KMeans Euclidean assignment D288 split-K candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for exact D=288. High-K rows split the cluster
+tile loop across CTAs, write one partial argmin per K tile, then reduce those
+partials with a second Weave kernel. Non-splitK rows reuse the validated D288
+parent. It is not intended for sm_120a/sm_121a where ptxas rejects
+tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_d288_exactd_a532_v1 as _direct
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = _direct.BLOCK_N
+BLOCK_K = _direct.BLOCK_K
+CHUNK_D = _direct.CHUNK_D
+D_CHUNKS = _direct.D_CHUNKS
+SCORE_CHUNK_K = _direct.SCORE_CHUNK_K
+CSQ_VEC = _direct.CSQ_VEC
+CSQ_STAGE_VEC = _direct.CSQ_STAGE_VEC
+NUM_COMPUTE_WARPS = _direct.NUM_COMPUTE_WARPS
+X_TILE_BYTES = _direct.X_TILE_BYTES
+C_TILE_BYTES = _direct.C_TILE_BYTES
+CSQ_TILE_BYTES = _direct.CSQ_TILE_BYTES
+SUPPORTED_DIMS = {288}
+BF16_DTYPE_NAMES = {'bfloat16', 'torch.bfloat16'}
+SPLITK_GRID_CAP = 4096
+REDUCE_THREADS = 128
+SPLITK_MIN_K_TILES = 8
+ROUTE_ID = 'd288_splitk_cta_0438_v1'
+SEED_ID = 'd288-splitk-cta-0438-v1'
+flash_kmeans_assign_d288_splitk_cta_0438_v1_partial = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_splitk_cta_0438_v1_partial", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_splitk_cta_0438_v1_partial", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get('LOOM_FLASH_KMEANS_D288_SPLITK_CTA_0438_V1_VERIFY_KERNEL') == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d288_splitk_cta_0438_v1_partial", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    return _direct._cuda_include_dirs()
+
+def _compiled_partial_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0348"}, "kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial", 26624, 192]}'))
+
+def _compiled_reduce_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0349"}, "kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce", 0, 128]}'))
+
+def _compile_ir(ir_obj: Any) -> tuple[bytes, str, int, int]:
+    from .._dispatch_runtime import generate_kernel
+    from .._dispatch_runtime import compile_cuda
+    smem_bytes = ir_obj.computed_smem_bytes
+    source = generate_kernel(ir_obj, validate=False, smem_bytes=smem_bytes)
+    cubin = compile_cuda(source, options=['--use_fast_math'], include_dirs=_cuda_include_dirs())
+    return (cubin, ''.join(['kernel_', format(ir_obj.symbol, '')]), int(smem_bytes), int(ir_obj.threads))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    if not _use_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _direct.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = 'd288_exactd_a532_v1'
+        outputs['route_trace'] = trace
+        return outputs
+    _launch_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles)
+    total_work = bsz * num_n_tiles * k_tiles
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1))
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_splitk_cta_0438_v1 requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join(['flash_kmeans_assign_d288_splitk_cta_0438_v1 supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _use_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > 16:
+        return False
+    return k_tiles >= SPLITK_MIN_K_TILES
+
+def _launch_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    total_work = bsz * num_n_tiles * k_tiles
+    partial_scores, partial_indices = _partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _direct._make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_partial_kernel()
+    partial_args = pack_kernel_args(flash_kmeans_assign_d288_splitk_cta_0438_v1_partial, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes)
+    cubin, kernel_name, smem_bytes, threads = _compiled_reduce_kernel()
+    reduce_args = pack_kernel_args(reduce_ir, partial_scores=partial_scores, partial_indices=partial_indices, out=inputs['out'], B=bsz, N=n_points, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes)
+
+def _partial_buffers(inputs: dict[str, Any], total_work: int) -> tuple[Any, Any]:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work))
+    cache = inputs.setdefault('_flash_kmeans_assign_d288_splitk_cta_0438_v1_partials', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    scores = torch.empty((total_work, BLOCK_N), dtype=torch.float32, device=inputs['x'].device)
+    indices = torch.empty((total_work, BLOCK_N), dtype=torch.int32, device=inputs['x'].device)
+    cache[cache_key] = (scores, indices)
+    return (scores, indices)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d288_splitk_cta_0438_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_d288_splitk_cta_0438_v1', 'guard_condition': 'dtype == bfloat16 and D == 288 and N % 128 == 0 and K % 256 == 0 and num_n_tiles <= 16 and K_tiles >= 8', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'reason': 'D288 split-K seed exposes K tiles as CTA work then reduces partial argmins'}
+
+def compile_and_launch_flash_kmeans_assign_d288_splitk_cta_0438_v1(B: int=1, N: int=512, K: int=8192, D: int=288, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51204)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51204}}])
+    return result
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    return ''.join(['B=', format(int(inputs['B']), ''), ',N=', format(int(inputs['N']), ''), ',K=', format(int(inputs['K']), ''), ',D=', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    return str(inputs.get('dtype', inputs['x'].dtype)).replace('torch.', '')
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d352_exactd_splitk_c95c_v2.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d352_exactd_splitk_c95c_v2.py
new file mode 100644
index 00000000..570da43f
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d352_exactd_splitk_c95c_v2.py
@@ -0,0 +1,34 @@
+"""Exact-D352 Split-K Flash-KMeans staging seed.
+
+Minimum architecture: sm_100a.  This D352-only seed reuses the validated
+tcgen05/TMEM D32/K256 producer-reducer ABI with D=352 (eleven D32 chunks),
+avoiding the incumbent D352-to-D384 packing kernels.  It is unsupported on
+sm_120a/sm_121a because those targets reject tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1 as _abi
+from . import flash_kmeans_assign_gap_pad_v1 as _gap
+BLOCK_N = _abi.BLOCK_N
+MMA_BLOCK_K = _abi.MMA_BLOCK_K
+FEAT_D = 352
+MAX_POINT_TILES = _abi.MAX_POINT_TILES
+ROUTE_ID = 'd352_exactd_splitk_c95c_v2'
+SEED_ID = 'd352-exactd-splitk-c95c-v2'
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_partial_d32k256_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz, n, d, k = (int(inputs[x]) for x in ('B', 'N', 'D', 'K'))
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'} or d != FEAT_D or n % BLOCK_N or k % MMA_BLOCK_K:
+        raise ValueError('D352 exact seed requires BF16 D=352, N%64=0, and K%256=0')
+    ntiles, ktiles = (n // BLOCK_N, k // MMA_BLOCK_K)
+    if ntiles > MAX_POINT_TILES or ktiles < 4:
+        return _gap.launch_for_eval(inputs)
+    _abi._launch_blockn64_splitk(inputs, bsz=bsz, n_points=n, dim=d, n_clusters=k, num_n_tiles=ntiles, k_tiles=ktiles, k_slices=ktiles)
+    total_work = bsz * ntiles * ktiles
+    trace = _abi._route_trace(inputs, total_work=total_work, grid=(min(total_work, _abi.SPLITK_GRID_CAP), 1, 1), k_slices=ktiles)
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'guard_id': 'guard_d352_exactd_splitk_c95c_v2', 'guard_condition': 'D == 352 and N/64 <= 32 and K/256 >= 4', 'reason': 'exact D352 D32-chunk producer removes D384 packing'})
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2.py
new file mode 100644
index 00000000..3e0b11c8
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2.py
@@ -0,0 +1,95 @@
+"""Flash-KMeans Euclidean assignment exact-D416 split-D candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for an exact D=416 score producer by accumulating thirteen D=32
+chunks into the same TMEM score tile before the argmin role consumes it. Its
+64B-swizzled TMA maps match the physical 32-element feature chunks; no host
+padding or packing is used on the eval path. It is not
+intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+CHUNK_D = 32
+FEAT_D = 416
+D_CHUNKS = FEAT_D // CHUNK_D
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * CHUNK_D * 2
+C_TILE_BYTES = BLOCK_K * CHUNK_D * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d_64b
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d_64b(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, CHUNK_D)
+    tmap_c = create_tensor_map_3d_64b(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, CHUNK_D)
+    inputs['_flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0347"}, "kernel_flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2", 26624, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim % CHUNK_D:
+        raise ValueError(''.join(['D must be divisible by CHUNK_D=', format(CHUNK_D, ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out'], 'selected_route': 'd416_exactd_splitd_a4a579d1_v2', 'route_trace': {'selected_route': 'd416_exactd_splitd_a4a579d1_v2', 'selected_seed': 'flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2', 'route_kind': 'shape_specific_seed', 'guard_condition': 'dtype == bfloat16 and D == 416 and N % 128 == 0 and K % 256 == 0'}}
+
+def compile_and_launch_flash_kmeans_assign_splitd_d416(B: int=1, N: int=1024, K: int=512, D: int=416, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(41601)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'B': B, 'N': N, 'D': D, 'K': K, 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    passed = bool(torch.equal(out, ref))
+    result: dict[str, Any] = {'passed': passed}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 41601}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_exactd_splitd_d480_exact_seed_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_exactd_splitd_d480_exact_seed_v1.py
new file mode 100644
index 00000000..400aa5c8
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_exactd_splitd_d480_exact_seed_v1.py
@@ -0,0 +1,30 @@
+"""Flash-KMeans exact-D480 staged seed.
+
+Minimum architecture: sm_100a.  The contract-visible score producer is the
+32-wide tcgen05/TMEM split-D core and accumulates all fifteen D=32 chunks
+before the TMEM-to-register argmax writes ``cluster_ids``.  This is B200/B300
+only; sm_120a/sm_121a reject tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2 as _core
+BLOCK_N = _core.BLOCK_N
+BLOCK_K = _core.BLOCK_K
+CHUNK_D = _core.CHUNK_D
+FEAT_D = 480
+ROUTE_ID = 'd480_exactd_splitd_d480_exact_seed_v1'
+SEED_ID = 'd480-exactd-splitd-d480-exact-seed-v1'
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 26624, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    dim = int(inputs['D'])
+    if dim != FEAT_D:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires exact D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    if int(inputs['N']) % BLOCK_N:
+        raise ValueError(''.join(['N must be divisible by ', format(BLOCK_N, '')]))
+    if int(inputs['K']) % BLOCK_K:
+        raise ValueError(''.join(['K must be divisible by ', format(BLOCK_K, '')]))
+    outputs = _core.launch_for_eval(inputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': {'selected_route': ROUTE_ID, 'selected_seed': SEED_ID, 'route_kind': 'shape_specific_seed', 'guard_condition': 'dtype == bfloat16 and D == 480 and N % 128 == 0 and K % 256 == 0', 'producer': 'tcgen05_mma D=32 split-D -> TMEM -> register argmax -> cluster_ids'}}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_k1024_eac2_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_k1024_eac2_v1.py
new file mode 100644
index 00000000..a5508ad8
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_k1024_eac2_v1.py
@@ -0,0 +1,40 @@
+"""D480 K1024 Split-K activation experiment for Flash-KMeans assignment.
+
+Minimum architecture: sm_100a.  This D480-only staging seed reuses the
+validated tcgen05/TMEM D32x15 producer and Weave reducer, but exposes K=1024
+rows with at most 32 N=64 tiles to the producer/reducer ABI.  The parent keeps
+those rows on serial CTA ownership; this variant tests whether four K=256
+partials amortize the reducer without changing dispatcher policy.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1 as _parent
+BLOCK_N = _parent.BLOCK_N
+MMA_BLOCK_K = _parent.MMA_BLOCK_K
+FEAT_D = 480
+ROUTE_ID = 'd480_splitk_k1024_eac2_v1'
+SEED_ID = 'd480-splitk-k1024-eac2-v1'
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_partial_d32k256_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Run Split-K at K1024+ when the parent producer grid remains bounded."""
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _parent._validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    if not _use_k1024_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        return _parent.launch_for_eval(inputs)
+    k_slices = k_tiles // _parent.SPLITK_GROUP_K_TILES
+    _parent._launch_blockn64_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices)
+    total_work = bsz * num_n_tiles * k_slices
+    trace = _parent._route_trace(inputs, total_work=total_work, grid=(min(total_work, _parent.SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': SEED_ID, 'guard_id': 'guard_d480_splitk_k1024_eac2_v1', 'guard_condition': 'dtype == bfloat16 and D == 480 and N % 64 == 0 and K % 256 == 0 and N/64 <= 32 and K/256 >= 4', 'reason': 'D480 K1024+ bounded-point-tile rows use the tcgen05 partial/reducer path'})
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_k1024_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    return dim == FEAT_D and num_n_tiles <= _parent.MAX_POINT_TILES and (k_tiles >= 4)
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1.py
new file mode 100644
index 00000000..ce8cc985
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1.py
@@ -0,0 +1,172 @@
+"""Flash-KMeans exact-D480 D32/K256 Split-K producer/reducer candidate.
+
+Minimum architecture: sm_100a.  This D480-only candidate preserves the
+tcgen05/TMEM producer and exposes each K=256 centroid tile as a coarse CTA
+partial; a second Weave reducer consumes the global partial-score/index ABI
+and writes contract-visible ``cluster_ids``.  D=480 is fifteen exact D32
+chunks, so no feature padding or fallback is used.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_d480_exactd_splitd_d480_exact_seed_v1 as _direct
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = 64
+MMA_BLOCK_K = _base.BLOCK_K
+FEAT_CHUNK = 32
+ROW16_LOAD_COUNT = 64
+ROW16_LOGICAL_CHUNK_K = 128
+CSQ_STAGE_VEC = _base.CSQ_STAGE_VEC
+X_TILE_BYTES = BLOCK_N * FEAT_CHUNK * 2
+C_TILE_BYTES = MMA_BLOCK_K * FEAT_CHUNK * 2
+CSQ_TILE_BYTES = MMA_BLOCK_K * 4
+SUPPORTED_DIMS = {480}
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+SPLITK_GRID_CAP = _base.SPLITK_GRID_CAP
+SPLITK_MIN_K_TILES = _base.SPLITK_MIN_K_TILES
+SPLITK_GROUP_K_TILES = 1
+SPLITK_TILE_K = MMA_BLOCK_K * SPLITK_GROUP_K_TILES
+MAX_POINT_TILES = 32
+NUM_COMPUTE_WARPS = 4
+REDUCE_LANES_PER_ROW = 4
+REDUCE_THREADS = BLOCK_N * REDUCE_LANES_PER_ROW
+ROUTE_ID = 'd480_splitk_producer_reducer_d32k256_v1'
+SEED_ID = 'd480-splitk-producer-reducer-d32k256-v1'
+VERIFY_ENV = 'LOOM_FLASH_KMEANS_D480_SPLITK_PRODUCER_REDUCER_D32K256_VERIFY_KERNEL'
+flash_kmeans_assign_d480_splitk_partial_d32k256_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_partial_d32k256_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_d480_splitk_reduce_d32k256_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_reduce_d32k256_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_partial_d32k256_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_reduce_d32k256_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get(VERIFY_ENV) == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d480_splitk_partial_d32k256_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 22528, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _compiled_partial_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0345"}, "kernel_flash_kmeans_assign_d480_splitk_partial_d32k256_v1", 22528, 192]}'))
+
+def _compiled_reduce_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0346"}, "kernel_flash_kmeans_assign_d480_splitk_reduce_d32k256_v1", 0, 256]}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _compiled_partial_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _compiled_reduce_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    if not _use_blockn64_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _direct.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = _base.ROUTE_ID
+        trace['fallback_from'] = ROUTE_ID
+        trace['fallback_reason'] = 'shape does not satisfy BLOCK_N=64 grouped Split-K constraints'
+        outputs['route_trace'] = trace
+        return outputs
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    _launch_blockn64_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices)
+    total_work = bsz * num_n_tiles * k_slices
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _use_blockn64_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > MAX_POINT_TILES:
+        return False
+    if k_tiles % SPLITK_GROUP_K_TILES != 0:
+        return False
+    return k_tiles >= 32 or (k_tiles >= SPLITK_MIN_K_TILES and dim >= 448)
+
+def _launch_blockn64_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int) -> None:
+    import torch
+    from .._dispatch_runtime import pack_kernel_args
+    total_work = bsz * num_n_tiles * k_slices
+    partial_scores, partial_indices = _partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_kernel()
+    partial_args = pack_kernel_args(flash_kmeans_assign_d480_splitk_partial_d32k256_v1, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce_kernel()
+    reduce_args = pack_kernel_args(reduce_ir, partial_scores=partial_scores, partial_indices=partial_indices, out=inputs['out'], B=bsz, N=n_points, K=n_clusters, num_n_tiles=num_n_tiles, K_slices=k_slices)
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(BLOCK_N))
+    cached = inputs.get('_flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d_64b
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d_64b(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, FEAT_CHUNK)
+    tmap_c = create_tensor_map_3d_64b(inputs['centroids'].data_ptr(), bsz * n_clusters, MMA_BLOCK_K, dim, FEAT_CHUNK)
+    inputs['_flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _partial_buffers(inputs: dict[str, Any], total_work: int) -> tuple[Any, Any]:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work), int(BLOCK_N), int(SPLITK_GROUP_K_TILES))
+    cache = inputs.setdefault('_flash_kmeans_assign_d480_splitk_producer_reducer_d32k256_v1_partials', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    scores = torch.empty((total_work, BLOCK_N), dtype=torch.float32, device=inputs['x'].device)
+    indices = torch.empty((total_work, BLOCK_N), dtype=torch.int32, device=inputs['x'].device)
+    cache[cache_key] = (scores, indices)
+    return (scores, indices)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d480_splitk_producer_reducer_streamdep_r63_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_d480_splitk_producer_reducer_d32k256_v1', 'guard_condition': 'dtype == bfloat16 and D == 480 and N % 64 == 0 and K % 256 == 0 and num_n_tiles <= 32 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'cluster_grouping': 1, 'tmem_layout': 'ROW_16x256B', 'producer_to_reducer_sync': 'same_stream_ordering', 'cuda_module_cache': 'persistent_per_process', 'producer_work_feed': '2x_g2_for_same_N_K'}, 'reason': 'BLOCK_N=64 G1/R4 tile-search variant uses ROW_16x256B score drains, single-MMA producer slices, and four-lane Split-K reducer'}
+
+def compile_and_launch_flash_kmeans_assign_d480_splitk_producer_reducer(B: int=1, N: int=512, K: int=8192, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51204)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51204}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1.py
new file mode 100644
index 00000000..808dfc1a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1.py
@@ -0,0 +1,117 @@
+"""Flash-KMeans Euclidean assignment direct D64 seed.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for exact D=64 rows. It reuses the single 64-wide feature tile
+path from the micro-D seed but TMA-loads the original tensors directly instead
+of launching a BF16 pad/copy sidecar. It is not intended for sm_120a/sm_121a
+where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D_PAD = 64
+SUPPORTED_D = {64}
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D_PAD * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D_PAD * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+ROUTE_ID = 'd64_direct_single64_1p2gap_9f2a_v1'
+SEED_ID = 'd64-direct-single64-1p2gap-9f2a-v1'
+flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _create_direct_tensor_map_3d(data_ptr: int, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D_PAD, FEAT_D_PAD)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d(data_ptr, global_height, shared_height, FEAT_D_PAD, FEAT_D_PAD).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_PAD)
+    cached = inputs.get('_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_direct_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N)
+    tmap_c = _create_direct_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K)
+    inputs['_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0339"}, "kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1", 51200, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1 requires D=64, got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': _route_trace(inputs, grid=grid)}
+
+def compile_and_launch_flash_kmeans_assign_d64_direct(B: int=4, N: int=1024, K: int=512, D: int=64, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(6401)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 6401}}])
+    return result
+
+def _route_trace(inputs: dict[str, Any], *, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval', 'selected_seed': SEED_ID, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_d64_direct_single64_1p2gap_9f2a_v1', 'guard_condition': 'dtype == bfloat16 and D == 64 and N % 128 == 0 and K % 256 == 0', 'classification': 'seed-probe', 'dispatcher_kernel_ms': None, 'reason': 'direct D64 seed uses one 64-feature tcgen05 tile without BF16 pack/pad sidecar', 'launch_grid': grid}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1.py
new file mode 100644
index 00000000..a76bc69d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1.py
@@ -0,0 +1,41 @@
+"""Exact-D768 no-padding Split-K Flash-KMeans assignment seed.
+
+Minimum architecture: sm_100a.  This exact priority-route reuses the proven
+tcgen05/TMEM BLOCK_N=64 G1/R4 producer and four-lane Weave Split-K reducer,
+but extends its runtime feature-tile loop to D=768 (twelve 64-wide chunks).
+The producer writes per-slice argmax state to global partial buffers; the
+reducer consumes those buffers to produce contract-visible ``cluster_ids``.
+No D padding or non-Weave fallback is used.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1 as _g1
+TARGET_D = 768
+ROUTE_ID = 'd768_no_padding_splitk_priority_d768_exact_seed_v1'
+SEED_ID = 'd768-no-padding-splitk-priority-d768-exact-seed-v1'
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    if dim != TARGET_D:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires exact D=', format(TARGET_D, ''), ', got D=', format(dim, '')]))
+    dtype_name = _g1._base._dtype_name(inputs)
+    if dtype_name not in _g1.BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if n_points % _g1.BLOCK_N != 0 or n_clusters % _g1.MMA_BLOCK_K != 0:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires N divisible by ', format(_g1.BLOCK_N, ''), ' and K divisible by ', format(_g1.MMA_BLOCK_K, ''), '; got N=', format(n_points, ''), ', K=', format(n_clusters, '')]))
+    num_n_tiles = n_points // _g1.BLOCK_N
+    k_tiles = n_clusters // _g1.MMA_BLOCK_K
+    if num_n_tiles > _g1.MAX_POINT_TILES or k_tiles < _g1.SPLITK_MIN_K_TILES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires N/64 <= ', format(_g1.MAX_POINT_TILES, ''), ' and K/256 >= ', format(_g1.SPLITK_MIN_K_TILES, ''), '; got N=', format(n_points, ''), ', K=', format(n_clusters, '')]))
+    k_slices = k_tiles // _g1.SPLITK_GROUP_K_TILES
+    _g1._launch_blockn64_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices)
+    total_work = bsz * num_n_tiles * k_slices
+    trace = _g1._route_trace(inputs, total_work=total_work, grid=(min(total_work, _g1.SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1:launch_for_eval', 'selected_seed': SEED_ID, 'guard_id': 'guard_exact_d768_no_padding_splitk_priority_d768_exact_seed_v1', 'guard_condition': 'dtype == bfloat16 and D == 768 and N % 64 == 0 and K % 256 == 0', 'feature_tiles': TARGET_D // _g1.FEAT_CHUNK, 'reason': 'exact-D768 G1/R4 tcgen05 Split-K seed; twelve feature chunks with no D padding'})
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_dispatcher.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_dispatcher.py
new file mode 100644
index 00000000..f5342678
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_dispatcher.py
@@ -0,0 +1,548 @@
+"""Flash-KMeans Euclidean assignment guarded seed dispatcher.
+
+Minimum architecture: sm_100a. Every production route is Weave-only and uses
+existing tcgen05/TMEM seed kernels; no external runtime fallback is present.
+The tcgen05/TMEM routes are not intended for sm_120a/sm_121a where ptxas
+rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from collections.abc import Callable
+from dataclasses import dataclass
+from threading import RLock
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_b23d_v2 as _non128d_d160
+from . import flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1 as _non128d_v1
+from . import flash_kmeans_assign_cleanroom_tcgen05_v10 as _single
+from . import flash_kmeans_assign_cleanroom_tcgen05_v15 as _paired
+from . import flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1 as _d64_direct
+from . import flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1 as _d112_a262
+from . import flash_kmeans_assign_d128_splitk_priority_575c_v1 as _d128_priority
+from . import flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1 as _tail_pad192_f9b2
+from . import flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4 as _d224_d17c
+from . import flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1 as _d288_hybrid
+from . import flash_kmeans_assign_d352_exactd_splitk_c95c_v2 as _d352_exactd
+from . import flash_kmeans_assign_d480_splitk_k1024_eac2_v1 as _d480_eac2
+from . import flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1 as _d768_priority
+from . import flash_kmeans_assign_gap_pad_v1 as _gap_pad
+from . import flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1 as _highd_paired_gridcap160
+from . import flash_kmeans_assign_highd_splitd_6fcf_v1 as _highd
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _highd_splitk
+from . import flash_kmeans_assign_lowdim_e50c_v1 as _lowdim
+from . import flash_kmeans_assign_microdim_hybrid_9c0d_v1 as _microdim
+from . import flash_kmeans_assign_microdim_pipeline4_08f9_v4 as _microdim_pipeline4
+from . import flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1 as _highd_no_padding_r63
+from .flash_kmeans_assign_stream import bind_current_stream
+BLOCK_N = _single.BLOCK_N
+BLOCK_K = _single.BLOCK_K
+FEAT_D = _single.FEAT_D
+D144_D176_F9B2_DIMS = _decode_capture(_json_loads('{"__tuple__": [144, 176]}'))
+SUPPORTED_DIMS = _decode_capture(_json_loads('{"__tuple__": [16, 32, 64, 48, 112, 224, 288, 352, 416, 480, 80, 96, 128, 144, 176, 160, 192, 256, 320, 384, 448, 512, 768]}'))
+D64_SEED_ID = 'd64-direct-single64-1p2gap-9f2a-v1'
+D112_A262_SEED_ID = _d112_a262.SEED_ID
+MICRODIM_PAD64_SEED_ID = 'microdim-pad64-d64-direct-v1'
+MICRODIM_HYBRID_SEED_ID = _microdim.SEED_ID
+MICRODIM_PIPELINE4_SEED_ID = _microdim_pipeline4.SEED_ID
+LOWDIM_E50C_SEED_ID = 'lowdim-e50c-v1'
+SMALL_SEED_ID = 'small-grid-single-tile-v10'
+PAIRED_SEED_ID = 'paired-large-v15'
+D144_D160_D176_PAD192_F9B2_SEED_ID = 'd144-d160-d176-pad192-tail-repair-f9b2-v1'
+D160_PADDED_SEED_ID = 'd160-padded_single-repeated-mma-b23d-v2'
+D192_SINGLE_SEED_ID = 'd192-single-repeated-mma-v1'
+D192_PAIRED_SEED_ID = 'd192-paired-repeated-mma-v1'
+D256_SINGLE_SEED_ID = 'd256-single-repeated-mma-v1'
+D288_PARENT_SPLITK_HYBRID_SEED_ID = _d288_hybrid.SEED_ID
+HIGHD_SPLITD_SEED_ID = _highd.SEED_ID
+HIGHD_SPLITK_SEED_ID = _highd_splitk.SEED_ID
+HIGHD_PAIRED_PACKEDPARTIAL_SEED_ID = _highd_paired_gridcap160.SEED_ID
+HIGHD_NO_PADDING_PORTFOLIO_R63_SEED_ID = _highd_no_padding_r63.SEED_ID
+D768_PRIORITY_SEED_ID = _d768_priority.SEED_ID
+D480_EAC2_SEED_ID = _d480_eac2.SEED_ID
+GAP_PAD_SEED_ID = _gap_pad.SEED_ID
+D352_EXACTD_SEED_ID = _d352_exactd.SEED_ID
+D224_D17C_SEED_ID = 'flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4'
+D64_ROUTE_ID = 'd64_direct_single64_1p2gap_9f2a_v1'
+D112_A262_ROUTE_ID = _d112_a262.ROUTE_ID
+D112_A262_LIVE_REBASE_ARTIFACT = 'artifacts/generalize_auto_tuning/generalize-auto-tuning-flash-kmeans-assign-bf8f/dispatcher_consumption/live_incumbent_rebase.json'
+D112_A262_LIVE_REBASE_MEASUREMENT_SESSION_ID = 'd112-a262-live-rebase-3673c9957e9a4fba9b59c8b0a4ee076e'
+D112_A262_SELECTED_SHAPE_KEYS = frozenset({(2, 2048, 112, 512), (1, 512, 112, 8192), (1, 256, 112, 256), (2, 512, 112, 8192), (1, 384, 112, 4096), (3, 768, 112, 8192)})
+D112_A262_RETAINED_SHAPE_KEYS = frozenset(_d112_a262.SHAPE_KEYS) - D112_A262_SELECTED_SHAPE_KEYS
+if len(D112_A262_SELECTED_SHAPE_KEYS) != 6 or len(D112_A262_RETAINED_SHAPE_KEYS) != 8:
+    raise RuntimeError('D112 a262 additive ownership must preserve the measured 6/8 partition')
+MICRODIM_PAD64_ROUTE_ID = 'microdim_pad64_d64_direct_v1'
+MICRODIM_HYBRID_ROUTE_ID = _microdim.ROUTE_ID
+MICRODIM_PIPELINE4_ROUTE_ID = _microdim_pipeline4.ROUTE_ID
+LOWDIM_E50C_ROUTE_ID = 'lowdim_e50c_v1'
+GAP_PAD_ROUTE_ID = _gap_pad.ROUTE_ID
+D352_EXACTD_ROUTE_ID = _d352_exactd.ROUTE_ID
+D224_D17C_ROUTE_ID = 'd224_tmem_abi_repair_d17c_v4'
+SMALL_ROUTE_ID = 'small_grid_single_tile_v10'
+PAIRED_ROUTE_ID = 'paired_large_v15'
+D128_EVEN_NEAR_FLOOR_V10_ROUTE_ID = 'd128_even_near_floor_v10_repair'
+D128_PRIORITY_SPLITK_ROUTE_ID = _d128_priority.ROUTE_ID
+D144_D160_D176_PAD192_F9B2_ROUTE_ID = 'd144_d160_d176_pad192_tail_repair_f9b2_v1'
+D160_PADDED_ROUTE_ID = 'd160_padded_single_repeated_mma_v2'
+D192_SINGLE_ROUTE_ID = 'd192_single_repeated_mma_v1'
+D192_PAIRED_ROUTE_ID = 'd192_paired_repeated_mma_v1'
+D256_SINGLE_ROUTE_ID = 'd256_single_repeated_mma_v1'
+D288_PARENT_SPLITK_HYBRID_ROUTE_ID = _d288_hybrid.ROUTE_ID
+HIGHD_SPLITD_ROUTE_ID = _highd.ROUTE_ID
+HIGHD_SPLITK_ROUTE_ID = _highd_splitk.ROUTE_ID
+HIGHD_PAIRED_PACKEDPARTIAL_ROUTE_ID = _highd_paired_gridcap160.ROUTE_ID
+HIGHD_NO_PADDING_PORTFOLIO_R63_ROUTE_ID = _highd_no_padding_r63.ROUTE_ID
+D768_PRIORITY_ROUTE_ID = _d768_priority.ROUTE_ID
+D480_EAC2_ROUTE_ID = _d480_eac2.ROUTE_ID
+GENERIC_FALLBACK_ID = 'aligned_weave_v10_fallback'
+UNSUPPORTED_ROUTE_ID = 'unsupported_shape'
+SMALL_GRID_N_TILE_CAP = 8
+SMALL_GRID_K_TILE_CAP = 2
+SLOW_ROUTE_SPEEDUP_THRESHOLD = 0.98
+BF16_DTYPE_NAMES = {'bfloat16', 'bf16', 'torch.bfloat16'}
+D768_PRIORITY_SHAPES = frozenset({(1, 512, 4096), (1, 1024, 4096), (1, 512, 8192), (1, 1024, 8192), (1, 2048, 4096)})
+MICRODIM_PAD64_SHAPES = frozenset({(3, 2432, 512, 16), (4, 1024, 512, 16), (3, 2432, 512, 32), (4, 1024, 512, 32)})
+MICRODIM_PIPELINE4_SOURCE_SHAPES = frozenset({(8, 65536, 16, 512), (8, 65536, 32, 512)})
+MICRODIM_PIPELINE4_SELECTED_SHAPES = MICRODIM_PIPELINE4_SOURCE_SHAPES
+MICRODIM_PIPELINE4_LIVE_REBASE_ARTIFACT = 'artifacts/generalize_auto_tuning/generalize-auto-tuning-flash-kmeans-assign-a083/dispatcher_consumption/live_incumbent_rebase.json'
+MICRODIM_PIPELINE4_LIVE_REBASE_MEASUREMENT_SESSION_ID = 'a083-live-rebase-80f484e6feb84482873f1cf45ed292bd'
+if len(MICRODIM_PIPELINE4_SELECTED_SHAPES) != 2:
+    raise RuntimeError('08f9 additive ownership must preserve the measured two-row partition')
+D224_D17C_SHAPES = frozenset({(4, 1536, 256, 224)})
+PRIORITY_EXPECTED_SEEDS = {128: _d128_priority.SEED_ID}
+_PREPARE_LOCK = RLock()
+
+@dataclass(frozen=True)
+class RouteDecision:
+    route_id: str
+    entrypoint: str
+    selected_seed: str
+    route_kind: str
+    route_source: str
+    guard_id: str
+    guard_condition: str
+    reason: str
+
+    def trace_row(self, *, shape_key: str | None=None, expected_seed: str | None=None, dispatcher_kernel_ms: float | None=None, shape_specific_kernel_ms: float | None=None, relative_speedup_vs_baseline: float | None=None) -> dict[str, Any]:
+        return {'shape_key': shape_key, 'selected_route': self.route_id, 'selected_entrypoint': self.entrypoint, 'selected_seed': self.selected_seed, 'expected_seed': expected_seed, 'route_kind': self.route_kind, 'route_source': self.route_source, 'guard_id': self.guard_id, 'guard_condition': self.guard_condition, 'classification': _classify_route(self, expected_seed, relative_speedup_vs_baseline), 'dispatcher_kernel_ms': dispatcher_kernel_ms, 'shape_specific_kernel_ms': shape_specific_kernel_ms, 'relative_speedup_vs_baseline': relative_speedup_vs_baseline, 'reason': self.reason}
+
+@dataclass(frozen=True)
+class PreparedKMeansLaunchPlan:
+    """Exact KMeans route with fully marshalled launches and owned workspace."""
+    inputs: dict[str, Any]
+    decision: RouteDecision
+    arch: str
+    shape: tuple[int, int, int, int, str]
+    direct_launcher: Callable[..., Any]
+    launch_count: int
+    device_index: int
+    stream: Any
+    stream_handle: int
+    timeout_ms: float | None = None
+
+    @property
+    def selected_route(self) -> str:
+        return self.decision.route_id
+
+    @property
+    def launch_entrypoint(self) -> str:
+        return self.decision.entrypoint
+
+    def launch(self, *, stream: Any=None, timeout_ms: float | None=None, public_inputs_already_recorded: bool=False) -> dict[str, Any]:
+        """Submit the bound launch sequence without dispatch or allocation."""
+        import torch
+        if not isinstance(public_inputs_already_recorded, bool):
+            raise TypeError('public_inputs_already_recorded must be a bool')
+        with torch.cuda.device(self.device_index):
+            resolved_stream = self.stream if stream is None else stream
+            resolved_handle = int(resolved_stream.cuda_stream)
+            if resolved_handle != self.stream_handle:
+                raise RuntimeError(''.join(['prepared Flash-KMeans plan is stream-bound: prepared on stream 0x', format(self.stream_handle, ''.join(['x'])), ', requested 0x', format(resolved_handle, ''.join(['x'])), '; prepare a separate plan inside the target torch.cuda.stream(...) context']))
+            try:
+                result = self.direct_launcher(self.inputs, stream=None, timeout_ms=self.timeout_ms if timeout_ms is None else timeout_ms)
+            finally:
+                self.direct_launcher.record_stream(resolved_stream)
+                if not public_inputs_already_recorded:
+                    seen: set[int] = set()
+                    for value in self.inputs.values():
+                        identity = id(value)
+                        record_stream = getattr(value, 'record_stream', None)
+                        if identity not in seen and callable(record_stream):
+                            seen.add(identity)
+                            record_stream(resolved_stream)
+            return result
+
+    def _launch_stream_bound_recorded(self, *, timeout_ms: float | None=None) -> dict[str, Any]:
+        """Submit an internally proved fixed-stream slot without re-traversal.
+
+        Exported stateful runtimes may call this only after validating the
+        prepared stream, recording every current public tensor, and recording
+        the plan's route-private launch storage at slot publication.
+        """
+        return self.direct_launcher(self.inputs, stream=None, timeout_ms=self.timeout_ms if timeout_ms is None else timeout_ms)
+ROUTE_SMALL_V10 = RouteDecision(route_id=SMALL_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval', selected_seed=SMALL_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_small_grid_single_tile_v10', guard_condition='dtype == bfloat16 and D == 128 and N % 128 == 0 and K % 256 == 0 and num_n_tiles <= 8 and K_tiles <= 2', reason='small-grid anchor uses the v10 single point-tile seed')
+ROUTE_PAIRED_V15 = RouteDecision(route_id=PAIRED_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval', selected_seed=PAIRED_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_paired_large_v15', guard_condition='dtype == bfloat16 and D == 128 and N % 128 == 0 and K % 256 == 0 and num_n_tiles % 2 == 0 and not (num_n_tiles <= 8 and K_tiles <= 2)', reason='even point-tile grids use the v15 paired point-tile seed')
+ROUTE_ALIGNED_V10_FALLBACK = RouteDecision(route_id=GENERIC_FALLBACK_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval', selected_seed=SMALL_SEED_ID, route_kind='fallback', route_source='generic-weave-fallback', guard_id='guard_aligned_v10_weave_fallback', guard_condition='dtype == bfloat16 and D == 128 and N % 128 == 0 and K % 256 == 0 and num_n_tiles % 2 == 1 and not (num_n_tiles <= 8 and K_tiles <= 2)', reason='v15 paired kernel requires an even number of point tiles; v10 is the aligned Weave fallback')
+ROUTE_D128_EVEN_NEAR_FLOOR_V10_REPAIR = RouteDecision(route_id=D128_EVEN_NEAR_FLOOR_V10_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval', selected_seed=SMALL_SEED_ID, route_kind='specialized', route_source='generated-variant', guard_id='guard_d128_even_b8_n8192_k256_v10_repair', guard_condition='dtype == bfloat16 and B == 8 and D == 128 and N == 8192 and K == 256', reason='same-session post-D895 replay shows v10 beats paired v15 on the B8/N8192/K256 near-floor row')
+ROUTE_D128_PRIORITY_SPLITK = RouteDecision(route_id=D128_PRIORITY_SPLITK_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d128_splitk_priority_575c_v1:launch_for_eval', selected_seed=_d128_priority.SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d128_no_padding_splitk_priority_575c_v1', guard_condition='B == 1 and D == 128 and N in [512,1024,2048] and K in [4096,8192]', reason='exact five-row D128 priority bucket consumes the 64x256 G1/R4 Split-K seed')
+ROUTE_D64_DIRECT_9F2A = RouteDecision(route_id=D64_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval', selected_seed=D64_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d64_direct_single64_1p2gap_9f2a_v1', guard_condition='dtype == bfloat16 and D == 64 and N % 128 == 0 and K % 256 == 0', reason='D64 lowdim-tail bucket uses the 1d9f direct one-MMA tcgen05 score producer')
+ROUTE_D112_A262 = RouteDecision(route_id=D112_A262_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1:launch_for_eval', selected_seed=D112_A262_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_additive_d112_gap_pad_6_a262_bf8f_v1', guard_condition='dtype == bfloat16 and (B, N, D, K) is one of the six rows selected by the bf8f live-current-main CUPTI rebase', reason='the additive a262 portfolio owns only rows where its direct prepared GPU span cleared 0.98x of live current main; the other eight D112 rows retain the existing gap-pad route')
+ROUTE_MICRODIM_PAD64 = RouteDecision(route_id=MICRODIM_PAD64_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval', selected_seed=MICRODIM_PAD64_SEED_ID, route_kind='specialized', route_source='generated-variant', guard_id='guard_microdim_pad64_d64_direct_v1', guard_condition='dtype == bfloat16 and (B,N,K,D) is one of the four retained D16/D32 K512 low-shape rows', reason='two independent same-session B200 A/B runs retained only the B3/N2432 and B4/N1024 rows for zero-padding to the existing D64 direct seed')
+ROUTE_MICRODIM_HYBRID = RouteDecision(route_id=MICRODIM_HYBRID_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval', selected_seed=MICRODIM_HYBRID_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_microdim_hybrid_9c0d_v1', guard_condition='dtype == bfloat16 and D in [16, 32] and N % 128 == 0 and K % 256 == 0', reason="D16/D32 consume c92d's hybrid seed: short K=512 rows use direct staging and large/high-K rows keep 6cd2 pack+TMA")
+ROUTE_MICRODIM_PIPELINE4 = RouteDecision(route_id=MICRODIM_PIPELINE4_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_microdim_pipeline4_08f9_v4:launch_for_eval', selected_seed=MICRODIM_PIPELINE4_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_additive_microdim_pipeline4_08f9_v4_a083', guard_condition='dtype == bfloat16 and (B, N, D, K) is one of the two rows selected by the a083 live-incumbent CUPTI rebase', reason='the fresh a083 three-order CUPTI ownership screen selected both exact B8/N65536/K512 D16 and D32 rows over microdim_hybrid_9c0d_v1')
+ROUTE_D224_D17C = RouteDecision(route_id=D224_D17C_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4:launch_for_eval', selected_seed=D224_D17C_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d224_d17c_exact_b4_n1536_k256', guard_condition='dtype == bfloat16 and (B,N,K,D) == (4,1536,256,224)', reason='the exact D224 single-launch seed removes the measured two-launch gap on this one validated row')
+ROUTE_LOWDIM_E50C = RouteDecision(route_id=LOWDIM_E50C_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_lowdim_e50c_v1:launch_for_eval', selected_seed=LOWDIM_E50C_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_lowdim_e50c_v1_d80_d96', guard_condition='dtype == bfloat16 and D in [80, 96] and N % 128 == 0 and K % 256 == 0', reason='D80/D96 lowdim-tail bucket uses the e50c fused pad-to-128 tcgen05 route after fdac missed the same-session floor')
+ROUTE_GAP_PAD = RouteDecision(route_id=GAP_PAD_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_gap_pad_v1:launch_for_eval', selected_seed=GAP_PAD_SEED_ID, route_kind='specialized', route_source='generated-variant', guard_id='guard_gap_pad_to_supported_seed_v1', guard_condition='dtype == bfloat16 and D in [48, 112, 224, 352, 416, 480] and N % 128 == 0 and K % 256 == 0', reason='between-bucket D rows zero-pad to the next supported Weave seed bucket without changing the delegated seed schedule')
+ROUTE_D352_EXACTD = RouteDecision(route_id=D352_EXACTD_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d352_exactd_splitk_c95c_v2:launch_for_eval', selected_seed=D352_EXACTD_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d352_exactd_splitk_c95c_v2', guard_condition='dtype == bfloat16 and D == 352 and N/64 <= 32 and K/256 >= 4', reason='exact-D352 D32-chunk Split-K seed removes the D384 pack on its validated envelope')
+ROUTE_D480_EAC2 = RouteDecision(route_id=D480_EAC2_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d480_splitk_k1024_eac2_v1:launch_for_eval', selected_seed=D480_EAC2_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d480_splitk_k1024_eac2_v1', guard_condition='dtype == bfloat16 and D == 480 and N % 64 == 0 and K % 256 == 0 and N/64 <= 32 and K/256 >= 4', reason='D480 bounded point-tile K1024+ rows consume the validated tcgen05 producer/reducer seed; low-K and large-N rows retain the Weave gap-pad route')
+ROUTE_D288_PARENT_SPLITK_HYBRID = RouteDecision(route_id=D288_PARENT_SPLITK_HYBRID_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d288_parent_splitk_hybrid_20260629_v1:launch_for_eval', selected_seed=D288_PARENT_SPLITK_HYBRID_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d288_parent_splitk_hybrid_20260629_v1', guard_condition='dtype == bfloat16 and D == 288 and N % 128 == 0 and K % 256 == 0 and (K <= 2048 or K >= 4096)', reason='D288 consumes the measured exact-D parent/Split-K hybrid; the high-K branch includes its CTA Split-K reduction in the dispatcher-timed path')
+ROUTE_D144_D176_PAD192_F9B2 = RouteDecision(route_id=D144_D160_D176_PAD192_F9B2_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d160_pad192_tail_repair_f9b2_v1:launch_for_eval', selected_seed=D144_D160_D176_PAD192_F9B2_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d144_d176_pad192_tail_repair_f9b2_v1', guard_condition='dtype == bfloat16 and D in [144, 176] and N % 128 == 0 and K % 256 == 0', reason='D144/D176 consume the f9b2 tail-safe seed: pack D to D=192 scratch, then reuse the D192 tcgen05 path; D160 remains on the faster promoted b23d route')
+ROUTE_D160_PADDED = RouteDecision(route_id=D160_PADDED_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_b23d_v2:launch_for_eval', selected_seed=D160_PADDED_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d160_padded_single_repeated_mma_b23d_v2', guard_condition='dtype == bfloat16 and D == 160 and N % 128 == 0 and K % 256 == 0', reason='D160 consumes the 81d5 padded-tail wrapper: pack D=160 to D=192 scratch, then reuse the D192 tcgen05 path')
+ROUTE_D192_SINGLE = RouteDecision(route_id=D192_SINGLE_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1:launch_for_eval', selected_seed=D192_SINGLE_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d192_single_repeated_mma_v1', guard_condition='dtype == bfloat16 and D == 192 and N % 128 == 0 and K % 256 == 0 and (num_n_tiles % 2 != 0 or (num_n_tiles <= 8 and K_tiles <= 2))', reason='D192 small or odd point-tile grids use the b23d single repeated-MMA path')
+ROUTE_D192_PAIRED = RouteDecision(route_id=D192_PAIRED_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1:launch_for_eval', selected_seed=D192_PAIRED_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d192_paired_repeated_mma_v1', guard_condition='dtype == bfloat16 and D == 192 and N % 128 == 0 and K % 256 == 0 and num_n_tiles % 2 == 0 and not (num_n_tiles <= 8 and K_tiles <= 2)', reason='D192 even point-tile grids use the b23d paired repeated-MMA path')
+ROUTE_D256_SINGLE = RouteDecision(route_id=D256_SINGLE_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1:launch_for_eval', selected_seed=D256_SINGLE_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d256_single_repeated_mma_v1', guard_condition='dtype == bfloat16 and D == 256 and N % 128 == 0 and K % 256 == 0', reason='D256 consumes the existing b23d single repeated-MMA route; paired D256 remains a resource-repair lane')
+ROUTE_HIGHD_SPLITD = RouteDecision(route_id=HIGHD_SPLITD_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_highd_splitd_6fcf_v1:launch_for_eval', selected_seed=HIGHD_SPLITD_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_highd_splitd_6fcf_v1', guard_condition='dtype == bfloat16 and D in [320, 384, 448, 512] and N % 128 == 0 and K % 256 == 0 and not (num_n_tiles <= 16 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448)))', reason='high-D rows use the 6fcf split-D seed except where 8de8 split-K A/B showed wins')
+ROUTE_HIGHD_SPLITK = RouteDecision(route_id=HIGHD_SPLITK_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_highd_splitk_8de8_v1:launch_for_eval', selected_seed=HIGHD_SPLITK_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_highd_splitk_8de8_v1', guard_condition='dtype == bfloat16 and D in [320, 384, 448, 512] and N % 128 == 0 and K % 256 == 0 and num_n_tiles <= 16 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', reason='8de8 split-K is selected only for measured low point-tile high-K high-D wins')
+ROUTE_HIGHD_PAIRED_PACKEDPARTIAL = RouteDecision(route_id=HIGHD_PAIRED_PACKEDPARTIAL_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1:launch_for_eval', selected_seed=HIGHD_PAIRED_PACKEDPARTIAL_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_highd_paired_packedpartial_gridcap160_0194_v1', guard_condition='dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448, 512]', reason='round-35 same-session audit showed the paired packed-partial seed beats the exported highd_splitk route for the no-padding D448/D512 paired rows')
+ROUTE_HIGHD_NO_PADDING_PORTFOLIO_R63 = RouteDecision(route_id=HIGHD_NO_PADDING_PORTFOLIO_R63_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1:launch_for_eval', selected_seed=HIGHD_NO_PADDING_PORTFOLIO_R63_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_no_padding_highd_portfolio_r63_g1_d512n512_v1', guard_condition='dtype == bfloat16 and (B, N, K, D) is one of the exact no-padding high-D portfolio rows measured in R63', reason='R63 portfolio is the validated no-padding high-D path; it keeps the R52 portfolio for established rows and uses the G1/R4 streamdep child for D512/N512/K4096')
+ROUTE_D768_PRIORITY = RouteDecision(route_id=D768_PRIORITY_ROUTE_ID, entrypoint='loom.examples.weave.flash_kmeans_assign_d768_no_padding_splitk_priority_d768_exact_seed_v1:launch_for_eval', selected_seed=D768_PRIORITY_SEED_ID, route_kind='specialized', route_source='shape-specific-seed', guard_id='guard_d768_no_padding_priority_exact5_incumbent', guard_condition='dtype == bfloat16 and D == 768 and (B, N, K) in [(1,512,4096), (1,1024,4096), (1,512,8192), (1,1024,8192), (1,2048,4096)]', reason='exact-D768 priority comparator route reuses the validated no-padding G1/R4 Split-K Weave seed; it closes the contract comparator gap without padding')
+_ROUTE_FNS: dict[str, Callable[[dict[str, Any]], Any]] = {D64_ROUTE_ID: _d64_direct.launch_for_eval, D112_A262_ROUTE_ID: _d112_a262.launch_for_eval, MICRODIM_PAD64_ROUTE_ID: _gap_pad.launch_for_eval, MICRODIM_PIPELINE4_ROUTE_ID: _microdim_pipeline4.launch_for_eval, MICRODIM_HYBRID_ROUTE_ID: _microdim.launch_for_eval, LOWDIM_E50C_ROUTE_ID: _lowdim.launch_for_eval, D480_EAC2_ROUTE_ID: _d480_eac2.launch_for_eval, GAP_PAD_ROUTE_ID: _gap_pad.launch_for_eval, D352_EXACTD_ROUTE_ID: _d352_exactd.launch_for_eval, D224_D17C_ROUTE_ID: _d224_d17c.launch_for_eval, D288_PARENT_SPLITK_HYBRID_ROUTE_ID: _d288_hybrid.launch_for_eval, SMALL_ROUTE_ID: _single.launch_for_eval, PAIRED_ROUTE_ID: _paired.launch_for_eval, D128_PRIORITY_SPLITK_ROUTE_ID: _d128_priority.launch_for_eval, D128_EVEN_NEAR_FLOOR_V10_ROUTE_ID: _single.launch_for_eval, GENERIC_FALLBACK_ID: _single.launch_for_eval, D144_D160_D176_PAD192_F9B2_ROUTE_ID: _tail_pad192_f9b2.launch_for_eval, D160_PADDED_ROUTE_ID: _non128d_d160.launch_for_eval, D192_SINGLE_ROUTE_ID: _non128d_v1.launch_for_eval, D192_PAIRED_ROUTE_ID: _non128d_v1.launch_for_eval, D256_SINGLE_ROUTE_ID: _non128d_v1.launch_for_eval, HIGHD_SPLITD_ROUTE_ID: _highd.launch_for_eval, HIGHD_SPLITK_ROUTE_ID: _highd_splitk.launch_for_eval, HIGHD_PAIRED_PACKEDPARTIAL_ROUTE_ID: _highd_paired_gridcap160.launch_for_eval, HIGHD_NO_PADDING_PORTFOLIO_R63_ROUTE_ID: _highd_no_padding_r63.launch_for_eval, D768_PRIORITY_ROUTE_ID: _d768_priority.launch_for_eval}
+_LAST_ROUTE_TRACE: list[dict[str, Any]] = []
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Contract-harness entrypoint for the explicit guarded portfolio."""
+    decision = select_route(inputs)
+    return _launch_route(inputs, decision)
+
+def prepare_launch_plan(inputs: dict[str, Any], *, arch: str | None=None, stream: Any=None, timeout_ms: float | None=None) -> PreparedKMeansLaunchPlan:
+    """Resolve and marshal a complete route once for allocation-free reuse.
+
+    Preparation executes the selected route's host setup under launch capture.
+    That eagerly creates every route-specific scratch tensor, TMA descriptor,
+    compiled module, launch argument array, and nested child decision without
+    submitting GPU work.  The returned plan is tied to these exact input and
+    output tensors.
+    """
+    import torch
+    from .._dispatch_runtime import detect_gpu_arch
+    from .._dispatch_runtime import capture_kernel_launches
+    input_device = inputs['x'].device
+    device_index = input_device.index
+    if device_index is None:
+        device_index = torch.cuda.current_device()
+    device_index = int(device_index)
+    with torch.cuda.device(device_index):
+        resolved_stream = torch.cuda.current_stream(device_index) if stream is None else stream
+        stream_device = getattr(resolved_stream, 'device', None)
+        stream_device_index = getattr(stream_device, 'index', stream_device)
+        if stream_device_index is not None and int(stream_device_index) != device_index:
+            raise ValueError(''.join(['Flash-KMeans stream device ', format(stream_device_index, ''), ' does not match input device ', format(device_index, '')]))
+        stream_handle = int(resolved_stream.cuda_stream)
+        with torch.cuda.stream(resolved_stream):
+            detected_arch = detect_gpu_arch()
+            resolved_arch = detected_arch if arch is None else str(arch)
+            if resolved_arch != detected_arch:
+                raise ValueError(''.join(['flash_kmeans_assign launch arch must match the active device: requested ', format(resolved_arch, ''), ', detected ', format(detected_arch, '')]))
+            if resolved_arch not in {'sm_100a', 'sm_103a'}:
+                raise ValueError(''.join(['flash_kmeans_assign prepared routes require sm_100a or sm_103a, got ', format(resolved_arch, '')]))
+            decision = select_route(inputs)
+            shape = _shape_fields(inputs)
+            trace = decision.trace_row(shape_key=_shape_key(inputs))
+            with _PREPARE_LOCK:
+                for key in tuple(inputs):
+                    if key.startswith('_flash_kmeans_assign_'):
+                        inputs.pop(key)
+                inputs['_flash_kmeans_assign_prepared_stream_key'] = (device_index, stream_handle)
+                inputs['_flash_kmeans_assign_dispatch_route'] = trace
+                route_launcher = _ROUTE_FNS[decision.route_id]
+                with capture_kernel_launches(stream=resolved_stream, arch=resolved_arch, inputs=inputs) as captured:
+                    prepared_outputs = route_launcher(inputs)
+                prepared_result = _finish_route(inputs, decision, prepared_outputs)
+                direct_launcher = captured.bind(prepared_result)
+                _LAST_ROUTE_TRACE[:] = [trace]
+    return PreparedKMeansLaunchPlan(inputs=inputs, decision=decision, arch=resolved_arch, shape=shape, direct_launcher=direct_launcher, launch_count=direct_launcher.launch_count, device_index=device_index, stream=resolved_stream, stream_handle=stream_handle, timeout_ms=timeout_ms)
+
+def launch_prepared(plan: PreparedKMeansLaunchPlan, *, stream: Any=None, timeout_ms: float | None=None, public_inputs_already_recorded: bool=False) -> dict[str, Any]:
+    """Launch a plan returned by :func:`prepare_launch_plan`."""
+    if not isinstance(plan, PreparedKMeansLaunchPlan):
+        raise TypeError('plan must be returned by prepare_launch_plan')
+    return plan.launch(stream=stream, timeout_ms=timeout_ms, public_inputs_already_recorded=public_inputs_already_recorded)
+
+def launch_for_eval_forced_fallback(inputs: dict[str, Any]) -> dict[str, Any]:
+    """Coverage probe entrypoint that forces the aligned Weave fallback route."""
+    decision = _select_fallback_route(inputs)
+    return _launch_route(inputs, decision)
+
+def launch_for_eval_forced_d352_exactd(inputs: dict[str, Any]) -> dict[str, Any]:
+    """ABI preflight entrypoint that forces the validated D352 exact-D route."""
+    bsz, n_points, dim, n_clusters, dtype = _shape_fields(inputs)
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype)
+    if not _use_d352_exactd(D=dim, num_n_tiles=n_points // BLOCK_N, k_tiles=n_clusters // BLOCK_K):
+        raise ValueError('forced D352 exact-D route requires D=352, N/64 <= 32, and K/256 >= 4')
+    return _launch_route(inputs, ROUTE_D352_EXACTD)
+
+def launch_for_eval_forced_d112_a262(inputs: dict[str, Any]) -> dict[str, Any]:
+    """ABI preflight entrypoint that forces the exact 14-row D112 portfolio."""
+    bsz, n_points, dim, n_clusters, dtype = _shape_fields(inputs)
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype)
+    if not _supports_d112_a262(B=bsz, N=n_points, D=dim, K=n_clusters):
+        raise ValueError('forced D112 a262 route requires one of the exact 14 assigned D112 rows')
+    return _launch_route(inputs, ROUTE_D112_A262)
+
+def launch_for_eval_forced_microdim_pipeline4(inputs: dict[str, Any]) -> dict[str, Any]:
+    """ABI preflight entrypoint for both source-supported 08f9 rows."""
+    bsz, n_points, dim, n_clusters, dtype = _shape_fields(inputs)
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype)
+    if not _supports_microdim_pipeline4(B=bsz, N=n_points, D=dim, K=n_clusters):
+        raise ValueError('forced microdim pipeline4 requires B=8, N=65536, K=512, and D in [16, 32]')
+    return _launch_route(inputs, ROUTE_MICRODIM_PIPELINE4)
+
+def last_route_trace() -> list[dict[str, Any]]:
+    return [dict(row) for row in _LAST_ROUTE_TRACE]
+
+def select_route(inputs: dict[str, Any]) -> RouteDecision:
+    bsz, n_points, dim, n_clusters, dtype = _shape_fields(inputs)
+    return select_route_from_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype)
+
+def select_route_from_shape(*, B: int, N: int, D: int, K: int, dtype: Any='bfloat16') -> RouteDecision:
+    _validate_supported_shape(B=B, N=N, D=D, K=K, dtype=dtype)
+    num_n_tiles = N // BLOCK_N
+    k_tiles = K // BLOCK_K
+    if D == _d64_direct.FEAT_D_PAD:
+        return ROUTE_D64_DIRECT_9F2A
+    if _use_microdim_pad64(B=B, N=N, D=D, K=K):
+        return ROUTE_MICRODIM_PAD64
+    if _use_microdim_pipeline4(B=B, N=N, D=D, K=K):
+        return ROUTE_MICRODIM_PIPELINE4
+    if D in _microdim.SUPPORTED_D:
+        return ROUTE_MICRODIM_HYBRID
+    if D == 288 and _use_d288_parent_splitk_hybrid(K=K):
+        return ROUTE_D288_PARENT_SPLITK_HYBRID
+    if _use_d352_exactd(D=D, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        return ROUTE_D352_EXACTD
+    if _use_d480_eac2(D=D, N=N, k_tiles=k_tiles):
+        return ROUTE_D480_EAC2
+    if _use_d224_d17c(B=B, N=N, D=D, K=K):
+        return ROUTE_D224_D17C
+    if _use_d112_a262(B=B, N=N, D=D, K=K):
+        return ROUTE_D112_A262
+    if D in _gap_pad.SUPPORTED_D:
+        return ROUTE_GAP_PAD
+    if D in {80, 96}:
+        return ROUTE_LOWDIM_E50C
+    if D in D144_D176_F9B2_DIMS:
+        return ROUTE_D144_D176_PAD192_F9B2
+    if D == 160:
+        return ROUTE_D160_PADDED
+    if D == 192:
+        if num_n_tiles % 2 != 0 or (num_n_tiles <= SMALL_GRID_N_TILE_CAP and k_tiles <= SMALL_GRID_K_TILE_CAP):
+            return ROUTE_D192_SINGLE
+        return ROUTE_D192_PAIRED
+    if D == 256:
+        return ROUTE_D256_SINGLE
+    if D == _d768_priority.TARGET_D:
+        return ROUTE_D768_PRIORITY
+    if _use_d128_priority_splitk(B=B, N=N, D=D, K=K):
+        return ROUTE_D128_PRIORITY_SPLITK
+    if _use_highd_no_padding_portfolio_r63(B=B, N=N, D=D, K=K):
+        return ROUTE_HIGHD_NO_PADDING_PORTFOLIO_R63
+    if _use_highd_paired_packedpartial(B=B, N=N, D=D, K=K):
+        return ROUTE_HIGHD_PAIRED_PACKEDPARTIAL
+    if D in _highd.SUPPORTED_DIMS:
+        if _use_highd_splitk(D=D, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+            return ROUTE_HIGHD_SPLITK
+        return ROUTE_HIGHD_SPLITD
+    if B == 8 and N == 8192 and (K == 256):
+        return ROUTE_D128_EVEN_NEAR_FLOOR_V10_REPAIR
+    if num_n_tiles <= SMALL_GRID_N_TILE_CAP and k_tiles <= SMALL_GRID_K_TILE_CAP:
+        return ROUTE_SMALL_V10
+    if num_n_tiles % 2 == 0:
+        return ROUTE_PAIRED_V15
+    return ROUTE_ALIGNED_V10_FALLBACK
+
+def route_trace_for_shape(label: str, params: dict[str, Any], *, expected_seed: str | None=None, dispatcher_kernel_ms: float | None=None, shape_specific_kernel_ms: float | None=None, relative_speedup_vs_baseline: float | None=None) -> dict[str, Any]:
+    try:
+        decision = select_route(params)
+    except ValueError as exc:
+        return _unsupported_trace_row(shape_key=label, expected_seed=expected_seed, dispatcher_kernel_ms=dispatcher_kernel_ms, shape_specific_kernel_ms=shape_specific_kernel_ms, relative_speedup_vs_baseline=relative_speedup_vs_baseline, reason=str(exc))
+    return decision.trace_row(shape_key=label, expected_seed=expected_seed, dispatcher_kernel_ms=dispatcher_kernel_ms, shape_specific_kernel_ms=shape_specific_kernel_ms, relative_speedup_vs_baseline=relative_speedup_vs_baseline)
+
+def route_trace_for_shapes(shapes: list[dict[str, Any]], *, expected_seeds: dict[str, str] | None=None, per_shape_metrics: dict[str, dict[str, Any]] | None=None, baseline_metrics: dict[str, dict[str, Any]] | None=None) -> list[dict[str, Any]]:
+    rows: list[dict[str, Any]] = []
+    for shape in shapes:
+        label = str(shape['label'])
+        params = dict(shape.get('params', {}))
+        metrics = (per_shape_metrics or {}).get(label, {})
+        baseline = (baseline_metrics or {}).get(label, {})
+        dispatcher_ms = _optional_float(metrics.get('kernel_ms'))
+        baseline_ms = _optional_float(baseline.get('kernel_ms'))
+        speedup = None
+        if dispatcher_ms is not None and baseline_ms is not None and (dispatcher_ms > 0.0):
+            speedup = baseline_ms / dispatcher_ms
+        rows.append(route_trace_for_shape(label, params, expected_seed=(expected_seeds or {}).get(label), dispatcher_kernel_ms=dispatcher_ms, shape_specific_kernel_ms=baseline_ms, relative_speedup_vs_baseline=speedup))
+    return rows
+
+def compile_and_launch_flash_kmeans_assign_dispatcher(B: int=2, N: int=1024, K: int=512, D: int=128, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(5101)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref)), 'route_trace': last_route_trace()}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 5101}}])
+    return result
+
+def _launch_route(inputs: dict[str, Any], decision: RouteDecision) -> dict[str, Any]:
+    trace = decision.trace_row(shape_key=_shape_key(inputs))
+    inputs['_flash_kmeans_assign_dispatch_route'] = trace
+    _LAST_ROUTE_TRACE[:] = [trace]
+    with bind_current_stream(inputs):
+        outputs = _ROUTE_FNS[decision.route_id](inputs)
+    return _finish_route(inputs, decision, outputs)
+
+def _finish_route(inputs: dict[str, Any], decision: RouteDecision, outputs: Any) -> dict[str, Any]:
+    trace = decision.trace_row(shape_key=_shape_key(inputs))
+    normalized = _normalize_outputs(outputs, inputs)
+    if decision.route_id in {D112_A262_ROUTE_ID, MICRODIM_PIPELINE4_ROUTE_ID}:
+        child_trace = normalized.get('route_trace')
+        if isinstance(child_trace, dict):
+            trace['child_route_trace'] = dict(child_trace)
+        cluster_ids = normalized['cluster_ids']
+        caller_out = inputs['out']
+        trace['caller_owned_output'] = cluster_ids is caller_out or int(cluster_ids.data_ptr()) == int(caller_out.data_ptr())
+        trace['caller_output_data_ptr'] = int(caller_out.data_ptr())
+        trace['returned_output_data_ptr'] = int(cluster_ids.data_ptr())
+    _LAST_ROUTE_TRACE[:] = [trace]
+    normalized['selected_route'] = decision.route_id
+    normalized['route_trace'] = trace
+    return normalized
+
+def _select_fallback_route(inputs: dict[str, Any]) -> RouteDecision:
+    bsz, n_points, dim, n_clusters, dtype = _shape_fields(inputs)
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype)
+    if dim != FEAT_D:
+        raise ValueError(''.join(['forced fallback is only defined for D=', format(FEAT_D, ''), ', got ', format(dim, '')]))
+    return ROUTE_ALIGNED_V10_FALLBACK
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign dispatcher route must return cluster_ids or write inputs['out']")
+
+def _shape_fields(inputs: dict[str, Any]) -> tuple[int, int, int, int, str]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = _dtype_name(inputs)
+    return (bsz, n_points, dim, n_clusters, dtype)
+
+def _validate_supported_shape(*, B: int, N: int, D: int, K: int, dtype: Any) -> None:
+    dtype_name = str(dtype).replace('torch.', '')
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_dispatcher requires bfloat16 input, got ', format(dtype, '')]))
+    if D not in SUPPORTED_DIMS:
+        raise ValueError(''.join(['flash_kmeans_assign_dispatcher has no Weave route for D=', format(D, ''), '; supported D values are ', format(SUPPORTED_DIMS, '')]))
+    if D == _d768_priority.TARGET_D and (not _is_d768_priority_shape(B=B, N=N, K=K)):
+        raise ValueError(''.join(['flash_kmeans_assign_dispatcher has a D=768 Weave route only for the validated priority shapes ', format(sorted(D768_PRIORITY_SHAPES), ''), '; got N=', format(N, ''), ', K=', format(K, '')]))
+    if N % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(N, '')]))
+    if K % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(K, '')]))
+
+def _use_highd_splitk(*, D: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > 16:
+        return False
+    return k_tiles >= 32 or (k_tiles >= _highd_splitk.SPLITK_MIN_K_TILES and D >= 448)
+
+def _use_d128_priority_splitk(*, B: int, N: int, D: int, K: int) -> bool:
+    return B == 1 and D == _d128_priority.TARGET_D and (N in (512, 1024, 2048)) and (K in (4096, 8192))
+
+def _use_microdim_pad64(*, B: int, N: int, D: int, K: int) -> bool:
+    return (B, N, K, D) in MICRODIM_PAD64_SHAPES
+
+def _supports_microdim_pipeline4(*, B: int, N: int, D: int, K: int) -> bool:
+    return (int(B), int(N), int(D), int(K)) in MICRODIM_PIPELINE4_SOURCE_SHAPES
+
+def _use_microdim_pipeline4(*, B: int, N: int, D: int, K: int) -> bool:
+    return (int(B), int(N), int(D), int(K)) in MICRODIM_PIPELINE4_SELECTED_SHAPES
+
+def _use_d224_d17c(*, B: int, N: int, D: int, K: int) -> bool:
+    return (B, N, K, D) in D224_D17C_SHAPES
+
+def _supports_d112_a262(*, B: int, N: int, D: int, K: int) -> bool:
+    return _d112_a262.supports_shape(B=B, N=N, D=D, K=K)
+
+def _use_d112_a262(*, B: int, N: int, D: int, K: int) -> bool:
+    return (int(B), int(N), int(D), int(K)) in D112_A262_SELECTED_SHAPE_KEYS
+
+def _is_d768_priority_shape(*, B: int, N: int, K: int) -> bool:
+    return (B, N, K) in D768_PRIORITY_SHAPES
+
+def _use_d288_parent_splitk_hybrid(*, K: int) -> bool:
+    """Keep unsupported middle-K values on the existing gap-pad route."""
+    return K <= 2048 or K >= 4096
+
+def _use_d352_exactd(*, D: int, num_n_tiles: int, k_tiles: int) -> bool:
+    return D == _d352_exactd.FEAT_D and num_n_tiles <= _d352_exactd.MAX_POINT_TILES and (k_tiles >= 4)
+
+def _use_d480_eac2(*, D: int, N: int, k_tiles: int) -> bool:
+    """Apply the seed guard in eac2's 64-row point-tile units."""
+    return _d480_eac2._use_k1024_splitk(dim=D, num_n_tiles=N // _d480_eac2.BLOCK_N, k_tiles=k_tiles)
+
+def _use_highd_paired_packedpartial(*, B: int, N: int, D: int, K: int) -> bool:
+    return B == 1 and N == 2048 and (K == 4096) and (D in _highd_paired_gridcap160.PAIRED_PACKEDPARTIAL_DIMS)
+
+def _use_highd_no_padding_portfolio_r63(*, B: int, N: int, D: int, K: int) -> bool:
+    return (B, N, K, D) in _highd_no_padding_r63.NO_PADDING_HIGHD_SHAPES
+
+def _classify_route(route: RouteDecision, expected_seed: str | None, relative_speedup_vs_baseline: float | None) -> str:
+    if expected_seed is not None:
+        if route.selected_seed != expected_seed:
+            return 'guard-miss'
+        if relative_speedup_vs_baseline is not None and relative_speedup_vs_baseline < SLOW_ROUTE_SPEEDUP_THRESHOLD:
+            return 'fallback-slow' if route.route_kind == 'fallback' else 'kernel-slow'
+        return 'seed-consumed'
+    if route.route_kind == 'fallback':
+        return 'coverage-only'
+    return 'route-ok'
+
+def _unsupported_trace_row(*, shape_key: str, expected_seed: str | None, dispatcher_kernel_ms: float | None, shape_specific_kernel_ms: float | None, relative_speedup_vs_baseline: float | None, reason: str) -> dict[str, Any]:
+    return {'shape_key': shape_key, 'selected_route': UNSUPPORTED_ROUTE_ID, 'selected_entrypoint': 'none', 'selected_seed': None, 'expected_seed': expected_seed, 'route_kind': 'none', 'route_source': 'unknown', 'guard_id': 'guard_miss_no_supported_weave_route', 'guard_condition': 'no production Weave guard matched this shape', 'classification': 'guard-miss' if expected_seed is not None else 'unmeasured', 'dispatcher_kernel_ms': dispatcher_kernel_ms, 'shape_specific_kernel_ms': shape_specific_kernel_ms, 'relative_speedup_vs_baseline': relative_speedup_vs_baseline, 'reason': reason}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
+
+def _optional_float(value: Any) -> float | None:
+    if value is None:
+        return None
+    return float(value)
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_gap_pad_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_gap_pad_v1.py
new file mode 100644
index 00000000..70dfc473
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_gap_pad_v1.py
@@ -0,0 +1,166 @@
+"""Flash-KMeans assignment gap-D pad-to-supported seed adapter.
+
+Minimum architecture: sm_100a. This generated-variant route zero-pads legal
+between-bucket and selected micro-D BF16 dimensions to the next existing Weave seed bucket, then
+delegates to the unmodified tcgen05/TMEM seed for that padded dimension. It is
+not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1 as _non128d
+from . import flash_kmeans_assign_cleanroom_tcgen05_v10 as _single
+from . import flash_kmeans_assign_cleanroom_tcgen05_v15 as _paired
+from . import flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1 as _d64
+from . import flash_kmeans_assign_highd_splitd_6fcf_v1 as _highd_splitd
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _highd_splitk
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = _single.BLOCK_N
+BLOCK_K = _single.BLOCK_K
+SUPPORTED_PAD: dict[int, int] = {16: 64, 32: 64, 48: 64, 112: 128, 224: 256, 288: 320, 352: 384, 416: 448, 480: 512}
+SUPPORTED_D = set(SUPPORTED_PAD)
+SEED_ID = 'gap-pad-to-supported-seed-v1'
+ROUTE_ID = 'gap_pad_to_supported_seed_v1'
+PACK_THREADS = 256
+PACK_GRID_CAP = 4096
+_SCRATCH_CACHE: dict[tuple[int, ...], tuple[Any, Any]] = {}
+_ROUTE_INPUT_CACHE: dict[tuple[int, ...], dict[str, Any]] = {}
+flash_kmeans_assign_gap_pad_pack_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_gap_pad_pack_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "D_PAD", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_gap_pad_pack_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "D_PAD", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+pack_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_gap_pad_pack_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "D_PAD", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _compiled_pack_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0338"}, "kernel_flash_kmeans_assign_gap_pad_pack_v1", 0, 256]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_gap_pad_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_gap_pad_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    d_pad = SUPPORTED_PAD[dim]
+    x_pad, c_pad = _scratch_buffers(inputs, d_pad)
+    _launch_pack(inputs, x_pad, c_pad, d_pad)
+    route_inputs = _route_inputs(inputs, x_pad, c_pad, d_pad)
+    route_fn, route_id, route_seed, route_entrypoint = _route_for_padded_dim(d_pad=d_pad, n_points=n_points, n_clusters=n_clusters)
+    outputs = route_fn(route_inputs)
+    normalized = _normalize_outputs(outputs, inputs)
+    normalized['selected_route'] = ''.join(['d', format(dim, ''), '_pad', format(d_pad, ''), '_', format(route_id, '')])
+    normalized['route_trace'] = {'shape_key': _shape_key(inputs), 'selected_route': normalized['selected_route'], 'selected_entrypoint': ''.join([format(__name__, ''), ':launch_for_eval']), 'selected_seed': ''.join(['d', format(dim, ''), '-pad', format(d_pad, ''), '-', format(route_seed, '')]), 'route_kind': 'specialized', 'route_source': 'generated-variant', 'guard_id': ''.join(['guard_d', format(dim, ''), '_pad', format(d_pad, ''), '_gap_pad_v1']), 'guard_condition': ''.join(['dtype == bfloat16 and D == ', format(dim, ''), ' and N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']), 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'residual_contract_regions': [''.join(['zero_pad_to_d', format(d_pad, ''), '_pack'])], 'reason': ''.join(['D', format(dim, ''), ' gap route pads to D', format(d_pad, ''), ' and delegates to ', format(route_entrypoint, '')])}
+    return normalized
+
+def _scratch_buffers(inputs: dict[str, Any], d_pad: int) -> tuple[Any, Any]:
+    import torch
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), bsz, n_points, n_clusters, dim, d_pad)
+    cached = _SCRATCH_CACHE.get(key)
+    if cached is not None:
+        return cached
+    x_pad = torch.empty((bsz, n_points, d_pad), dtype=inputs['x'].dtype, device=inputs['x'].device)
+    c_pad = torch.empty((bsz, n_clusters, d_pad), dtype=inputs['centroids'].dtype, device=inputs['centroids'].device)
+    _SCRATCH_CACHE[key] = (x_pad, c_pad)
+    return (x_pad, c_pad)
+
+def _launch_pack(inputs: dict[str, Any], x_pad: Any, c_pad: Any, d_pad: int) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    total_x_pad = bsz * n_points * d_pad
+    total_c_pad = bsz * n_clusters * d_pad
+    work_items = max(total_x_pad, total_c_pad)
+    grid_x = min((work_items + PACK_THREADS - 1) // PACK_THREADS, PACK_GRID_CAP)
+    cubin, kernel_name, smem_bytes, threads = _compiled_pack_kernel()
+    args = [inputs['x'], inputs['centroids'], x_pad, c_pad, bsz, n_points, dim, n_clusters, d_pad, total_x_pad, total_c_pad]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(grid_x, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _route_inputs(inputs: dict[str, Any], x_pad: Any, c_pad: Any, d_pad: int) -> dict[str, Any]:
+    key = stream_cache_key(inputs, int(x_pad.data_ptr()), int(c_pad.data_ptr()), int(inputs['x_sq'].data_ptr()), int(inputs['c_sq'].data_ptr()), int(inputs['out'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), d_pad)
+    cached = _ROUTE_INPUT_CACHE.get(key)
+    if cached is not None:
+        return cached
+    route_inputs = {'label': inputs.get('label'), 'B': int(inputs['B']), 'N': int(inputs['N']), 'D': d_pad, 'K': int(inputs['K']), 'dtype': inputs.get('dtype', 'bfloat16'), 'x': x_pad, 'centroids': c_pad, 'x_sq': inputs['x_sq'], 'c_sq': inputs['c_sq'], 'out': inputs['out'], 'original_D': int(inputs['D'])}
+    _ROUTE_INPUT_CACHE[key] = route_inputs
+    return route_inputs
+
+def _route_for_padded_dim(*, d_pad: int, n_points: int, n_clusters: int):
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    if d_pad == 64:
+        return (_d64.launch_for_eval, 'd64_direct_single64_1p2gap_9f2a_v1', 'd64-direct-single64-1p2gap-9f2a-v1', 'loom.examples.weave.flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1:launch_for_eval')
+    if d_pad == 128:
+        if num_n_tiles <= 8 and k_tiles <= 2:
+            return (_single.launch_for_eval, 'small_grid_single_tile_v10', 'small-grid-single-tile-v10', 'loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval')
+        if num_n_tiles % 2 == 0:
+            return (_paired.launch_for_eval, 'paired_large_v15', 'paired-large-v15', 'loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v15:launch_for_eval')
+        return (_single.launch_for_eval, 'aligned_weave_v10_fallback', 'small-grid-single-tile-v10', 'loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_v10:launch_for_eval')
+    if d_pad == 256:
+        return (_non128d.launch_for_eval, 'd256_single_repeated_mma_v1', 'd256-single-repeated-mma-v1', 'loom.examples.weave.flash_kmeans_assign_cleanroom_tcgen05_non128d_splitd_v1:launch_for_eval')
+    if d_pad in _highd_splitd.SUPPORTED_DIMS:
+        if _use_highd_splitk(d_pad=d_pad, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+            return (_highd_splitk.launch_for_eval, 'highd_splitk_8de8_v1', _highd_splitk.SEED_ID, 'loom.examples.weave.flash_kmeans_assign_highd_splitk_8de8_v1:launch_for_eval')
+        return (_highd_splitd.launch_for_eval, 'highd_splitd_6fcf_v1', _highd_splitd.SEED_ID, 'loom.examples.weave.flash_kmeans_assign_highd_splitd_6fcf_v1:launch_for_eval')
+    raise ValueError(''.join(['no padded route for D_PAD=', format(d_pad, '')]))
+
+def _use_highd_splitk(*, d_pad: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > 16:
+        return False
+    return k_tiles >= 32 or (k_tiles >= _highd_splitk.SPLITK_MIN_K_TILES and d_pad >= 448)
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign gap pad route must return cluster_ids or write inputs['out']")
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def compile_and_launch_flash_kmeans_assign_gap_pad(B: int=2, N: int=2048, K: int=512, D: int=112, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(11205)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref)), 'route_trace': inputs.get('_flash_kmeans_assign_dispatch_route')}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 11205}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_ownerreduce_r39_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_ownerreduce_r39_v1.py
new file mode 100644
index 00000000..93b94dda
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_ownerreduce_r39_v1.py
@@ -0,0 +1,158 @@
+"""Flash-KMeans high-D paired owner-reduce round-39 candidate.
+
+Minimum architecture: sm_100a. This additive exact-bucket seed keeps the
+Blackwell tcgen05/TMEM packed-key producer on the contract-visible path for
+B=1,N=2048,K=4096 high-D rows. D448 keeps the validated R1 reducer ownership
+but fully unrolls its eight-slice packed-key scan after a reduce2 row-group
+probe underperformed. D512 delegates to the validated gridcap160 packed-partial
+route. It is not intended for sm_120a/sm_121a where ptxas rejects tcgen05
+instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1 as _gridcap160
+from . import flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1 as _r1
+from . import flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1 as _r2
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_TILE_K = _g2r4.SPLITK_TILE_K
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PRODUCER_GRID_CAP_D448 = 128
+PAIRED_K_SLICES = 8
+REDUCE_ROW_GROUPS_D448 = 2
+REDUCE_ROWS_PER_CTA_D448 = BLOCK_N // REDUCE_ROW_GROUPS_D448
+REDUCE_THREADS_D448 = 32
+REDUCE_THREADS_R1_D448 = BLOCK_N
+U32_MASK = 4294967295
+ROUTE_ID = 'highd_paired_ownerreduce_r39_v1'
+SEED_ID = 'highd-paired-ownerreduce-r39-v1'
+flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce2_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce2_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 32}'))
+reduce1_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+reduce2_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce2_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 32}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_OWNERREDUCE_R39_VERIFY_KERNEL')
+    if verify_kernel == 'd448_reduce1':
+        return reduce1_ir
+    if verify_kernel == 'd448_reduce':
+        return reduce2_ir
+    if verify_kernel == 'd512_partial':
+        return _r2.partial_ir
+    if verify_kernel == 'd512_reduce':
+        return _r2.reduce_ir
+    return _r1.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+@lru_cache(maxsize=1)
+def _loaded_reduce2_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(reduce2_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce1_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(reduce1_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_d448_custom(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        num_n_tiles = n_points // BLOCK_N
+        k_tiles = n_clusters // MMA_BLOCK_K
+        k_slices = k_tiles // SPLITK_GROUP_K_TILES
+        if k_slices != PAIRED_K_SLICES:
+            raise ValueError(''.join([format(ROUTE_ID, ''), ' requires K_slices=', format(PAIRED_K_SLICES, ''), ', got ', format(k_slices, '')]))
+        total_work = bsz * num_n_tiles * k_slices
+        producer_grid, reducer_grid = _launch_d448_reduce1(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+        trace = _route_trace_d448(inputs, total_work=total_work, producer_grid=producer_grid, reducer_grid=reducer_grid, k_slices=k_slices)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _gridcap160.launch_for_eval(inputs)
+    trace = _wrap_gridcap160_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_d448_custom(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim == 448)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if (bsz, n_points, n_clusters, dim) not in {(1, 2048, 4096, 448), (1, 2048, 4096, 512)}:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' is exact-shape only for paired D448/D512 rows']))
+
+def _launch_d448_reduce2(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> tuple[tuple[int, int, int], tuple[int, int, int]]:
+    import torch
+    partial_keys = _r1._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _r1._loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(_r1.partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    producer_grid = (min(total_work, PRODUCER_GRID_CAP_D448), 1, 1)
+    partial_kernel.launch(grid=producer_grid, block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce2_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reducer_work = bsz * num_n_tiles * REDUCE_ROW_GROUPS_D448
+    reducer_grid = (min(reducer_work, SPLITK_GRID_CAP), 1, 1)
+    reduce_kernel.launch(grid=reducer_grid, block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+    return (producer_grid, reducer_grid)
+
+def _launch_d448_reduce1(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> tuple[tuple[int, int, int], tuple[int, int, int]]:
+    import torch
+    partial_keys = _r1._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _r1._loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(_r1.partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    producer_grid = (min(total_work, PRODUCER_GRID_CAP_D448), 1, 1)
+    partial_kernel.launch(grid=producer_grid, block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce1_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reducer_grid = (min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1)
+    reduce_kernel.launch(grid=reducer_grid, block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+    return (producer_grid, reducer_grid)
+
+def _route_trace_d448(inputs: dict[str, Any], *, total_work: int, producer_grid: tuple[int, int, int], reducer_grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_ownerreduce_r39_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_ownerreduce_r39_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448,512]; D448 uses unrolled R1 reducer ownership, D512 delegates to gridcap160', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': producer_grid, 'reduce_grid': reducer_grid, 'paired_packedpartial_route': True, 'selected_reducer_variant': 'r39_reduce1_unroll8', 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'producer_work_items': total_work, 'producer_grid_cap': PRODUCER_GRID_CAP_D448, 'producer_grid_work_items_per_cta': total_work // min(total_work, PRODUCER_GRID_CAP_D448), 'producer_to_consumer': 'u64_partial_key_buffer_plus_reduce1_unroll8', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': 1, 'reducer_threads': REDUCE_THREADS_R1_D448, 'producer_to_reducer_sync': 'same_stream_ordering', 'reducer_scan_unroll': PAIRED_K_SLICES}, 'reason': 'D448 keeps the R1 tcgen05 packed-key producer and row ownership but fully unrolls the eight-slice packed-key scan after the reduce2 row-group probe underfed the seed'}
+
+def _wrap_gridcap160_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_ownerreduce_r39_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_ownerreduce_r39_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448,512]; D448 uses unrolled R1 reducer ownership, D512 delegates to gridcap160', 'classification': 'route-ok', 'child_route': child_outputs.get('selected_route') or child_trace.get('selected_route'), 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'selected_reducer_variant': 'gridcap160_child', 'paired_packedpartial_route': True, 'reason': 'D512 keeps the validated gridcap160 producer cap and R2 reducer child'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_ownerreduce_r39(B: int=1, N: int=2048, K: int=4096, D: int=448, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = 44801 if D == 448 else 51202
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': seed}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1.py
new file mode 100644
index 00000000..844dc6cb
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1.py
@@ -0,0 +1,134 @@
+"""Flash-KMeans high-D paired packed-partial grid-cap candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel candidate keeps the
+Blackwell tcgen05/TMEM G2 packed-key distance producer on the contract-visible
+path for paired B=1,N=2048,K=4096 high-D rows. It preserves the validated R1
+reducer for D=448 and R2 reducer for D=512, but caps producer launch work at
+128 CTAs so each producer CTA owns two fixed K-slice work items. Huge-K focus
+rows delegate to the validated 4f2c stream-ordered child. It is not intended
+for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1 as _r1
+from . import flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1 as _r2
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1 as _streamdep
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_TILE_K = _g2r4.SPLITK_TILE_K
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+PRODUCER_GRID_CAP = 128
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PAIRED_PACKEDPARTIAL_DIMS = {448, 512}
+ROUTE_ID = 'highd_paired_packedpartial_gridcap128_8512_v1'
+SEED_ID = 'highd-paired-packedpartial-gridcap128-8512-v1'
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_PACKEDPARTIAL_GRIDCAP128_8512_VERIFY_KERNEL')
+    if verify_kernel == 'r1_reduce':
+        return _r1.reduce_ir
+    if verify_kernel == 'r2_partial':
+        return _r2.partial_ir
+    if verify_kernel == 'r2_reduce':
+        return _r2.reduce_ir
+    if verify_kernel == 'streamdep_partial':
+        return _streamdep.partial_ir
+    if verify_kernel == 'streamdep_reduce':
+        return _streamdep.reduce_ir
+    return _r1.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_paired_gridcap(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        child = _r1 if dim == 448 else _r2
+        reducer = 'r1_single_lane' if dim == 448 else 'r2_two_lane'
+        _launch_paired_gridcap(inputs, child=child, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+        trace = _route_trace_paired(inputs, child=child, reducer=reducer)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _streamdep.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_paired_gridcap(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim in PAIRED_PACKEDPARTIAL_DIMS)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _launch_paired_gridcap(inputs: dict[str, Any], *, child: Any, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    import torch
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    total_work = bsz * num_n_tiles * k_slices
+    partial_keys = child._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = child._loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(child.partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, PRODUCER_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = child._loaded_reduce_key_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _route_trace_paired(inputs: dict[str, Any], *, child: Any, reducer: str) -> dict[str, Any]:
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    total_work = int(inputs['B']) * num_n_tiles * k_slices
+    child_entrypoint = 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1:launch_for_eval' if child is _r1 else 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1:launch_for_eval'
+    child_route = _r1.ROUTE_ID if child is _r1 else _r2.ROUTE_ID
+    child_guard = 'guard_highd_paired_packedpartial_r1_r1c1_v1' if child is _r1 else 'guard_highd_paired_packedpartial_r2_7b3c_v1'
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_gridcap128_8512_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448,512]; D=448 uses packed partial R1, D=512 uses packed partial R2, producer grid capped at 128 CTAs', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_entrypoint, 'child_guard_id': child_guard, 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': (min(total_work, PRODUCER_GRID_CAP), 1, 1), 'paired_packedpartial_route': True, 'selected_reducer_variant': reducer, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'producer_work_items': total_work, 'producer_grid_cap': PRODUCER_GRID_CAP, 'producer_grid_work_items_per_cta': total_work // min(total_work, PRODUCER_GRID_CAP), 'producer_to_consumer': 'u64_partial_key_buffer_plus_shape_guarded_r1_or_r2_reduce', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': _r1.REDUCE_LANES_PER_ROW if child is _r1 else _r2.REDUCE_LANES_PER_ROW, 'producer_to_reducer_sync': 'same_stream_ordering'}, 'reason': 'paired high-D row keeps the G2 tcgen05 packed-key producer but caps producer CTAs at 128 to reduce launch wave scheduling overhead while preserving the same reducer ABI'}
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    child_route = child_outputs.get('selected_route') or child_trace.get('selected_route')
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_gridcap128_8512_v1', 'guard_condition': 'dtype == bfloat16 and D in [384,448,512] and N % 64 == 0 and K % 256 == 0; paired B=1,N=2048,K=4096,D in [448,512] uses 128-grid-cap packed partial keys, other high-D rows use highd_splitk_blockn64_g2r4_streamdep_4f2c_v1', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'paired_packedpartial_route': False, 'reason': 'non-paired high-D focus row keeps the stream-ordered G2/R4 Split-K child'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_packedpartial(B: int=1, N: int=2048, K: int=4096, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = 44801 if D == 448 else 51202
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': seed}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1.py
new file mode 100644
index 00000000..53c8480d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1.py
@@ -0,0 +1,135 @@
+"""Flash-KMeans high-D paired packed-partial grid-cap-160 candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel candidate keeps the
+Blackwell tcgen05/TMEM packed-key distance producer on the contract-visible
+path for paired B=1,N=2048,K=4096 high-D rows. D=512 changes producer work
+ownership from the 128-CTA cap to a 160-CTA cap while keeping the validated R2
+reducer; D=448 and other high-D focus rows delegate to the gridcap128 seed
+because the 160-CTA cap was slower for D=448. It is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_packedpartial_gridcap128_8512_v1 as _gridcap128
+from . import flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1 as _r1
+from . import flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1 as _r2
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1 as _streamdep
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_TILE_K = _g2r4.SPLITK_TILE_K
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+PRODUCER_GRID_CAP = 160
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PAIRED_PACKEDPARTIAL_DIMS = {448, 512}
+ROUTE_ID = 'highd_paired_packedpartial_gridcap160_0194_v1'
+SEED_ID = 'highd-paired-packedpartial-gridcap160-0194-v1'
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_PACKEDPARTIAL_GRIDCAP160_0194_VERIFY_KERNEL')
+    if verify_kernel == 'r1_reduce':
+        return _r1.reduce_ir
+    if verify_kernel == 'r2_partial':
+        return _r2.partial_ir
+    if verify_kernel == 'r2_reduce':
+        return _r2.reduce_ir
+    if verify_kernel == 'streamdep_partial':
+        return _streamdep.partial_ir
+    if verify_kernel == 'streamdep_reduce':
+        return _streamdep.reduce_ir
+    return _r1.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_paired_gridcap160(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        child = _r2
+        reducer = 'r2_two_lane'
+        _launch_paired_gridcap(inputs, child=child, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+        trace = _route_trace_paired(inputs, child=child, reducer=reducer)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _gridcap128.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_paired_gridcap160(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim == 512)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _launch_paired_gridcap(inputs: dict[str, Any], *, child: Any, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    import torch
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    total_work = bsz * num_n_tiles * k_slices
+    partial_keys = child._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = child._loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(child.partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, PRODUCER_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = child._loaded_reduce_key_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _route_trace_paired(inputs: dict[str, Any], *, child: Any, reducer: str) -> dict[str, Any]:
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    total_work = int(inputs['B']) * num_n_tiles * k_slices
+    producer_grid = min(total_work, PRODUCER_GRID_CAP)
+    child_entrypoint = 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1:launch_for_eval' if child is _r1 else 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1:launch_for_eval'
+    child_route = _r1.ROUTE_ID if child is _r1 else _r2.ROUTE_ID
+    child_guard = 'guard_highd_paired_packedpartial_r1_r1c1_v1' if child is _r1 else 'guard_highd_paired_packedpartial_r2_7b3c_v1'
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_gridcap160_0194_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D == 512; D=512 uses packed partial R2 with producer grid capped at 160 CTAs', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_entrypoint, 'child_guard_id': child_guard, 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': (producer_grid, 1, 1), 'paired_packedpartial_route': True, 'selected_reducer_variant': reducer, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'producer_work_items': total_work, 'producer_grid_cap': PRODUCER_GRID_CAP, 'producer_grid_work_items_per_cta_floor': total_work // producer_grid, 'producer_grid_remainder_work_items': total_work % producer_grid, 'producer_to_consumer': 'u64_partial_key_buffer_plus_shape_guarded_r1_or_r2_reduce', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': _r1.REDUCE_LANES_PER_ROW if child is _r1 else _r2.REDUCE_LANES_PER_ROW, 'producer_to_reducer_sync': 'same_stream_ordering'}, 'reason': 'paired D512 row keeps the G2 tcgen05 packed-key producer but caps producer CTAs at a small over-subscription of the B200 SM count to test one full producer wave plus a residual wave'}
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_gridcap160_0194_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_gridcap160_0194_v1', 'guard_condition': 'dtype == bfloat16 and D in [384,448,512] and N % 64 == 0 and K % 256 == 0; paired B=1,N=2048,K=4096,D=512 uses 160-grid-cap packed partial keys, D=448 and other high-D rows delegate to highd_paired_packedpartial_gridcap128_8512_v1', 'classification': 'route-ok', 'child_route': child_outputs.get('selected_route') or child_trace.get('selected_route'), 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'paired_packedpartial_route': bool(child_trace.get('paired_packedpartial_route', False)), 'reason': 'D448 and non-paired high-D focus rows delegate to the prior gridcap128 composite seed'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_packedpartial(B: int=1, N: int=2048, K: int=4096, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = 44801 if D == 448 else 51202
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': seed}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1.py
new file mode 100644
index 00000000..25e0bbc4
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1.py
@@ -0,0 +1,159 @@
+"""Flash-KMeans high-D paired packed-partial R1 Split-K candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel candidate keeps the
+Blackwell tcgen05/TMEM G2 distance-product producer on the contract-visible
+path for paired B=1,N=2048,K=4096 high-D rows, but replaces separate
+partial-score and partial-index buffers with one ordered u64 key per row and
+K-slice. A single reducer thread scans the packed keys for each row and writes
+cluster IDs.
+Huge-K focus rows delegate to the validated 4f2c stream-ordered child. It is
+not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1 as _streamdep
+from .flash_kmeans_assign_stream import stream_cache_key
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+FEAT_CHUNK = _g2r4.FEAT_CHUNK
+ROW16_LOAD_COUNT = _g2r4.ROW16_LOAD_COUNT
+ROW16_LOGICAL_CHUNK_K = _g2r4.ROW16_LOGICAL_CHUNK_K
+CSQ_STAGE_VEC = _g2r4.CSQ_STAGE_VEC
+X_TILE_BYTES = _g2r4.X_TILE_BYTES
+C_TILE_BYTES = _g2r4.C_TILE_BYTES
+CSQ_TILE_BYTES = _g2r4.CSQ_TILE_BYTES
+SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_TILE_K = _g2r4.SPLITK_TILE_K
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PAIRED_PACKEDPARTIAL_DIMS = {448, 512}
+NUM_COMPUTE_WARPS = _g2r4.NUM_COMPUTE_WARPS
+REDUCE_LANES_PER_ROW = 1
+REDUCE_THREADS = BLOCK_N * REDUCE_LANES_PER_ROW
+PAIRED_K_SLICES = 8
+U32_MASK = 4294967295
+ROUTE_ID = 'highd_paired_packedpartial_r1_r1c1_v1'
+SEED_ID = 'highd-paired-packedpartial-r1-r1c1-v1'
+flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_highd_paired_packedpartial_reduce_r1_r1c1_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_reduce_r1_r1c1_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_reduce_r1_r1c1_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_PACKEDPARTIAL_R1_R1C1_VERIFY_KERNEL')
+    if verify_kernel == 'reduce':
+        return reduce_ir
+    if verify_kernel == 'streamdep_partial':
+        return _streamdep.partial_ir
+    if verify_kernel == 'streamdep_reduce':
+        return _streamdep.reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_r1c1_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_key_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(partial_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce_key_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(reduce_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_paired_packedpartial(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        num_n_tiles = n_points // BLOCK_N
+        k_tiles = n_clusters // MMA_BLOCK_K
+        k_slices = k_tiles // SPLITK_GROUP_K_TILES
+        total_work = bsz * num_n_tiles * k_slices
+        _launch_paired_packedpartial(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+        trace = _route_trace_paired(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _streamdep.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_paired_packedpartial(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim in PAIRED_PACKEDPARTIAL_DIMS)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _launch_paired_packedpartial(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> None:
+    import torch
+    if k_slices != PAIRED_K_SLICES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires K_slices=', format(PAIRED_K_SLICES, ''), ', got ', format(k_slices, '')]))
+    partial_keys = _partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce_key_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _partial_key_buffer(inputs: dict[str, Any], total_work: int) -> Any:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work), int(BLOCK_N), int(SPLITK_GROUP_K_TILES))
+    cache = inputs.setdefault('_flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1_keys', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    keys = torch.empty((total_work, BLOCK_N), dtype=torch.int64, device=inputs['x'].device)
+    cache[cache_key] = keys
+    return keys
+
+def _route_trace_paired(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_r1_r1c1_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448, 512]', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'producer_work_items': total_work, 'producer_to_consumer': 'u64_partial_key_buffer_plus_r1_reduce', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': REDUCE_LANES_PER_ROW, 'reducer_fixed_k_slices': PAIRED_K_SLICES, 'producer_to_reducer_sync': 'same_stream_ordering'}, 'reason': 'paired high-D row keeps the G2 tcgen05 Split-K producer but packs score/index partials into one u64 buffer and scans all K-slice keys with a single row thread'}
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    child_route = child_outputs.get('selected_route') or child_trace.get('selected_route')
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_r1_r1c1_v1', 'guard_condition': 'dtype == bfloat16 and D in [384,448,512] and N % 64 == 0 and K % 256 == 0; paired B=1,N=2048,K=4096,D in [448,512] uses packed partial keys, all other focus rows use highd_splitk_blockn64_g2r4_streamdep_4f2c_v1', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'reason': 'non-paired high-D focus row keeps the stream-ordered G2/R4 Split-K child'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_packedpartial(B: int=1, N: int=2048, K: int=4096, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51202)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51202}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1.py
new file mode 100644
index 00000000..32c1d4d8
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1.py
@@ -0,0 +1,170 @@
+"""Flash-KMeans high-D paired packed-partial R2 Split-K candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel candidate keeps the
+Blackwell tcgen05/TMEM G2 distance-product producer on the contract-visible
+path for paired B=1,N=2048,K=4096 high-D rows, but replaces separate
+partial-score and partial-index buffers with one ordered u64 key per row and
+K-slice. A two-lane reducer scans packed keys and writes cluster IDs.
+Huge-K focus rows delegate to the validated 4f2c stream-ordered child. It is
+not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1 as _streamdep
+from .flash_kmeans_assign_stream import stream_cache_key
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+FEAT_CHUNK = _g2r4.FEAT_CHUNK
+ROW16_LOAD_COUNT = _g2r4.ROW16_LOAD_COUNT
+ROW16_LOGICAL_CHUNK_K = _g2r4.ROW16_LOGICAL_CHUNK_K
+CSQ_STAGE_VEC = _g2r4.CSQ_STAGE_VEC
+X_TILE_BYTES = _g2r4.X_TILE_BYTES
+C_TILE_BYTES = _g2r4.C_TILE_BYTES
+CSQ_TILE_BYTES = _g2r4.CSQ_TILE_BYTES
+DEFAULT_SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_GROUP_K_TILES_ENV = 'LOOM_FLASH_KMEANS_HIGHD_PAIRED_PACKEDPARTIAL_R2_7B3C_GROUP_K_TILES'
+
+def _configured_splitk_group_k_tiles() -> int:
+    raw = os.environ.get(SPLITK_GROUP_K_TILES_ENV)
+    if raw is None or raw == '':
+        return DEFAULT_SPLITK_GROUP_K_TILES
+    value = int(raw)
+    if value not in (1, DEFAULT_SPLITK_GROUP_K_TILES):
+        raise ValueError(''.join([format(SPLITK_GROUP_K_TILES_ENV, ''), ' must be 1 or ', format(DEFAULT_SPLITK_GROUP_K_TILES, ''), ', got ', format(value, '')]))
+    return value
+SPLITK_GROUP_K_TILES = _decode_capture(_json_loads('2'))
+SPLITK_TILE_K = MMA_BLOCK_K * SPLITK_GROUP_K_TILES
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PAIRED_PACKEDPARTIAL_DIMS = {448, 512}
+NUM_COMPUTE_WARPS = _g2r4.NUM_COMPUTE_WARPS
+REDUCE_LANES_PER_ROW = 2
+REDUCE_THREADS = BLOCK_N * REDUCE_LANES_PER_ROW
+U32_MASK = 4294967295
+if SPLITK_GROUP_K_TILES == DEFAULT_SPLITK_GROUP_K_TILES:
+    ROUTE_ID = 'highd_paired_packedpartial_r2_7b3c_v1'
+    SEED_ID = 'highd-paired-packedpartial-r2-7b3c-v1'
+else:
+    ROUTE_ID = 'highd_paired_packedpartial_r2_g1_tileprobe_7b3c_v1'
+    SEED_ID = 'highd-paired-packedpartial-r2-g1-tileprobe-7b3c-v1'
+flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_PACKEDPARTIAL_R2_7B3C_VERIFY_KERNEL')
+    if verify_kernel == 'reduce':
+        return reduce_ir
+    if verify_kernel == 'streamdep_partial':
+        return _streamdep.partial_ir
+    if verify_kernel == 'streamdep_reduce':
+        return _streamdep.reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_key_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(partial_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce_key_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(reduce_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_paired_packedpartial(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        num_n_tiles = n_points // BLOCK_N
+        k_tiles = n_clusters // MMA_BLOCK_K
+        k_slices = k_tiles // SPLITK_GROUP_K_TILES
+        total_work = bsz * num_n_tiles * k_slices
+        _launch_paired_packedpartial(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+        trace = _route_trace_paired(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _streamdep.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_paired_packedpartial(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim in PAIRED_PACKEDPARTIAL_DIMS)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _launch_paired_packedpartial(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> None:
+    import torch
+    partial_keys = _partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce_key_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _partial_key_buffer(inputs: dict[str, Any], total_work: int) -> Any:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work), int(BLOCK_N), int(SPLITK_GROUP_K_TILES))
+    cache = inputs.setdefault('_flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1_keys', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    keys = torch.empty((total_work, BLOCK_N), dtype=torch.int64, device=inputs['x'].device)
+    cache[cache_key] = keys
+    return keys
+
+def _route_trace_paired(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_r2_7b3c_v1', 'guard_condition': ''.join(['dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448, 512]; grouped_mma_k_tiles=', format(SPLITK_GROUP_K_TILES, '')]), 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'producer_work_items': total_work, 'producer_to_consumer': 'u64_partial_key_buffer_plus_r2_reduce', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': REDUCE_LANES_PER_ROW, 'producer_to_reducer_sync': 'same_stream_ordering', 'tile_probe_env': SPLITK_GROUP_K_TILES_ENV if SPLITK_GROUP_K_TILES != DEFAULT_SPLITK_GROUP_K_TILES else None}, 'reason': ''.join(['paired high-D row keeps the G2 tcgen05 Split-K producer but packs score/index partials into one u64 buffer and scans keys with a two-lane row reducer; grouped_mma_k_tiles=', format(SPLITK_GROUP_K_TILES, '')])}
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    child_route = child_outputs.get('selected_route') or child_trace.get('selected_route')
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_packedpartial_r2_7b3c_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_packedpartial_r2_7b3c_v1', 'guard_condition': 'dtype == bfloat16 and D in [384,448,512] and N % 64 == 0 and K % 256 == 0; paired B=1,N=2048,K=4096,D in [448,512] uses packed partial keys, all other focus rows use highd_splitk_blockn64_g2r4_streamdep_4f2c_v1', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'reason': 'non-paired high-D focus row keeps the stream-ordered G2/R4 Split-K child'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_packedpartial(B: int=1, N: int=2048, K: int=4096, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51202)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51202}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1.py
new file mode 100644
index 00000000..41c08c7f
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1.py
@@ -0,0 +1,137 @@
+"""Flash-KMeans high-D paired D448 X-reuse dual-TMEM round-47 candidate.
+
+Minimum architecture: sm_100a. This additive exact-bucket seed keeps the
+Blackwell tcgen05/TMEM packed-key producer on the contract-visible path for
+B=1,N=2048,K=4096,D=448, but reorders the paired local-K producer so each
+64-wide X feature tile is loaded once and consumed by two 256-column TMEM
+accumulators. The D448 reducer remains the round-39 unrolled R1 reducer, and
+D512 delegates to the round-39 route. It is not intended for sm_120a/sm_121a
+where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_ownerreduce_r39_v1 as _r39
+from . import flash_kmeans_assign_highd_paired_packedpartial_r1_r1c1_v1 as _r1
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _r39.BLOCK_N
+MMA_BLOCK_K = _r39.MMA_BLOCK_K
+FEAT_CHUNK = _g2r4.FEAT_CHUNK
+ROW16_LOAD_COUNT = _g2r4.ROW16_LOAD_COUNT
+ROW16_LOGICAL_CHUNK_K = _g2r4.ROW16_LOGICAL_CHUNK_K
+CSQ_STAGE_VEC = _g2r4.CSQ_STAGE_VEC
+X_TILE_BYTES = _g2r4.X_TILE_BYTES
+C_TILE_BYTES = _g2r4.C_TILE_BYTES
+CSQ_TILE_BYTES = _g2r4.CSQ_TILE_BYTES
+SPLITK_GROUP_K_TILES = _r39.SPLITK_GROUP_K_TILES
+C_PAIR_BYTES = SPLITK_GROUP_K_TILES * C_TILE_BYTES
+SPLITK_TILE_K = _r39.SPLITK_TILE_K
+SPLITK_GRID_CAP = _r39.SPLITK_GRID_CAP
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+PRODUCER_GRID_CAP_D448 = _r39.PRODUCER_GRID_CAP_D448
+PAIRED_K_SLICES = _r39.PAIRED_K_SLICES
+D448_FEATURE_TILES = 448 // FEAT_CHUNK
+NUM_COMPUTE_WARPS = _g2r4.NUM_COMPUTE_WARPS
+U32_MASK = _r39.U32_MASK
+ROUTE_ID = 'highd_paired_xreuse_dualtmem_r47_v1'
+SEED_ID = 'highd-paired-xreuse-dualtmem-r47-v1'
+flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 75776, "constants": [], "cta_group": 1, "threads": 192}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 75776, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1", "arg_keys": ["partial_keys", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 64}'))
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get('LOOM_FLASH_KMEANS_HIGHD_PAIRED_XREUSE_DUALTMEM_R47_VERIFY_KERNEL')
+    if verify_kernel == 'd448_reduce':
+        return reduce_ir
+    if verify_kernel == 'd512_partial':
+        return _r39._r2.partial_ir
+    if verify_kernel == 'd512_reduce':
+        return _r39._r2.reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 75776, "constants": [], "cta_group": 1, "threads": 192}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_key_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _base._compile_ir(partial_ir)
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _use_d448_custom(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        num_n_tiles = n_points // BLOCK_N
+        k_tiles = n_clusters // MMA_BLOCK_K
+        k_slices = k_tiles // SPLITK_GROUP_K_TILES
+        if k_slices != PAIRED_K_SLICES:
+            raise ValueError(''.join([format(ROUTE_ID, ''), ' requires K_slices=', format(PAIRED_K_SLICES, ''), ', got ', format(k_slices, '')]))
+        total_work = bsz * num_n_tiles * k_slices
+        producer_grid, reducer_grid = _launch_d448(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+        trace = _route_trace_d448(inputs, total_work=total_work, producer_grid=producer_grid, reducer_grid=reducer_grid, k_slices=k_slices)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _r39.launch_for_eval(inputs)
+    trace = _wrap_r39_trace(inputs, child_outputs=outputs)
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _use_d448_custom(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim == 448)
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if (bsz, n_points, n_clusters, dim) not in {(1, 2048, 4096, 448), (1, 2048, 4096, 512)}:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' is exact-shape only for paired D448/D512 rows']))
+
+def _launch_d448(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> tuple[tuple[int, int, int], tuple[int, int, int]]:
+    import torch
+    partial_keys = _r1._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    producer_grid = (min(total_work, PRODUCER_GRID_CAP_D448), 1, 1)
+    partial_kernel.launch(grid=producer_grid, block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _r39._loaded_reduce1_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reducer_grid = (min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1)
+    reduce_kernel.launch(grid=reducer_grid, block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+    return (producer_grid, reducer_grid)
+
+def _route_trace_d448(inputs: dict[str, Any], *, total_work: int, producer_grid: tuple[int, int, int], reducer_grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_xreuse_dualtmem_r47_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448,512]; D448 uses X-reuse dual-TMEM producer, D512 delegates to R39', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': producer_grid, 'reduce_grid': reducer_grid, 'paired_packedpartial_route': True, 'selected_reducer_variant': 'r39_reduce1_unroll8', 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'feature_tiles': D448_FEATURE_TILES, 'feature_loop_bound': 'compile_time_7', 'feature_loop_unroll': D448_FEATURE_TILES, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'x_tma_loads_per_work_item': D448_FEATURE_TILES, 'score_tmem_regions': 2, 'score_tmem_cols': [0, MMA_BLOCK_K], 'producer_work_items': total_work, 'producer_grid_cap': PRODUCER_GRID_CAP_D448, 'producer_grid_work_items_per_cta': total_work // min(total_work, PRODUCER_GRID_CAP_D448), 'producer_to_consumer': 'dual_tmem_xreuse_u64_partial_key_buffer_plus_reduce1_unroll8', 'partial_key': 'ordered_f32_score_high32_inverse_cluster_index_low32', 'reducer_lanes_per_row': 1, 'reducer_threads': _r39.REDUCE_THREADS_R1_D448, 'producer_to_reducer_sync': 'same_stream_ordering', 'reducer_scan_unroll': PAIRED_K_SLICES}, 'reason': 'D448 keeps the R39 packed-key producer/reducer ABI but loads each X feature tile once and accumulates the two paired local-K halves into separate TMEM regions before draining'}
+
+def _wrap_r39_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any]) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'shape-specific-seed-composite', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_paired_xreuse_dualtmem_r47_v1', 'guard_condition': 'dtype == bfloat16 and B == 1 and N == 2048 and K == 4096 and D in [448,512]; D448 uses X-reuse dual-TMEM producer, D512 delegates to R39', 'classification': 'route-ok', 'child_route': child_outputs.get('selected_route') or child_trace.get('selected_route'), 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'selected_reducer_variant': 'r39_d512_child', 'paired_packedpartial_route': True, 'reason': 'D512 delegates unchanged to the round-39 gridcap160 child route'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47(B: int=1, N: int=2048, K: int=4096, D: int=448, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = 44801 if D == 448 else 51202
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': seed}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitd_6fcf_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitd_6fcf_v1.py
new file mode 100644
index 00000000..184fb2f6
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitd_6fcf_v1.py
@@ -0,0 +1,118 @@
+"""Flash-KMeans Euclidean assignment high-D split-D candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for D in {320, 384, 448, 512}. It slices the feature dimension
+into 64-wide TMA/MMA groups so high-D shapes stay within shared memory. It is
+not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+FEAT_CHUNK = 64
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_CHUNK * 2
+C_TILE_BYTES = BLOCK_K * FEAT_CHUNK * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+PAIRED_GRID_CAP = 2516
+SUPPORTED_DIMS = {320, 384, 448, 512}
+BF16_DTYPE_NAMES = {'bfloat16', 'bf16', 'torch.bfloat16'}
+ROUTE_ID = 'highd_splitd_single_tile_6fcf_v1'
+SEED_ID = 'highd-splitd-single-tile-6fcf-v1'
+flash_kmeans_assign_highd_splitd_6fcf_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitd_6fcf_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']))
+    cached = inputs.get('_flash_kmeans_assign_highd_splitd_6fcf_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, FEAT_CHUNK)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K, dim, FEAT_CHUNK)
+    inputs['_flash_kmeans_assign_highd_splitd_6fcf_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0327"}, "kernel_flash_kmeans_assign_highd_splitd_6fcf_v1", 51200, 192]}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitd_6fcf_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype_name = _dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_highd_splitd_6fcf_v1 requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join(['flash_kmeans_assign_highd_splitd_6fcf_v1 supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    total_tiles = bsz * num_n_tiles
+    grid = (min(total_tiles, PAIRED_GRID_CAP), 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    trace = _route_trace(inputs, total_tiles=total_tiles, grid=grid)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def compile_and_launch_flash_kmeans_assign_highd_splitd(B: int=1, N: int=1024, K: int=512, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51201)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51201}}])
+    return result
+
+def _route_trace(inputs: dict[str, Any], *, total_tiles: int, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_splitd_6fcf_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_splitd_6fcf_v1', 'guard_condition': 'dtype == bfloat16 and D in [320, 384, 448, 512] and N % 128 == 0 and K % 256 == 0', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_tiles, 'launch_grid': grid, 'reason': 'high-D split-D seed accumulates 64-feature tcgen05 slices into one argmin path'}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_8de8_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_8de8_v1.py
new file mode 100644
index 00000000..fd78c636
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_8de8_v1.py
@@ -0,0 +1,153 @@
+"""Flash-KMeans Euclidean assignment high-D split-K candidate.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for D in {320, 384, 448, 512}. High-K rows split the cluster
+tile loop across CTAs, write one partial argmin per K tile, then reduce those
+partials with a second Weave kernel. Non-splitK rows reuse the validated 6fcf
+split-D seed. It is not intended for sm_120a/sm_121a where ptxas rejects
+tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitd_6fcf_v1 as _splitd
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = _splitd.BLOCK_N
+BLOCK_K = _splitd.BLOCK_K
+FEAT_CHUNK = _splitd.FEAT_CHUNK
+SCORE_CHUNK_K = _splitd.SCORE_CHUNK_K
+CSQ_VEC = _splitd.CSQ_VEC
+CSQ_STAGE_VEC = _splitd.CSQ_STAGE_VEC
+NUM_COMPUTE_WARPS = _splitd.NUM_COMPUTE_WARPS
+X_TILE_BYTES = _splitd.X_TILE_BYTES
+C_TILE_BYTES = _splitd.C_TILE_BYTES
+CSQ_TILE_BYTES = _splitd.CSQ_TILE_BYTES
+SUPPORTED_DIMS = set(_splitd.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_splitd.BF16_DTYPE_NAMES)
+SPLITK_GRID_CAP = 4096
+REDUCE_THREADS = 128
+SPLITK_MIN_K_TILES = 16
+ROUTE_ID = 'highd_splitk_8de8_v1'
+SEED_ID = 'highd-splitk-8de8-v1'
+flash_kmeans_assign_highd_splitk_partial_8de8_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_8de8_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_highd_splitk_reduce_8de8_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_8de8_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_8de8_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_8de8_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 128}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get('LOOM_FLASH_KMEANS_HIGHD_SPLITK_VERIFY_KERNEL') == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_8de8_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    return _splitd._cuda_include_dirs()
+
+def _compiled_partial_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0325"}, "kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1", 51200, 192]}'))
+
+def _compiled_reduce_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0326"}, "kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1", 0, 128]}'))
+
+def _compile_ir(ir_obj: Any) -> tuple[bytes, str, int, int]:
+    from .._dispatch_runtime import generate_kernel
+    from .._dispatch_runtime import compile_cuda
+    smem_bytes = ir_obj.computed_smem_bytes
+    source = generate_kernel(ir_obj, validate=False, smem_bytes=smem_bytes)
+    cubin = compile_cuda(source, options=['--use_fast_math'], include_dirs=_cuda_include_dirs())
+    return (cubin, ''.join(['kernel_', format(ir_obj.symbol, '')]), int(smem_bytes), int(ir_obj.threads))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    if not _use_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _splitd.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = _splitd.ROUTE_ID
+        outputs['route_trace'] = trace
+        return outputs
+    _launch_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles)
+    total_work = bsz * num_n_tiles * k_tiles
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1))
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_highd_splitk_8de8_v1 requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join(['flash_kmeans_assign_highd_splitk_8de8_v1 supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _use_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > 16:
+        return False
+    return k_tiles >= 32 or (k_tiles >= SPLITK_MIN_K_TILES and dim >= 448)
+
+def _launch_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    total_work = bsz * num_n_tiles * k_tiles
+    partial_scores, partial_indices = _partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _splitd._make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_partial_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes)
+    cubin, kernel_name, smem_bytes, threads = _compiled_reduce_kernel()
+    reduce_args = [partial_scores, partial_indices, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_tiles]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes)
+
+def _partial_buffers(inputs: dict[str, Any], total_work: int) -> tuple[Any, Any]:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work))
+    cache = inputs.setdefault('_flash_kmeans_assign_highd_splitk_8de8_v1_partials', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    scores = torch.empty((total_work, BLOCK_N), dtype=torch.float32, device=inputs['x'].device)
+    indices = torch.empty((total_work, BLOCK_N), dtype=torch.int32, device=inputs['x'].device)
+    cache[cache_key] = (scores, indices)
+    return (scores, indices)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_splitk_8de8_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_splitk_8de8_v1', 'guard_condition': 'dtype == bfloat16 and D in [320, 384, 448, 512] and N % 128 == 0 and K % 256 == 0 and num_n_tiles <= 16 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'reason': 'high-D split-K seed exposes K tiles as CTA work then reduces partial argmins'}
+
+def compile_and_launch_flash_kmeans_assign_highd_splitk(B: int=1, N: int=512, K: int=8192, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51204)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51204}}])
+    return result
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    return _splitd._shape_key(inputs)
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    return _splitd._dtype_name(inputs)
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1.py
new file mode 100644
index 00000000..25cb3e70
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1.py
@@ -0,0 +1,172 @@
+"""Flash-KMeans high-D Split-K BLOCK_N=64 G1/R4 streamdep round-63 candidate.
+
+Minimum architecture: sm_100a. This additive child keeps the M=64 ROW_16x256B
+partial geometry but reduces the grouped producer from two MMA K tiles per
+work item to one. The target is to double producer work feed for no-padding
+D448/D512 mid-K rows while preserving the four-lane reducer and same-stream
+producer-to-reducer ordering. It is not intended for sm_120a/sm_121a where
+ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from .flash_kmeans_assign_stream import stream_cache_key
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = 64
+MMA_BLOCK_K = _base.BLOCK_K
+FEAT_CHUNK = _base.FEAT_CHUNK
+ROW16_LOAD_COUNT = 64
+ROW16_LOGICAL_CHUNK_K = 128
+CSQ_STAGE_VEC = _base.CSQ_STAGE_VEC
+X_TILE_BYTES = BLOCK_N * FEAT_CHUNK * 2
+C_TILE_BYTES = MMA_BLOCK_K * FEAT_CHUNK * 2
+CSQ_TILE_BYTES = MMA_BLOCK_K * 4
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+SPLITK_GRID_CAP = _base.SPLITK_GRID_CAP
+SPLITK_MIN_K_TILES = _base.SPLITK_MIN_K_TILES
+SPLITK_GROUP_K_TILES = 1
+SPLITK_TILE_K = MMA_BLOCK_K * SPLITK_GROUP_K_TILES
+MAX_POINT_TILES = 32
+NUM_COMPUTE_WARPS = 4
+REDUCE_LANES_PER_ROW = 4
+REDUCE_THREADS = BLOCK_N * REDUCE_LANES_PER_ROW
+ROUTE_ID = 'highd_splitk_blockn64_g1r4_streamdep_r63_v1'
+SEED_ID = 'highd-splitk-blockn64-g1r4-streamdep-r63-v1'
+VERIFY_ENV = 'LOOM_FLASH_KMEANS_HIGHD_SPLITK_BLOCKN64_G1R4_STREAMDEP_R63_VERIFY_KERNEL'
+flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get(VERIFY_ENV) == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _compiled_partial_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0328"}, "kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", 43008, 192]}'))
+
+def _compiled_reduce_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0329"}, "kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1", 0, 256]}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _compiled_partial_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _compiled_reduce_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    if not _use_blockn64_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _base.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = _base.ROUTE_ID
+        trace['fallback_from'] = ROUTE_ID
+        trace['fallback_reason'] = 'shape does not satisfy BLOCK_N=64 grouped Split-K constraints'
+        outputs['route_trace'] = trace
+        return outputs
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    _launch_blockn64_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices)
+    total_work = bsz * num_n_tiles * k_slices
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _use_blockn64_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > MAX_POINT_TILES:
+        return False
+    if k_tiles % SPLITK_GROUP_K_TILES != 0:
+        return False
+    return k_tiles >= 32 or (k_tiles >= SPLITK_MIN_K_TILES and dim >= 448)
+
+def _launch_blockn64_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int) -> None:
+    import torch
+    total_work = bsz * num_n_tiles * k_slices
+    partial_scores, partial_indices = _partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce_kernel()
+    reduce_args = [partial_scores, partial_indices, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(BLOCK_N))
+    cached = inputs.get('_flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, FEAT_CHUNK)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, MMA_BLOCK_K, dim, FEAT_CHUNK)
+    inputs['_flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _partial_buffers(inputs: dict[str, Any], total_work: int) -> tuple[Any, Any]:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work), int(BLOCK_N), int(SPLITK_GROUP_K_TILES))
+    cache = inputs.setdefault('_flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1_partials', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    scores = torch.empty((total_work, BLOCK_N), dtype=torch.float32, device=inputs['x'].device)
+    indices = torch.empty((total_work, BLOCK_N), dtype=torch.int32, device=inputs['x'].device)
+    cache[cache_key] = (scores, indices)
+    return (scores, indices)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_splitk_blockn64_g1r4_streamdep_r63_v1', 'guard_condition': 'dtype == bfloat16 and D in [320, 384, 448, 512] and N % 64 == 0 and K % 256 == 0 and num_n_tiles <= 32 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'cluster_grouping': 1, 'tmem_layout': 'ROW_16x256B', 'producer_to_reducer_sync': 'same_stream_ordering', 'cuda_module_cache': 'persistent_per_process', 'producer_work_feed': '2x_g2_for_same_N_K'}, 'reason': 'BLOCK_N=64 G1/R4 tile-search variant uses ROW_16x256B score drains, single-MMA producer slices, and four-lane Split-K reducer'}
+
+def compile_and_launch_flash_kmeans_assign_highd_splitk_blockn64_g1r4(B: int=1, N: int=512, K: int=8192, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51204)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51204}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1.py
new file mode 100644
index 00000000..843e93b2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1.py
@@ -0,0 +1,160 @@
+"""Flash-KMeans high-D Split-K BLOCK_N=64 G2/R4 tile-search candidate.
+
+Minimum architecture: sm_100a. This candidate keeps the high-D Split-K
+tcgen05/TMEM score producer on the contract-visible path, keeps the M=64
+ROW_16x256B partial geometry, and tests a two-MMA grouped producer with the
+four-lane Split-K reducer. The goal is to expose twice as many producer CTAs
+as the G4/R4 parent without the K256 candidate's fourfold partial traffic.
+It is not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from .flash_kmeans_assign_stream import stream_cache_key
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = 64
+MMA_BLOCK_K = _base.BLOCK_K
+FEAT_CHUNK = _base.FEAT_CHUNK
+ROW16_LOAD_COUNT = 64
+ROW16_LOGICAL_CHUNK_K = 128
+CSQ_STAGE_VEC = _base.CSQ_STAGE_VEC
+X_TILE_BYTES = BLOCK_N * FEAT_CHUNK * 2
+C_TILE_BYTES = MMA_BLOCK_K * FEAT_CHUNK * 2
+CSQ_TILE_BYTES = MMA_BLOCK_K * 4
+SUPPORTED_DIMS = set(_base.SUPPORTED_DIMS)
+BF16_DTYPE_NAMES = set(_base.BF16_DTYPE_NAMES)
+SPLITK_GRID_CAP = _base.SPLITK_GRID_CAP
+SPLITK_MIN_K_TILES = _base.SPLITK_MIN_K_TILES
+SPLITK_GROUP_K_TILES = 2
+SPLITK_TILE_K = MMA_BLOCK_K * SPLITK_GROUP_K_TILES
+MAX_POINT_TILES = 32
+NUM_COMPUTE_WARPS = 4
+REDUCE_LANES_PER_ROW = 4
+REDUCE_THREADS = BLOCK_N * REDUCE_LANES_PER_ROW
+ROUTE_ID = 'highd_splitk_blockn64_g2r4_b5a6_v1'
+SEED_ID = 'highd-splitk-blockn64-g2r4-b5a6-v1'
+flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get('LOOM_FLASH_KMEANS_HIGHD_SPLITK_BLOCKN64_G2R4_B5A6_VERIFY_KERNEL') == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _compiled_partial_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0323"}, "kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", 43008, 192]}'))
+
+def _compiled_reduce_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0324"}, "kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1", 0, 256]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    if not _use_blockn64_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _base.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = _base.ROUTE_ID
+        trace['fallback_from'] = ROUTE_ID
+        trace['fallback_reason'] = 'shape does not satisfy BLOCK_N=64 grouped Split-K constraints'
+        outputs['route_trace'] = trace
+        return outputs
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    _launch_blockn64_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices)
+    total_work = bsz * num_n_tiles * k_slices
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    del bsz
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_DIMS:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' supports D=', format(sorted(SUPPORTED_DIMS), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % MMA_BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by MMA_BLOCK_K=', format(MMA_BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+
+def _use_blockn64_splitk(*, dim: int, num_n_tiles: int, k_tiles: int) -> bool:
+    if num_n_tiles > MAX_POINT_TILES:
+        return False
+    if k_tiles % SPLITK_GROUP_K_TILES != 0:
+        return False
+    return k_tiles >= 32 or (k_tiles >= SPLITK_MIN_K_TILES and dim >= 448)
+
+def _launch_blockn64_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    total_work = bsz * num_n_tiles * k_slices
+    partial_scores, partial_indices = _partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_partial_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes)
+    cubin, kernel_name, smem_bytes, threads = _compiled_reduce_kernel()
+    reduce_args = [partial_scores, partial_indices, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes)
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(BLOCK_N))
+    cached = inputs.get('_flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    from .._dispatch_runtime import create_tensor_map_3d
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    dim = int(inputs['D'])
+    tmap_x = create_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N, dim, FEAT_CHUNK)
+    tmap_c = create_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, MMA_BLOCK_K, dim, FEAT_CHUNK)
+    inputs['_flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _partial_buffers(inputs: dict[str, Any], total_work: int) -> tuple[Any, Any]:
+    import torch
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), int(inputs['D']), int(total_work), int(BLOCK_N), int(SPLITK_GROUP_K_TILES))
+    cache = inputs.setdefault('_flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1_partials', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    scores = torch.empty((total_work, BLOCK_N), dtype=torch.float32, device=inputs['x'].device)
+    indices = torch.empty((total_work, BLOCK_N), dtype=torch.int32, device=inputs['x'].device)
+    cache[cache_key] = (scores, indices)
+    return (scores, indices)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    return {'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_highd_splitk_blockn64_g2r4_b5a6_v1', 'guard_condition': 'dtype == bfloat16 and D in [320, 384, 448, 512] and N % 64 == 0 and K % 256 == 0 and num_n_tiles <= 32 and K_tiles % 2 == 0 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_work, 'launch_grid': grid, 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'cluster_grouping': 1, 'tmem_layout': 'ROW_16x256B'}, 'reason': 'BLOCK_N=64 G2/R4 tile-search variant uses ROW_16x256B score drains, two-MMA grouped producer slices, and four-lane Split-K reducer'}
+
+def compile_and_launch_flash_kmeans_assign_highd_splitk_blockn64(B: int=1, N: int=512, K: int=8192, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(51204)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 51204}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1.py
new file mode 100644
index 00000000..5a62f2e8
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1.py
@@ -0,0 +1,104 @@
+"""Flash-KMeans high-D Split-K G2/R4 stream-dependency candidate.
+
+Minimum architecture: sm_100a. This candidate reuses the b5a6 BLOCK_N=64
+G2/R4 tcgen05/TMEM partial producer and four-lane Split-K reducer unchanged,
+but queues the reducer after the producer on the same CUDA stream instead of
+waiting on the host between launches. It also keeps the loaded CUDA modules
+cached across contract iterations so the secondary launch can be queued with
+less inter-kernel idle time. It is not intended for sm_120a/sm_121a where
+ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from .._dispatch_runtime import pack_kernel_args
+BLOCK_N = _g2r4.BLOCK_N
+MMA_BLOCK_K = _g2r4.MMA_BLOCK_K
+SPLITK_GROUP_K_TILES = _g2r4.SPLITK_GROUP_K_TILES
+SPLITK_TILE_K = _g2r4.SPLITK_TILE_K
+SPLITK_GRID_CAP = _g2r4.SPLITK_GRID_CAP
+ROUTE_ID = 'highd_splitk_blockn64_g2r4_streamdep_4f2c_v1'
+SEED_ID = 'highd-splitk-blockn64-g2r4-streamdep-4f2c-v1'
+partial_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+reduce_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1", "arg_keys": ["partial_scores", "partial_indices", "out", "B", "N", "K", "num_n_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _verify_export_ir() -> Any:
+    if os.environ.get('LOOM_FLASH_KMEANS_HIGHD_SPLITK_BLOCKN64_G2R4_STREAMDEP_4F2C_VERIFY_KERNEL') == 'reduce':
+        return reduce_ir
+    return partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+@lru_cache(maxsize=1)
+def _loaded_partial_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _g2r4._compiled_partial_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+@lru_cache(maxsize=1)
+def _loaded_reduce_kernel() -> tuple[Any, int, int]:
+    from .._dispatch_runtime import CUDAKernel
+    cubin, kernel_name, smem_bytes, threads = _g2r4._compiled_reduce_kernel()
+    return (CUDAKernel(cubin, kernel_name), smem_bytes, threads)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _g2r4._validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // MMA_BLOCK_K
+    if not _g2r4._use_blockn64_splitk(dim=dim, num_n_tiles=num_n_tiles, k_tiles=k_tiles):
+        outputs = _g2r4.launch_for_eval(inputs)
+        trace = dict(outputs.get('route_trace', {}))
+        trace['selected_route'] = trace.get('selected_route', _g2r4.ROUTE_ID)
+        trace['fallback_from'] = ROUTE_ID
+        trace['fallback_reason'] = 'shape does not satisfy BLOCK_N=64 grouped Split-K constraints'
+        outputs['route_trace'] = trace
+        return outputs
+    k_slices = k_tiles // SPLITK_GROUP_K_TILES
+    total_work = bsz * num_n_tiles * k_slices
+    _launch_stream_ordered_splitk(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+    trace = _route_trace(inputs, total_work=total_work, grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), k_slices=k_slices)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _launch_stream_ordered_splitk(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> None:
+    import torch
+    partial_scores, partial_indices = _g2r4._partial_buffers(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _loaded_partial_kernel()
+    partial_args = pack_kernel_args(partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_scores=partial_scores, partial_indices=partial_indices, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    partial_kernel.launch(grid=(min(total_work, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _loaded_reduce_kernel()
+    reduce_args = [partial_scores, partial_indices, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reduce_kernel.launch(grid=(min(bsz * num_n_tiles, SPLITK_GRID_CAP), 1, 1), block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+
+def _route_trace(inputs: dict[str, Any], *, total_work: int, grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    trace = _g2r4._route_trace(inputs, total_work=total_work, grid=grid, k_slices=k_slices)
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1:launch_for_eval', 'selected_seed': SEED_ID, 'guard_id': 'guard_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1', 'guard_condition': 'dtype == bfloat16 and D in [320, 384, 448, 512] and N % 64 == 0 and K % 256 == 0 and num_n_tiles <= 32 and K_tiles % 2 == 0 and (K_tiles >= 32 or (K_tiles >= 16 and D >= 448))', 'tile_shape': {'BLOCK_N': BLOCK_N, 'BLOCK_K': SPLITK_TILE_K, 'mma_block_k': MMA_BLOCK_K, 'split_k_slices': k_slices, 'grouped_mma_k_tiles': SPLITK_GROUP_K_TILES, 'cluster_grouping': 1, 'tmem_layout': 'ROW_16x256B', 'producer_to_reducer_sync': 'same_stream_ordering', 'cuda_module_cache': 'persistent_per_process'}, 'reason': 'BLOCK_N=64 G2/R4 tile-search variant reuses b5a6 IR but queues producer and reducer on one stream without an intermediate host synchronize'})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_highd_splitk_blockn64(B: int=1, N: int=512, K: int=8192, D: int=448, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(44802)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 44802}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_lowdim_e50c_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_lowdim_e50c_v1.py
new file mode 100644
index 00000000..09d29500
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_lowdim_e50c_v1.py
@@ -0,0 +1,196 @@
+"""Flash-KMeans Euclidean assignment low-D seed for D=48/64/80/96/112.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) with a Weave BF16 pack/zero-fill producer from logical
+D=48/64/80/96/112 to a 128-wide MMA K tile. It is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from .flash_kmeans_assign_microdim_6cd2_v1 import ir as d64_ir
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D_PAD = 128
+FEAT_D_PAD_VECS = FEAT_D_PAD // 8
+FEAT_D_DIRECT = 64
+SUPPORTED_D = {48, 64, 80, 96, 112}
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D_PAD * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D_PAD * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+PACK_THREADS = 256
+PACK_GRID_CAP = 4096
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+_D64_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+flash_kmeans_assign_lowdim_pack_e50c_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_lowdim_pack_e50c_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+flash_kmeans_assign_lowdim_e50c_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_lowdim_e50c_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 100352, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_lowdim_e50c_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 100352, "constants": [], "cta_group": 1, "threads": 192}'))
+pack_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_lowdim_pack_e50c_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _create_padded_tensor_map_3d(data_ptr: int, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D_PAD, FEAT_D_PAD)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d(data_ptr, global_height, shared_height, FEAT_D_PAD, FEAT_D_PAD).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_tmaps(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> tuple[Any, Any]:
+    cache_key = (int(x_pad.data_ptr()), int(c_pad.data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_PAD)
+    cached = inputs.get('_flash_kmeans_assign_lowdim_e50c_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_padded_tensor_map_3d(x_pad.data_ptr(), bsz * n_points, BLOCK_N)
+    tmap_c = _create_padded_tensor_map_3d(c_pad.data_ptr(), bsz * n_clusters, BLOCK_K)
+    inputs['_flash_kmeans_assign_lowdim_e50c_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _create_d64_tensor_map_3d(data_ptr: int, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D_DIRECT, FEAT_D_DIRECT)
+    cached = _D64_TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d(data_ptr, global_height, shared_height, FEAT_D_DIRECT, FEAT_D_DIRECT).to(device=torch.device('cuda', device_index))
+    _D64_TMAP_CACHE[key] = cached
+    return cached
+
+def _make_d64_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_DIRECT)
+    cached = inputs.get('_flash_kmeans_assign_lowdim_e50c_v1_d64_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_d64_tensor_map_3d(inputs['x'].data_ptr(), bsz * n_points, BLOCK_N)
+    tmap_c = _create_d64_tensor_map_3d(inputs['centroids'].data_ptr(), bsz * n_clusters, BLOCK_K)
+    inputs['_flash_kmeans_assign_lowdim_e50c_v1_d64_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _scratch_buffers(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    import torch
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), bsz, n_points, n_clusters, int(inputs['D']), FEAT_D_PAD)
+    cache = inputs.setdefault('_flash_kmeans_assign_lowdim_e50c_v1_scratch', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    x_pad = torch.empty((bsz, n_points, FEAT_D_PAD), dtype=inputs['x'].dtype, device=inputs['x'].device)
+    c_pad = torch.empty((bsz, n_clusters, FEAT_D_PAD), dtype=inputs['centroids'].dtype, device=inputs['centroids'].device)
+    cache[cache_key] = (x_pad, c_pad)
+    inputs.pop('_flash_kmeans_assign_lowdim_e50c_v1_tmaps', None)
+    return (x_pad, c_pad)
+
+def _compiled_pack_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0335"}, "kernel_flash_kmeans_assign_lowdim_pack_e50c_v1", 0, 256]}'))
+
+def _compiled_d64_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0336"}, "kernel_flash_kmeans_assign_microdim_6cd2_v1", 51200, 192]}'))
+
+def _launch_d64_direct(inputs: dict[str, Any]) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    tmap_x, tmap_c = _make_d64_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_d64_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    args = pack_kernel_args(d64_ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(bsz * num_n_tiles, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _launch_pack(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    total_x_pad = bsz * n_points * FEAT_D_PAD
+    total_c_pad = bsz * n_clusters * FEAT_D_PAD
+    work_items = max(total_x_pad, total_c_pad)
+    grid_x = min((work_items + PACK_THREADS - 1) // PACK_THREADS, PACK_GRID_CAP)
+    cubin, kernel_name, smem_bytes, threads = _compiled_pack_kernel()
+    args = [inputs['x'], inputs['centroids'], x_pad, c_pad, bsz, n_points, dim, n_clusters, total_x_pad, total_c_pad]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(grid_x, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0337"}, "kernel_flash_kmeans_assign_lowdim_e50c_v1", 100352, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_lowdim_e50c_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_lowdim_e50c_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    if dim == FEAT_D_DIRECT:
+        _launch_d64_direct(inputs)
+        return {'cluster_ids': inputs['out']}
+    x_pad, c_pad = _scratch_buffers(inputs)
+    _launch_pack(inputs, x_pad, c_pad)
+    tmap_x, tmap_c = _make_tmaps(inputs, x_pad, c_pad)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_lowdim(B: int=4, N: int=1024, K: int=512, D: int=64, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(6401)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 6401}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_6cd2_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_6cd2_v1.py
new file mode 100644
index 00000000..f83d77b2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_6cd2_v1.py
@@ -0,0 +1,147 @@
+"""Flash-KMeans Euclidean assignment micro-D seed for D=16/32.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) with a Weave BF16 pack/zero-fill producer from logical D=16/32
+to a single 64-wide MMA K slice. It is not intended for sm_120a/sm_121a where
+ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from .flash_kmeans_assign_stream import stream_cache_key
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D_PAD = 64
+FEAT_D_PAD_VECS = FEAT_D_PAD // 8
+SUPPORTED_D = {16, 32}
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D_PAD * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D_PAD * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+PACK_THREADS = 256
+PACK_GRID_CAP = 4096
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+flash_kmeans_assign_microdim_pack_6cd2_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_pack_6cd2_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+flash_kmeans_assign_microdim_6cd2_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_6cd2_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_6cd2_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+pack_ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_pack_6cd2_v1", "arg_keys": ["x", "centroids", "x_pad", "c_pad", "B", "N", "D", "K", "total_x_pad", "total_c_pad"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 0, "constants": [], "cta_group": 1, "threads": 256}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _create_padded_tensor_map_3d(data_ptr: int, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D_PAD, FEAT_D_PAD)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d(data_ptr, global_height, shared_height, FEAT_D_PAD, FEAT_D_PAD).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_tmaps(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> tuple[Any, Any]:
+    cache_key = (int(x_pad.data_ptr()), int(c_pad.data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D_PAD)
+    cached = inputs.get('_flash_kmeans_assign_microdim_6cd2_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_padded_tensor_map_3d(x_pad.data_ptr(), bsz * n_points, BLOCK_N)
+    tmap_c = _create_padded_tensor_map_3d(c_pad.data_ptr(), bsz * n_clusters, BLOCK_K)
+    inputs['_flash_kmeans_assign_microdim_6cd2_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _scratch_buffers(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    import torch
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    cache_key = stream_cache_key(inputs, int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), bsz, n_points, n_clusters, int(inputs['D']))
+    cache = inputs.setdefault('_flash_kmeans_assign_microdim_6cd2_v1_scratch', {})
+    cached = cache.get(cache_key)
+    if cached is not None:
+        return cached
+    x_pad = torch.empty((bsz, n_points, FEAT_D_PAD), dtype=inputs['x'].dtype, device=inputs['x'].device)
+    c_pad = torch.empty((bsz, n_clusters, FEAT_D_PAD), dtype=inputs['centroids'].dtype, device=inputs['centroids'].device)
+    cache[cache_key] = (x_pad, c_pad)
+    inputs.pop('_flash_kmeans_assign_microdim_6cd2_v1_tmaps', None)
+    return (x_pad, c_pad)
+
+def _compiled_pack_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0333"}, "kernel_flash_kmeans_assign_microdim_pack_6cd2_v1", 0, 256]}'))
+
+def _launch_pack(inputs: dict[str, Any], x_pad: Any, c_pad: Any) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    total_x_pad = bsz * n_points * FEAT_D_PAD
+    total_c_pad = bsz * n_clusters * FEAT_D_PAD
+    work_items = max(total_x_pad, total_c_pad)
+    grid_x = min((work_items + PACK_THREADS - 1) // PACK_THREADS, PACK_GRID_CAP)
+    cubin, kernel_name, smem_bytes, threads = _compiled_pack_kernel()
+    args = [inputs['x'], inputs['centroids'], x_pad, c_pad, bsz, n_points, dim, n_clusters, total_x_pad, total_c_pad]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=(grid_x, 1, 1), block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0334"}, "kernel_flash_kmeans_assign_microdim_6cd2_v1", 51200, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> Any:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype = str(inputs.get('dtype', getattr(inputs['x'], 'dtype', 'bfloat16'))).replace('torch.', '')
+    if dtype not in {'bfloat16', 'bf16'}:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_6cd2_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_6cd2_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    x_pad, c_pad = _scratch_buffers(inputs)
+    _launch_pack(inputs, x_pad, c_pad)
+    tmap_x, tmap_c = _make_tmaps(inputs, x_pad, c_pad)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    return {'cluster_ids': inputs['out']}
+
+def compile_and_launch_flash_kmeans_assign_microdim(B: int=4, N: int=1024, K: int=512, D: int=16, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(1601)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 1601}}])
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_direct_9c0d_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_direct_9c0d_v1.py
new file mode 100644
index 00000000..4aa5adfc
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_direct_9c0d_v1.py
@@ -0,0 +1,101 @@
+"""Flash-KMeans Euclidean assignment direct micro-D seed for D=16/32.
+
+Minimum architecture: sm_100a. This candidate uses Blackwell tcgen05/TMEM
+(``lm.mma``) for D=16/32 by staging logical BF16 rows directly into a
+64-wide padded K-major shared-memory tile. It is not intended for
+sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D_PAD = 64
+FEAT_D_PAD_VECS = FEAT_D_PAD // 8
+STAGE_VEC = 8
+SUPPORTED_D = {16, 32}
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D_PAD * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D_PAD * 2
+CSQ_TILE_BYTES = BLOCK_K * 4
+ROUTE_ID = 'microdim_direct_staged_9c0d_v1'
+SEED_ID = 'microdim-direct-staged-9c0d-v1'
+BF16_DTYPE_NAMES = {'bfloat16', 'bf16', 'torch.bfloat16'}
+flash_kmeans_assign_microdim_direct_9c0d_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_direct_9c0d_v1", "arg_keys": ["x", "centroids", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_direct_9c0d_v1", "arg_keys": ["x", "centroids", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0332"}, "kernel_flash_kmeans_assign_microdim_direct_9c0d_v1", 51200, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    from .._dispatch_runtime import CUDAKernel
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype_name = _dtype_name(inputs)
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_direct_9c0d_v1 requires bfloat16 input, got ', format(dtype_name, '')]))
+    if dim not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_direct_9c0d_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(dim, '')]))
+    if n_points % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(n_points, '')]))
+    if n_clusters % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(n_clusters, '')]))
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    block = (threads, 1, 1)
+    args = [inputs['x'], inputs['centroids'], inputs['x_sq'], inputs['c_sq'], inputs['out'], bsz, n_points, dim, n_clusters, num_n_tiles, k_tiles]
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=block, args=args, shared_mem=smem_bytes)
+    trace = _route_trace(inputs, total_tiles=bsz * num_n_tiles, grid=grid)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def compile_and_launch_flash_kmeans_assign_microdim_direct(B: int=4, N: int=1024, K: int=512, D: int=16, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    torch.manual_seed(1601)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=[{'label': ''.join(['manual_b', format(B, ''), '_n', format(N, ''), '_k', format(K, ''), '_d', format(D, '')]), 'params': {'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'seed': 1601}}])
+    return result
+
+def _route_trace(inputs: dict[str, Any], *, total_tiles: int, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_microdim_direct_9c0d_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_microdim_direct_staged_9c0d_v1', 'guard_condition': 'dtype == bfloat16 and D in [16, 32] and N % 128 == 0 and K % 256 == 0', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'total_tiles': total_tiles, 'launch_grid': grid, 'reason': 'micro-D direct SMEM staging feeds one padded tcgen05 score tile without global scratch packing'}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_hybrid_9c0d_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_hybrid_9c0d_v1.py
new file mode 100644
index 00000000..3b279b95
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_hybrid_9c0d_v1.py
@@ -0,0 +1,93 @@
+"""Flash-KMeans Euclidean assignment guarded micro-D seed for D=16/32.
+
+Minimum architecture: sm_100a. This bucket seed combines two Weave-only
+tcgen05/TMEM paths: direct SMEM staging for small K=512 rows where global
+scratch packing is overhead-dominant, and the existing 6cd2 pack+TMA path for
+large/high-K rows where centroid reuse makes TMA staging faster. It is not
+intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from typing import Any
+from . import flash_kmeans_assign_microdim_6cd2_v1 as _pack
+from . import flash_kmeans_assign_microdim_direct_9c0d_v1 as _direct
+BLOCK_N = _direct.BLOCK_N
+BLOCK_K = _direct.BLOCK_K
+SUPPORTED_D = _direct.SUPPORTED_D
+BF16_DTYPE_NAMES = _direct.BF16_DTYPE_NAMES
+ROUTE_ID = 'microdim_hybrid_9c0d_v1'
+SEED_ID = 'microdim-hybrid-9c0d-v1'
+DIRECT_CHILD_ROUTE_ID = _direct.ROUTE_ID
+PACK_CHILD_ROUTE_ID = 'microdim_pack_6cd2_v1'
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_direct_9c0d_v1", "arg_keys": ["x", "centroids", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 51200, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz, n_points, dim, n_clusters, dtype_name = _shape_fields(inputs)
+    _validate_supported_shape(N=n_points, D=dim, K=n_clusters, dtype=dtype_name)
+    if _use_direct_path(N=n_points, K=n_clusters):
+        child_outputs = _direct.launch_for_eval(inputs)
+        child_route = DIRECT_CHILD_ROUTE_ID
+        child_seed = _direct.SEED_ID
+    else:
+        child_outputs = _pack.launch_for_eval(inputs)
+        child_route = PACK_CHILD_ROUTE_ID
+        child_seed = 'microdim-pack-6cd2-v1'
+    normalized = _normalize_outputs(child_outputs, inputs)
+    trace = _route_trace(inputs, child_route=child_route, child_seed=child_seed, direct_path=child_route == DIRECT_CHILD_ROUTE_ID, total_tiles=bsz * (n_points // BLOCK_N))
+    normalized['selected_route'] = ROUTE_ID
+    normalized['route_trace'] = trace
+    return normalized
+
+def _use_direct_path(*, N: int, K: int) -> bool:
+    return K == 512 and N <= 2432
+
+def _validate_supported_shape(*, N: int, D: int, K: int, dtype: Any) -> None:
+    dtype_name = str(dtype).replace('torch.', '')
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_hybrid_9c0d_v1 requires bfloat16 input, got ', format(dtype, '')]))
+    if D not in SUPPORTED_D:
+        raise ValueError(''.join(['flash_kmeans_assign_microdim_hybrid_9c0d_v1 requires D in ', format(sorted(SUPPORTED_D), ''), ', got ', format(D, '')]))
+    if N % BLOCK_N != 0:
+        raise ValueError(''.join(['N must be divisible by BLOCK_N=', format(BLOCK_N, ''), ', got ', format(N, '')]))
+    if K % BLOCK_K != 0:
+        raise ValueError(''.join(['K must be divisible by BLOCK_K=', format(BLOCK_K, ''), ', got ', format(K, '')]))
+
+def _normalize_outputs(outputs: Any, inputs: dict[str, Any]) -> dict[str, Any]:
+    if outputs is None:
+        return {'cluster_ids': inputs['out']}
+    if hasattr(outputs, 'shape'):
+        return {'cluster_ids': outputs}
+    if isinstance(outputs, dict):
+        normalized = dict(outputs)
+        if 'cluster_ids' not in normalized and 'out' in normalized:
+            normalized['cluster_ids'] = normalized['out']
+        if 'cluster_ids' in normalized:
+            return normalized
+    raise TypeError("flash_kmeans_assign microdim hybrid route must return cluster_ids or write inputs['out']")
+
+def _route_trace(inputs: dict[str, Any], *, child_route: str, child_seed: str, direct_path: bool, total_tiles: int) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_microdim_hybrid_9c0d_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_microdim_hybrid_9c0d_v1', 'guard_condition': 'dtype == bfloat16 and D in [16, 32] and N % 128 == 0 and K % 256 == 0', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'child_route': child_route, 'child_seed': child_seed, 'direct_staging': direct_path, 'total_tiles': total_tiles, 'reason': 'K=512 short rows use direct SMEM staging; larger rows retain the 6cd2 pack+TMA path for centroid reuse'}
+
+def _shape_fields(inputs: dict[str, Any]) -> tuple[int, int, int, int, str]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype_name = _dtype_name(inputs)
+    return (bsz, n_points, dim, n_clusters, dtype_name)
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_pipeline4_08f9_v4.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_pipeline4_08f9_v4.py
new file mode 100644
index 00000000..334fcc9d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_pipeline4_08f9_v4.py
@@ -0,0 +1,155 @@
+"""Flash-KMeans high-N D16 four-stage pipeline with D32 raw-TMA sibling.
+
+Minimum architecture: sm_100a.  D16 keeps one CTA per 128-point tile and
+uses exact K16, 32B-swizzled TMA operands.  Four centroid stages and four TMEM
+score stages overlap the eight K64 centroid chunks, while three point stages
+feed a bounded persistent grid.  A single cooperative K512 c_sq preload
+replaces the per-stage load/synchronize sequence, and four independent score
+chains shorten the per-row argmax dependency.  D32 retains the correct
+raw-TMA v1 child.  There is no global scratch, partial output, or
+host/reference sidecar.  This module
+is not intended for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+from . import flash_kmeans_assign_microdim_raw_tma_08f9_v1 as _d32
+BLOCK_N = 128
+BLOCK_K = 64
+FEAT_D = 16
+NUM_C_STAGES = 4
+NUM_ACC_STAGES = 4
+NUM_X_STAGES = 3
+NUM_COMPUTE_WARPS = 4
+THREADS = 192
+GRID_CAP = 152
+X_STAGE_BYTES = BLOCK_N * FEAT_D * 2
+C_STAGE_BYTES = BLOCK_K * FEAT_D * 2
+X_TOTAL_BYTES = X_STAGE_BYTES * NUM_X_STAGES
+C_TOTAL_BYTES = C_STAGE_BYTES * NUM_C_STAGES
+CSQ_ELEMS = 512
+CSQ_BYTES = CSQ_ELEMS * 4
+ROUTE_ID = 'microdim_pipeline4_08f9_v4'
+SEED_ID = 'microdim-pipeline4-08f9-v4'
+D16_CHILD_ROUTE_ID = 'microdim_d16_pipeline4_k64_08f9_v4'
+D32_CHILD_ROUTE_ID = _d32.ROUTE_ID
+TARGET_SHAPE = 'post_d895_d16_b8_n65536_k512_d16'
+TARGET_SHAPES = (TARGET_SHAPE, 'post_d895_d32_b8_n65536_k512_d32')
+BF16_DTYPE_NAMES = {'bfloat16', 'bf16', 'torch.bfloat16'}
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 23552, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 23552, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _create_d16_tmap(data_ptr: int, *, global_height: int, shared_height: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map_3d_32b
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), FEAT_D, FEAT_D)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map_3d_32b(data_ptr, global_height, shared_height, FEAT_D, FEAT_D).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_d16_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['K']), FEAT_D)
+    cached = inputs.get('_flash_kmeans_assign_microdim_pipeline4_08f9_v4_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_d16_tmap(inputs['x'].data_ptr(), global_height=bsz * n_points, shared_height=BLOCK_N)
+    tmap_c = _create_d16_tmap(inputs['centroids'].data_ptr(), global_height=bsz * n_clusters, shared_height=BLOCK_K)
+    inputs['_flash_kmeans_assign_microdim_pipeline4_08f9_v4_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_d16_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0330"}, "kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4", 23552, 192]}'))
+
+def _launch_d16(inputs: dict[str, Any]) -> None:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    n_clusters = int(inputs['K'])
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    tmap_x, tmap_c = _make_d16_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_d16_kernel()
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=FEAT_D, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    grid = (min(bsz * num_n_tiles, GRID_CAP), 1, 1)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=_dtype_name(inputs))
+    if dim == FEAT_D:
+        _launch_d16(inputs)
+        child_route = D16_CHILD_ROUTE_ID
+        child_seed = 'microdim-d16-pipeline4-k64-08f9-v4'
+    else:
+        child_outputs = _d32.launch_for_eval(inputs)
+        if child_outputs['cluster_ids'].data_ptr() != inputs['out'].data_ptr():
+            raise AssertionError('D32 raw-TMA child must write the caller-owned output')
+        child_route = D32_CHILD_ROUTE_ID
+        child_seed = _d32.SEED_ID
+    trace = _route_trace(inputs, child_route=child_route, child_seed=child_seed, pipelined=dim == FEAT_D)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def compile_and_launch_flash_kmeans_assign_microdim_b8_highn_2(*, benchmark: bool=False) -> dict[str, Any]:
+    from .._dispatch_runtime import evaluate
+    shapes = _exact_shapes(benchmark=benchmark)
+
+    def checked(inputs: dict[str, Any]) -> dict[str, Any]:
+        outputs = launch_for_eval(inputs)
+        if outputs['cluster_ids'].data_ptr() != inputs['out'].data_ptr():
+            raise AssertionError('microdim pipeline4 seed must write the caller-owned output')
+        if outputs['selected_route'] != ROUTE_ID:
+            raise AssertionError('microdim pipeline4 seed returned unexpected route metadata')
+        if outputs['route_trace']['shape_key'] != inputs['label']:
+            raise AssertionError('microdim pipeline4 seed returned the wrong shape key')
+        return outputs
+    payload = evaluate(checked, shapes=shapes, correctness=True, benchmark=benchmark, time_triton_baseline=False)
+    return {'passed': bool(payload['correctness']['all_correct']), 'contract_eval': payload}
+
+def _exact_shapes(*, benchmark: bool) -> list[dict[str, Any]]:
+    return [{'label': TARGET_SHAPES[0], 'params': {'B': 8, 'N': 65536, 'K': 512, 'D': 16, 'dtype': 'bfloat16', 'seed': 21601, 'check_correctness': True, 'benchmark': benchmark}}, {'label': TARGET_SHAPES[1], 'params': {'B': 8, 'N': 65536, 'K': 512, 'D': 32, 'dtype': 'bfloat16', 'seed': 23201, 'check_correctness': True, 'benchmark': benchmark}}]
+
+def _validate_supported_shape(*, B: int, N: int, D: int, K: int, dtype: Any) -> None:
+    dtype_name = str(dtype).replace('torch.', '')
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype, '')]))
+    if B != 8 or N != 65536 or K != 512 or (D not in {16, 32}):
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' owns B=8, N=65536, K=512, D in [16, 32]']))
+    if N % BLOCK_N != 0 or K % BLOCK_K != 0:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']))
+
+def _route_trace(inputs: dict[str, Any], *, child_route: str, child_seed: str, pipelined: bool) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_microdim_pipeline4_08f9_v4:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_microdim_pipeline4_08f9_v4', 'guard_condition': 'B == 8 and N == 65536 and K == 512 and D in [16, 32] and dtype == bfloat16', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'child_route': child_route, 'child_seed': child_seed, 'pipelined': pipelined, 'caller_owned_output': True, 'residual_contract_regions': [], 'reason': 'D16 preloads K512 c_sq once and overlaps exact K16 K64 tiles through four C/TMEM stages; D32 retains the one-CTA raw-TMA sibling'}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_raw_tma_08f9_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_raw_tma_08f9_v1.py
new file mode 100644
index 00000000..b1136878
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_microdim_raw_tma_08f9_v1.py
@@ -0,0 +1,114 @@
+"""Flash-KMeans high-N micro-D raw-TMA seed for D=16/32.
+
+Minimum architecture: sm_100a.  This candidate keeps the proven 6cd2
+tcgen05/TMEM score and argmax schedule, but replaces its global pad kernel and
+rank-3 padded tensor maps with rank-2 tensor maps over the raw logical rows.
+The 64-wide TMA box zero-fills columns beyond logical D, so the contract path
+is one assignment kernel with no global scratch handoff.  It is not intended
+for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from functools import lru_cache
+from typing import Any
+BLOCK_N = 128
+BLOCK_K = 256
+SCORE_CHUNK_K = 128
+CSQ_VEC = 4
+CSQ_STAGE_VEC = 4
+FEAT_D_PAD = 64
+SUPPORTED_D = {16, 32}
+NUM_COMPUTE_WARPS = 4
+X_TILE_BYTES = BLOCK_N * FEAT_D_PAD * 2
+C_TILE_BYTES = BLOCK_K * FEAT_D_PAD * 2
+CSQ_ELEMS = 512
+CSQ_TILE_BYTES = CSQ_ELEMS * 4
+ROUTE_ID = 'microdim_raw_tma_08f9_v1'
+SEED_ID = 'microdim-raw-tma-08f9-v1'
+BF16_DTYPE_NAMES = {'bfloat16', 'bf16', 'torch.bfloat16'}
+TARGET_SHAPE = 'post_d895_d16_b8_n65536_k512_d16'
+TARGET_SHAPES = (TARGET_SHAPE, 'post_d895_d32_b8_n65536_k512_d32')
+flash_kmeans_assign_microdim_raw_tma_08f9_v1 = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_raw_tma_08f9_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 52224, "constants": [], "cta_group": 1, "threads": 192}'))
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_microdim_raw_tma_08f9_v1", "arg_keys": ["x_tmap", "c_tmap", "x_sq", "c_sq", "out", "B", "N", "D", "K", "num_n_tiles", "K_tiles"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 52224, "constants": [], "cta_group": 1, "threads": 192}'))
+_TMAP_CACHE: dict[tuple[int, int, int, int, int, int], Any] = {}
+
+def _cuda_include_dirs() -> list[str]:
+    from .._dispatch_runtime import _cuda_include_dirs as _common_cuda_include_dirs
+    return _common_cuda_include_dirs()
+
+def _create_raw_tensor_map(data_ptr: int, *, global_height: int, shared_height: int, dim: int):
+    import torch
+    from .._dispatch_runtime import create_tensor_map
+    device_index = torch.cuda.current_device()
+    key = (device_index, int(data_ptr), int(global_height), int(shared_height), int(dim), FEAT_D_PAD)
+    cached = _TMAP_CACHE.get(key)
+    if cached is not None:
+        return cached
+    cached = create_tensor_map(data_ptr, dim, global_height, FEAT_D_PAD, shared_height, dim * 2).to(device=torch.device('cuda', device_index))
+    _TMAP_CACHE[key] = cached
+    return cached
+
+def _make_tmaps(inputs: dict[str, Any]) -> tuple[Any, Any]:
+    cache_key = (int(inputs['x'].data_ptr()), int(inputs['centroids'].data_ptr()), int(inputs['B']), int(inputs['N']), int(inputs['D']), int(inputs['K']))
+    cached = inputs.get('_flash_kmeans_assign_microdim_raw_tma_08f9_v1_tmaps')
+    if cached is not None and cached[0] == cache_key:
+        return (cached[1], cached[2])
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    tmap_x = _create_raw_tensor_map(inputs['x'].data_ptr(), global_height=bsz * n_points, shared_height=BLOCK_N, dim=dim)
+    tmap_c = _create_raw_tensor_map(inputs['centroids'].data_ptr(), global_height=bsz * n_clusters, shared_height=BLOCK_K, dim=dim)
+    inputs['_flash_kmeans_assign_microdim_raw_tma_08f9_v1_tmaps'] = (cache_key, tmap_x, tmap_c)
+    return (tmap_x, tmap_c)
+
+def _compiled_kernel() -> tuple[bytes, str, int, int]:
+    return _decode_capture(_json_loads('{"__tuple__": [{"__kernel_source__": "dispatch_kernel_0331"}, "kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1", 52224, 192]}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    from .._dispatch_runtime import CUDAKernel
+    from .._dispatch_runtime import pack_kernel_args
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    dtype_name = _dtype_name(inputs)
+    _validate_supported_shape(B=bsz, N=n_points, D=dim, K=n_clusters, dtype=dtype_name)
+    tmap_x, tmap_c = _make_tmaps(inputs)
+    cubin, kernel_name, smem_bytes, threads = _compiled_kernel()
+    num_n_tiles = n_points // BLOCK_N
+    k_tiles = n_clusters // BLOCK_K
+    grid = (bsz * num_n_tiles, 1, 1)
+    args = pack_kernel_args(ir, x_tmap=tmap_x, c_tmap=tmap_c, x_sq=inputs['x_sq'], c_sq=inputs['c_sq'], out=inputs['out'], B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles)
+    with CUDAKernel(cubin, kernel_name) as kernel:
+        kernel.launch(grid=grid, block=(threads, 1, 1), args=args, shared_mem=smem_bytes)
+    trace = _route_trace(inputs, total_tiles=bsz * num_n_tiles, grid=grid)
+    return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_supported_shape(*, B: int, N: int, D: int, K: int, dtype: Any) -> None:
+    dtype_name = str(dtype).replace('torch.', '')
+    if dtype_name not in BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype, '')]))
+    if B != 8 or N != 65536 or K != 512 or (D not in SUPPORTED_D):
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' owns B=8, N=65536, K=512, D in ', format(sorted(SUPPORTED_D), '')]))
+    if N % BLOCK_N != 0 or K % BLOCK_K != 0:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires N % ', format(BLOCK_N, ''), ' == 0 and K % ', format(BLOCK_K, ''), ' == 0']))
+
+def _route_trace(inputs: dict[str, Any], *, total_tiles: int, grid: tuple[int, int, int]) -> dict[str, Any]:
+    return {'shape_key': _shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_microdim_raw_tma_08f9_v1:launch_for_eval', 'selected_seed': SEED_ID, 'expected_seed': None, 'route_kind': 'specialized', 'route_source': 'shape-specific-seed', 'guard_id': 'guard_microdim_raw_tma_08f9_v1', 'guard_condition': 'B == 8 and N == 65536 and K == 512 and D in [16, 32] and dtype == bfloat16', 'classification': 'route-ok', 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'raw_tma_zero_fill': True, 'global_padding_scratch': False, 'total_tiles': total_tiles, 'launch_grid': grid, 'reason': 'raw rank-2 TMA zero-fills the 64-wide micro-D tile and removes the pack-kernel handoff'}
+
+def _shape_key(inputs: dict[str, Any]) -> str:
+    label = inputs.get('label')
+    if label:
+        return str(label)
+    return ''.join(['b', format(int(inputs['B']), ''), '_n', format(int(inputs['N']), ''), '_k', format(int(inputs['K']), ''), '_d', format(int(inputs['D']), '')])
+
+def _dtype_name(inputs: dict[str, Any]) -> str:
+    dtype = inputs.get('dtype')
+    if dtype is not None:
+        return str(dtype).replace('torch.', '')
+    x = inputs.get('x')
+    if x is not None and hasattr(x, 'dtype'):
+        return str(x.dtype).replace('torch.', '')
+    return 'bfloat16'
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r51_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r51_v1.py
new file mode 100644
index 00000000..63d1268a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r51_v1.py
@@ -0,0 +1,98 @@
+"""Flash-KMeans no-padding high-D Split-K portfolio round-51 candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel composition keeps
+Blackwell tcgen05/TMEM children on the contract-visible path for the no-padding
+high-D Split-K rows from the round-50 handoff plus expanded no-padding heldout
+rows. It routes D448 paired to the round-47 dual-TMEM X-reuse producer plus
+round-39 R1 reducer, D512 paired to the recorded round-39 incumbent, and the
+other high-D rows directly through the 4f2c streamdep child. It is not intended
+for sm_120a/sm_121a where ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_ownerreduce_r39_v1 as _r39
+from . import flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1 as _r47
+from . import flash_kmeans_assign_highd_splitk_8de8_v1 as _base
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_streamdep_4f2c_v1 as _streamdep
+ROUTE_ID = 'flash_kmeans_assign_no_padding_portfolio_r51_v1'
+SEED_ID = 'no-padding-highd-portfolio-r51-v1'
+VERIFY_ENV = 'LOOM_FLASH_KMEANS_NO_PADDING_PORTFOLIO_R51_VERIFY_KERNEL'
+NO_PADDING_HIGHD_SHAPES = {(1, 512, 8192, 320): 'd320_hugek_b1_n512_k8192_d320', (1, 1024, 8192, 320): 'd320_hugek_b1_n1024_k8192_d320', (1, 2048, 8192, 320): 'd320_hugek_b1_n2048_k8192_d320', (1, 512, 8192, 384): 'd384_hugek_b1_n512_k8192_d384', (1, 768, 8192, 384): 'd384_hugek_b1_n768_k8192_d384', (1, 1024, 8192, 384): 'd384_hugek_b1_n1024_k8192_d384', (1, 512, 4096, 448): 'd448_midk_b1_n512_k4096_d448', (1, 1024, 4096, 448): 'd448_midk_b1_n1024_k4096_d448', (1, 512, 8192, 448): 'd448_hugek_b1_n512_k8192_d448', (1, 1024, 8192, 448): 'd448_hugek_b1_n1024_k8192_d448', (1, 2048, 4096, 448): 'd448_paired_b1_n2048_k4096_d448', (1, 512, 4096, 512): 'd512_midk_b1_n512_k4096_d512', (1, 1024, 4096, 512): 'd512_midk_b1_n1024_k4096_d512', (1, 512, 8192, 512): 'd512_hugek_b1_n512_k8192_d512', (1, 1024, 8192, 512): 'd512_hugek_b1_n1024_k8192_d512', (1, 2048, 4096, 512): 'd512_paired_b1_n2048_k4096_d512'}
+NO_PADDING_HIGHD_EVAL_SHAPES = [{'label': 'd320_hugek_b1_n512_k8192_d320', 'params': {'B': 1, 'N': 512, 'D': 320, 'K': 8192, 'dtype': 'bfloat16', 'seed': 32004}}, {'label': 'd320_hugek_b1_n1024_k8192_d320', 'params': {'B': 1, 'N': 1024, 'D': 320, 'K': 8192, 'dtype': 'bfloat16', 'seed': 32005}}, {'label': 'd320_hugek_b1_n2048_k8192_d320', 'params': {'B': 1, 'N': 2048, 'D': 320, 'K': 8192, 'dtype': 'bfloat16', 'seed': 32006}}, {'label': 'd384_hugek_b1_n512_k8192_d384', 'params': {'B': 1, 'N': 512, 'D': 384, 'K': 8192, 'dtype': 'bfloat16', 'seed': 38403}}, {'label': 'd384_hugek_b1_n768_k8192_d384', 'params': {'B': 1, 'N': 768, 'D': 384, 'K': 8192, 'dtype': 'bfloat16', 'seed': 38404}}, {'label': 'd384_hugek_b1_n1024_k8192_d384', 'params': {'B': 1, 'N': 1024, 'D': 384, 'K': 8192, 'dtype': 'bfloat16', 'seed': 38405}}, {'label': 'd448_midk_b1_n512_k4096_d448', 'params': {'B': 1, 'N': 512, 'D': 448, 'K': 4096, 'dtype': 'bfloat16', 'seed': 44803}}, {'label': 'd448_midk_b1_n1024_k4096_d448', 'params': {'B': 1, 'N': 1024, 'D': 448, 'K': 4096, 'dtype': 'bfloat16', 'seed': 44805}}, {'label': 'd448_hugek_b1_n512_k8192_d448', 'params': {'B': 1, 'N': 512, 'D': 448, 'K': 8192, 'dtype': 'bfloat16', 'seed': 44802}}, {'label': 'd448_hugek_b1_n1024_k8192_d448', 'params': {'B': 1, 'N': 1024, 'D': 448, 'K': 8192, 'dtype': 'bfloat16', 'seed': 44806}}, {'label': 'd448_paired_b1_n2048_k4096_d448', 'params': {'B': 1, 'N': 2048, 'D': 448, 'K': 4096, 'dtype': 'bfloat16', 'seed': 44801}}, {'label': 'd512_midk_b1_n512_k4096_d512', 'params': {'B': 1, 'N': 512, 'D': 512, 'K': 4096, 'dtype': 'bfloat16', 'seed': 51203}}, {'label': 'd512_midk_b1_n1024_k4096_d512', 'params': {'B': 1, 'N': 1024, 'D': 512, 'K': 4096, 'dtype': 'bfloat16', 'seed': 51205}}, {'label': 'd512_hugek_b1_n512_k8192_d512', 'params': {'B': 1, 'N': 512, 'D': 512, 'K': 8192, 'dtype': 'bfloat16', 'seed': 51204}}, {'label': 'd512_hugek_b1_n1024_k8192_d512', 'params': {'B': 1, 'N': 1024, 'D': 512, 'K': 8192, 'dtype': 'bfloat16', 'seed': 51206}}, {'label': 'd512_paired_b1_n2048_k4096_d512', 'params': {'B': 1, 'N': 2048, 'D': 512, 'K': 4096, 'dtype': 'bfloat16', 'seed': 51202}}]
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get(VERIFY_ENV)
+    if verify_kernel == 'd448_reduce':
+        return _r47.reduce_ir
+    if verify_kernel == 'd512_partial':
+        return _r39._r2.partial_ir
+    if verify_kernel == 'd512_reduce':
+        return _r39._r2.reduce_ir
+    if verify_kernel == 'hugek_partial':
+        return _streamdep.partial_ir
+    if verify_kernel == 'hugek_reduce':
+        return _streamdep.reduce_ir
+    return _r47.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 75776, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _is_d448_paired(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        outputs = _r47.launch_for_eval(inputs)
+        trace = _wrap_child_trace(inputs, child_outputs=outputs, route_kind='shape-specific-seed-composition', selected_child='r47_dualtmem_xreuse_plus_r39_reduce1', reason='D448 paired row uses the round-47 dual-TMEM X-reuse producer and the round-39 unrolled R1 reducer')
+        return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    if _is_d512_paired(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        outputs = _r39.launch_for_eval(inputs)
+        trace = _wrap_child_trace(inputs, child_outputs=outputs, route_kind='shape-specific-seed-composition', selected_child='r39_ownerreduce_incumbent', reason='D512 paired row keeps the recorded round-39 incumbent route')
+        return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _streamdep.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs, route_kind='shape-specific-seed-composition', selected_child='4f2c_streamdep_child', reason='huge-K rows use the same-process fastest direct stream-dependency high-D Split-K child')
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _validate_shape(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int) -> None:
+    dtype_name = _base._dtype_name(inputs)
+    if dtype_name not in _base.BF16_DTYPE_NAMES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' requires bfloat16 input, got ', format(dtype_name, '')]))
+    if (bsz, n_points, n_clusters, dim) not in NO_PADDING_HIGHD_SHAPES:
+        raise ValueError(''.join([format(ROUTE_ID, ''), ' is exact-shape only for the no-padding high-D bucket, got B=', format(bsz, ''), ', N=', format(n_points, ''), ', K=', format(n_clusters, ''), ', D=', format(dim, '')]))
+
+def _is_d448_paired(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim == 448)
+
+def _is_d512_paired(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 2048 and (n_clusters == 4096) and (dim == 512)
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any], route_kind: str, selected_child: str, reason: str) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    child_route = child_outputs.get('selected_route') or child_trace.get('selected_route')
+    trace = dict(child_trace)
+    trace.update({'shape_key': _base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r51_v1:launch_for_eval', 'selected_seed': SEED_ID, 'route_kind': route_kind, 'route_source': 'shape-specific-seed-portfolio', 'guard_id': 'guard_no_padding_highd_splitk_portfolio_r51_v1', 'guard_condition': 'exact no-padding high-D bucket: D320/D384 hugeK, D448/D512 midK/hugeK/paired, all N/K aligned without padding', 'classification': 'route-ok', 'child_route': child_route, 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'portfolio_selected_child': selected_child, 'dispatcher_kernel_ms': None, 'shape_specific_kernel_ms': None, 'relative_speedup_vs_baseline': None, 'reason': reason})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_no_padding_portfolio_r51(B: int=1, N: int=2048, K: int=4096, D: int=448, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = {(1, 512, 8192, 320): 32004, (1, 1024, 8192, 320): 32005, (1, 2048, 8192, 320): 32006, (1, 512, 8192, 384): 38403, (1, 768, 8192, 384): 38404, (1, 1024, 8192, 384): 38405, (1, 512, 4096, 448): 44803, (1, 1024, 4096, 448): 44805, (1, 512, 8192, 448): 44802, (1, 1024, 8192, 448): 44806, (1, 2048, 4096, 448): 44801, (1, 512, 4096, 512): 51203, (1, 1024, 4096, 512): 51205, (1, 512, 8192, 512): 51204, (1, 1024, 8192, 512): 51206, (1, 2048, 4096, 512): 51202}[B, N, K, D]
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': NO_PADDING_HIGHD_SHAPES[B, N, K, D], 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=NO_PADDING_HIGHD_EVAL_SHAPES, correctness=True, benchmark=True, flashlib_baseline=True, benchmark_warmup_ms=100, benchmark_ms=1000, time_triton_baseline=False)
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1.py
new file mode 100644
index 00000000..4c412191
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1.py
@@ -0,0 +1,109 @@
+"""Flash-KMeans no-padding high-D Split-K portfolio round-52 candidate.
+
+Minimum architecture: sm_100a. This additive bucket-kernel variant keeps the
+round-51 no-padding high-D denominator but changes the D448 paired route to
+launch the round-47 dual-TMEM X-reuse producer with a 160-CTA grid cap before
+the round-39 R1 packed-key reducer. D512 paired and non-D448 rows delegate to
+the round-51 portfolio children. It is not intended for sm_120a/sm_121a where
+ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from typing import Any
+from . import flash_kmeans_assign_highd_paired_xreuse_dualtmem_r47_v1 as _r47
+from . import flash_kmeans_assign_highd_splitk_blockn64_g2r4_b5a6_v1 as _g2r4
+from . import flash_kmeans_assign_no_padding_portfolio_r51_v1 as _r51
+from .._dispatch_runtime import pack_kernel_args
+ROUTE_ID = 'flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1'
+SEED_ID = 'no-padding-highd-portfolio-r52-d448-gridcap160-v1'
+VERIFY_ENV = 'LOOM_FLASH_KMEANS_NO_PADDING_PORTFOLIO_R52_D448_GRIDCAP160_VERIFY_KERNEL'
+PRODUCER_GRID_CAP_D448 = 160
+NO_PADDING_HIGHD_SHAPES = _r51.NO_PADDING_HIGHD_SHAPES
+NO_PADDING_HIGHD_EVAL_SHAPES = _r51.NO_PADDING_HIGHD_EVAL_SHAPES
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get(VERIFY_ENV)
+    if verify_kernel == 'd448_reduce':
+        return _r47.reduce_ir
+    if verify_kernel == 'd512_partial':
+        return _r47._r39._r2.partial_ir
+    if verify_kernel == 'd512_reduce':
+        return _r47._r39._r2.reduce_ir
+    if verify_kernel == 'hugek_partial':
+        return _r51._streamdep.partial_ir
+    if verify_kernel == 'hugek_reduce':
+        return _r51._streamdep.reduce_ir
+    return _r47.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_keys", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 75776, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _r51._validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _r51._is_d448_paired(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        num_n_tiles = n_points // _r47.BLOCK_N
+        k_tiles = n_clusters // _r47.MMA_BLOCK_K
+        k_slices = k_tiles // _r47.SPLITK_GROUP_K_TILES
+        if k_slices != _r47.PAIRED_K_SLICES:
+            raise ValueError(''.join([format(ROUTE_ID, ''), ' requires K_slices=', format(_r47.PAIRED_K_SLICES, ''), ', got ', format(k_slices, '')]))
+        total_work = bsz * num_n_tiles * k_slices
+        producer_grid, reducer_grid = _launch_d448_gridcap160(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters, num_n_tiles=num_n_tiles, k_tiles=k_tiles, k_slices=k_slices, total_work=total_work)
+        trace = _route_trace_d448_gridcap160(inputs, total_work=total_work, producer_grid=producer_grid, reducer_grid=reducer_grid, k_slices=k_slices)
+        return {'cluster_ids': inputs['out'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _r51.launch_for_eval(inputs)
+    trace = _wrap_r51_child_trace(inputs, child_outputs=outputs, reason='non-D448 rows delegate to the round-51 no-padding portfolio')
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _launch_d448_gridcap160(inputs: dict[str, Any], *, bsz: int, n_points: int, dim: int, n_clusters: int, num_n_tiles: int, k_tiles: int, k_slices: int, total_work: int) -> tuple[tuple[int, int, int], tuple[int, int, int]]:
+    import torch
+    partial_keys = _r47._r1._partial_key_buffer(inputs, total_work)
+    tmap_x, tmap_c = _g2r4._make_tmaps(inputs)
+    stream = torch.cuda.current_stream()
+    partial_kernel, smem_bytes, threads = _r47._loaded_partial_key_kernel()
+    partial_args = pack_kernel_args(_r47.partial_ir, x_tmap=tmap_x, c_tmap=tmap_c, c_sq=inputs['c_sq'], partial_keys=partial_keys, B=bsz, N=n_points, D=dim, K=n_clusters, num_n_tiles=num_n_tiles, K_tiles=k_tiles, K_slices=k_slices)
+    producer_grid = (min(total_work, PRODUCER_GRID_CAP_D448), 1, 1)
+    partial_kernel.launch(grid=producer_grid, block=(threads, 1, 1), args=partial_args, shared_mem=smem_bytes, stream=stream)
+    reduce_kernel, smem_bytes, threads = _r47._r39._loaded_reduce1_kernel()
+    reduce_args = [partial_keys, inputs['out'], bsz, n_points, n_clusters, num_n_tiles, k_slices]
+    reducer_grid = (min(bsz * num_n_tiles, _r47.SPLITK_GRID_CAP), 1, 1)
+    reduce_kernel.launch(grid=reducer_grid, block=(threads, 1, 1), args=reduce_args, shared_mem=smem_bytes, stream=stream)
+    return (producer_grid, reducer_grid)
+
+def _route_trace_d448_gridcap160(inputs: dict[str, Any], *, total_work: int, producer_grid: tuple[int, int, int], reducer_grid: tuple[int, int, int], k_slices: int) -> dict[str, Any]:
+    trace = _r47._route_trace_d448(inputs, total_work=total_work, producer_grid=producer_grid, reducer_grid=reducer_grid, k_slices=k_slices)
+    trace.update({'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1:launch_for_eval', 'selected_seed': SEED_ID, 'route_source': 'shape-specific-seed-portfolio', 'guard_id': 'guard_no_padding_highd_splitk_portfolio_r52_d448_gridcap160_v1', 'guard_condition': 'exact no-padding high-D bucket; D448 paired uses R47 producer gridcap160, other rows delegate to round-51', 'portfolio_selected_child': 'r47_dualtmem_xreuse_gridcap160_plus_r39_reduce1', 'reason': 'D448 paired row keeps the round-47 dual-TMEM X-reuse producer/reducer ABI but raises the producer launch cap from 128 to 160 CTAs to reduce persistent work underfeed'})
+    tile_shape = dict(trace.get('tile_shape', {}))
+    tile_shape.update({'producer_grid_cap': PRODUCER_GRID_CAP_D448, 'producer_grid_work_items_per_cta_floor': total_work // PRODUCER_GRID_CAP_D448, 'producer_grid_remainder_work_items': total_work % PRODUCER_GRID_CAP_D448})
+    trace['tile_shape'] = tile_shape
+    return trace
+
+def _wrap_r51_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any], reason: str) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    trace = dict(child_trace)
+    trace.update({'shape_key': _r51._base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1:launch_for_eval', 'selected_seed': SEED_ID, 'route_source': 'shape-specific-seed-portfolio', 'guard_id': 'guard_no_padding_highd_splitk_portfolio_r52_d448_gridcap160_v1', 'portfolio_selected_child': child_trace.get('portfolio_selected_child'), 'child_route': child_outputs.get('selected_route') or child_trace.get('selected_route'), 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'reason': reason})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160(B: int=1, N: int=2048, K: int=4096, D: int=448, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = {(1, 768, 8192, 384): 38404, (1, 512, 8192, 448): 44802, (1, 2048, 4096, 448): 44801, (1, 512, 8192, 512): 51204, (1, 2048, 4096, 512): 51202}[B, N, K, D]
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': NO_PADDING_HIGHD_SHAPES[B, N, K, D], 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=NO_PADDING_HIGHD_EVAL_SHAPES, correctness=True, benchmark=True, flashlib_baseline=True, benchmark_warmup_ms=100, benchmark_ms=1000, time_triton_baseline=False)
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1.py
new file mode 100644
index 00000000..6c2a1c8a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1.py
@@ -0,0 +1,73 @@
+"""Flash-KMeans no-padding high-D round-63 G1/R4 D512 N512 portfolio.
+
+Minimum architecture: sm_100a. This additive bucket-kernel variant keeps the
+round-52 no-padding portfolio for established rows, but routes only the
+D512 K=4096 N512 mid-K row through the round-63 G1/R4 streamdep child to
+increase producer work feed. It is not intended for sm_120a/sm_121a where
+ptxas rejects tcgen05 instructions.
+"""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+import os
+from typing import Any
+from . import flash_kmeans_assign_highd_splitk_blockn64_g1r4_streamdep_r63_v1 as _g1
+from . import flash_kmeans_assign_no_padding_portfolio_r52_d448_gridcap160_v1 as _r52
+ROUTE_ID = 'flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1'
+SEED_ID = 'no-padding-highd-portfolio-r63-g1-d512n512-v1'
+VERIFY_ENV = 'LOOM_FLASH_KMEANS_NO_PADDING_PORTFOLIO_R63_G1_D512N512_VERIFY_KERNEL'
+NO_PADDING_HIGHD_SHAPES = _r52.NO_PADDING_HIGHD_SHAPES
+NO_PADDING_HIGHD_EVAL_SHAPES = _r52.NO_PADDING_HIGHD_EVAL_SHAPES
+
+def _verify_export_ir() -> Any:
+    verify_kernel = os.environ.get(VERIFY_ENV)
+    if verify_kernel == 'g1_reduce':
+        return _g1.reduce_ir
+    if verify_kernel == 'r52':
+        return _r52.ir
+    return _g1.partial_ir
+ir = _decode_capture(_json_loads('{"__ir__": "flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1", "arg_keys": ["x_tmap", "c_tmap", "c_sq", "partial_scores", "partial_indices", "B", "N", "D", "K", "num_n_tiles", "K_tiles", "K_slices"], "cluster_dims": [1, 1, 1], "computed_smem_bytes": 43008, "constants": [], "cta_group": 1, "threads": 192}'))
+
+def launch_for_eval(inputs: dict[str, Any]) -> dict[str, Any]:
+    bsz = int(inputs['B'])
+    n_points = int(inputs['N'])
+    dim = int(inputs['D'])
+    n_clusters = int(inputs['K'])
+    _r52._r51._validate_shape(inputs, bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters)
+    if _is_g1_d512n512_target(bsz=bsz, n_points=n_points, dim=dim, n_clusters=n_clusters):
+        outputs = _g1.launch_for_eval(inputs)
+        trace = _wrap_child_trace(inputs, child_outputs=outputs, selected_child='r63_blockn64_g1r4_streamdep_child', reason='D512 N512 mid-K no-padding row uses the round-63 G1/R4 streamdep child to double producer work feed versus G2/R4')
+        return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+    outputs = _r52.launch_for_eval(inputs)
+    trace = _wrap_child_trace(inputs, child_outputs=outputs, selected_child=outputs.get('route_trace', {}).get('portfolio_selected_child', 'r52_portfolio_child'), reason='non-target rows delegate unchanged to the round-52 no-padding portfolio')
+    return {'cluster_ids': outputs['cluster_ids'], 'selected_route': ROUTE_ID, 'route_trace': trace}
+
+def _is_g1_d512n512_target(*, bsz: int, n_points: int, dim: int, n_clusters: int) -> bool:
+    return bsz == 1 and n_points == 512 and (dim == 512) and (n_clusters == 4096)
+
+def _wrap_child_trace(inputs: dict[str, Any], *, child_outputs: dict[str, Any], selected_child: str, reason: str) -> dict[str, Any]:
+    child_trace = dict(child_outputs.get('route_trace', {}))
+    trace = dict(child_trace)
+    trace.update({'shape_key': _r52._r51._base._shape_key(inputs), 'selected_route': ROUTE_ID, 'selected_entrypoint': 'loom.examples.weave.flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1:launch_for_eval', 'selected_seed': SEED_ID, 'route_source': 'shape-specific-seed-portfolio', 'guard_id': 'guard_no_padding_highd_splitk_portfolio_r63_g1_d512n512_v1', 'guard_condition': 'exact no-padding high-D bucket; only D512 K4096 N512 uses G1/R4 streamdep child, other rows delegate to R52', 'portfolio_selected_child': selected_child, 'child_route': child_outputs.get('selected_route') or child_trace.get('selected_route'), 'child_entrypoint': child_trace.get('selected_entrypoint'), 'child_guard_id': child_trace.get('guard_id'), 'child_tile_shape': child_trace.get('tile_shape'), 'reason': reason})
+    return trace
+
+def compile_and_launch_flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512(B: int=1, N: int=512, K: int=4096, D: int=512, *, benchmark: bool=False) -> dict[str, Any]:
+    import torch
+    if not torch.cuda.is_available():
+        raise RuntimeError('CUDA GPU required')
+    seed = {(1, 512, 8192, 320): 32004, (1, 1024, 8192, 320): 32005, (1, 2048, 8192, 320): 32006, (1, 512, 8192, 384): 38403, (1, 768, 8192, 384): 38404, (1, 1024, 8192, 384): 38405, (1, 512, 4096, 448): 44803, (1, 1024, 4096, 448): 44805, (1, 512, 8192, 448): 44802, (1, 1024, 8192, 448): 44806, (1, 2048, 4096, 448): 44801, (1, 512, 4096, 512): 51203, (1, 1024, 4096, 512): 51205, (1, 512, 8192, 512): 51204, (1, 1024, 8192, 512): 51206, (1, 2048, 4096, 512): 51202}[B, N, K, D]
+    torch.manual_seed(seed)
+    x = torch.randn((B, N, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    centroids = torch.randn((B, K, D), dtype=torch.bfloat16, device='cuda').contiguous()
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    out = torch.empty((B, N), dtype=torch.int32, device='cuda')
+    inputs = {'label': NO_PADDING_HIGHD_SHAPES[B, N, K, D], 'B': B, 'N': N, 'D': D, 'K': K, 'dtype': 'bfloat16', 'x': x, 'centroids': centroids, 'x_sq': x_sq, 'c_sq': c_sq, 'out': out}
+    launch_for_eval(inputs)
+    ref_dist = x_sq.unsqueeze(-1) + c_sq.unsqueeze(1) - 2.0 * torch.einsum('bnd,bkd->bnk', x.float(), centroids.float())
+    ref = ref_dist.clamp_min(0.0).argmin(dim=-1).to(torch.int32)
+    result: dict[str, Any] = {'passed': bool(torch.equal(out, ref))}
+    if benchmark:
+        from .._dispatch_runtime import evaluate
+        result['contract_eval'] = evaluate(launch_for_eval, shapes=NO_PADDING_HIGHD_EVAL_SHAPES, correctness=True, benchmark=True, flashlib_baseline=True, benchmark_warmup_ms=100, benchmark_ms=1000, time_triton_baseline=False)
+    return result
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_stream.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_stream.py
new file mode 100644
index 00000000..e390f055
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch/flash_kmeans_assign_stream.py
@@ -0,0 +1,40 @@
+"""Current-stream ownership helpers for Flash-KMeans production routes."""
+from __future__ import annotations
+from json import loads as _json_loads
+from .._dispatch_runtime import _capture_cuTensorMapEncodeTiled, _decode_capture, _import_dispatch_module, _ir_proxy
+from collections.abc import Iterator
+from contextlib import contextmanager
+from typing import Any
+
+def current_stream(inputs: dict[str, Any]) -> Any:
+    """Resolve the caller's current stream on the input tensor device."""
+    import torch
+    return torch.cuda.current_stream(device=inputs['x'].device)
+
+def stream_cache_key(inputs: dict[str, Any], *parts: int) -> tuple[int, ...]:
+    """Prefix a cache key with the exact CUDA device and stream handle."""
+    import torch
+    prepared_key = inputs.get('_flash_kmeans_assign_prepared_stream_key')
+    if prepared_key is not None:
+        device_index, stream_handle = prepared_key
+    else:
+        device = inputs['x'].device
+        device_index = getattr(device, 'index', None)
+        if device_index is None:
+            device_index = torch.cuda.current_device()
+        stream_handle = current_stream(inputs).cuda_stream
+    return (int(device_index), int(stream_handle), *(int(part) for part in parts))
+
+@contextmanager
+def bind_current_stream(inputs: dict[str, Any]) -> Iterator[Any]:
+    """Keep a production child pipeline on the caller's entry stream."""
+    import torch
+    device = inputs['x'].device
+    stream = current_stream(inputs)
+    device_index = getattr(device, 'index', None)
+    current_device = torch.cuda.current_device()
+    if device_index is None or int(device_index) == int(current_device):
+        yield stream
+        return
+    with torch.cuda.device(device), torch.cuda.stream(stream):
+        yield stream
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_runtime.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_runtime.py
new file mode 100644
index 00000000..c57622d1
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_runtime.py
@@ -0,0 +1,1151 @@
+from __future__ import annotations
+_KERNEL_ALIAS_BY_IR_NAME = {'flash_kmeans_assign_lowdim_pack_e50c_v1': 'dispatch_kernel_0000', 'flash_kmeans_assign_lowdim_e50c_v1': 'dispatch_kernel_0001', 'flash_kmeans_assign_cleanroom_tcgen05_v10': 'dispatch_kernel_0002', 'flash_kmeans_assign_d160_pad192_pack_f9b2_v1': 'dispatch_kernel_0004', 'flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1': 'dispatch_kernel_0005', 'flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1': 'dispatch_kernel_0008', 'flash_kmeans_assign_highd_splitd_6fcf_v1': 'dispatch_kernel_0009', 'flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1': 'dispatch_kernel_0011', 'flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1': 'dispatch_kernel_0012', 'flash_kmeans_assign_microdim_pack_6cd2_v1': 'dispatch_kernel_0013', 'flash_kmeans_assign_microdim_6cd2_v1': 'dispatch_kernel_0014', 'flash_kmeans_assign_gap_pad_pack_v1': 'dispatch_kernel_0015', 'flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1': 'dispatch_kernel_0016', 'flash_kmeans_assign_cleanroom_tcgen05_v15': 'dispatch_kernel_0048', 'flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1': 'dispatch_kernel_0059', 'flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1': 'dispatch_kernel_0060', 'flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1': 'dispatch_kernel_0101', 'flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1': 'dispatch_kernel_0109', 'flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1': 'dispatch_kernel_0118', 'flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1': 'dispatch_kernel_0119', 'flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1': 'dispatch_kernel_0121', 'flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1': 'dispatch_kernel_0122', 'flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4': 'dispatch_kernel_0126', 'flash_kmeans_assign_microdim_raw_tma_08f9_v1': 'dispatch_kernel_0129', 'flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1': 'dispatch_kernel_0156', 'flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4': 'dispatch_kernel_0229', 'flash_kmeans_assign_d288_exactd_a532_v1': 'dispatch_kernel_0236', 'flash_kmeans_assign_d288_splitk_cta_0438_v1_partial': 'dispatch_kernel_0237', 'flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce': 'dispatch_kernel_0238', 'flash_kmeans_assign_d480_splitk_partial_d32k256_v1': 'dispatch_kernel_0258', 'flash_kmeans_assign_d480_splitk_reduce_d32k256_v1': 'dispatch_kernel_0259', 'flash_kmeans_assign_highd_splitk_partial_8de8_v1': 'dispatch_kernel_0277', 'flash_kmeans_assign_highd_splitk_reduce_8de8_v1': 'dispatch_kernel_0278', 'flash_kmeans_assign_microdim_direct_9c0d_v1': 'dispatch_kernel_0332', 'flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2': 'dispatch_kernel_0347', 'flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1': 'dispatch_kernel_0353', 'flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1': 'dispatch_kernel_0354', 'flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1': 'dispatch_kernel_0355'}
+_KERNEL_ALIAS_BY_REQUEST = {'{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_lowdim_pack_e50c_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0000', '{"computed_smem_bytes":100352,"constants":[],"ir_name":"flash_kmeans_assign_lowdim_e50c_v1","kwargs":{"smem_bytes":100352,"validate":false},"threads":192}': 'dispatch_kernel_0001', '{"computed_smem_bytes":100352,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_v10","kwargs":{"smem_bytes":100352,"validate":false},"threads":192}': 'dispatch_kernel_0002', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_d160_pad192_pack_f9b2_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0004', '{"computed_smem_bytes":149504,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1","kwargs":{"smem_bytes":149504,"validate":false},"threads":192}': 'dispatch_kernel_0005', '{"computed_smem_bytes":198656,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1","kwargs":{"smem_bytes":198656,"validate":false},"threads":192}': 'dispatch_kernel_0008', '{"computed_smem_bytes":51200,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitd_6fcf_v1","kwargs":{"smem_bytes":51200,"validate":false},"threads":192}': 'dispatch_kernel_0009', '{"computed_smem_bytes":43008,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1","kwargs":{"smem_bytes":43008,"validate":false},"threads":192}': 'dispatch_kernel_0011', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0012', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_microdim_pack_6cd2_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0013', '{"computed_smem_bytes":51200,"constants":[],"ir_name":"flash_kmeans_assign_microdim_6cd2_v1","kwargs":{"smem_bytes":51200,"validate":false},"threads":192}': 'dispatch_kernel_0014', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_gap_pad_pack_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0015', '{"computed_smem_bytes":51200,"constants":[],"ir_name":"flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1","kwargs":{"smem_bytes":51200,"validate":false},"threads":192}': 'dispatch_kernel_0016', '{"computed_smem_bytes":133120,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_v15","kwargs":{"smem_bytes":133120,"validate":false},"threads":192}': 'dispatch_kernel_0048', '{"computed_smem_bytes":43008,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1","kwargs":{"smem_bytes":43008,"validate":false},"threads":192}': 'dispatch_kernel_0059', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0060', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0101', '{"computed_smem_bytes":198656,"constants":[],"ir_name":"flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1","kwargs":{"smem_bytes":198656,"validate":false},"threads":192}': 'dispatch_kernel_0109', '{"computed_smem_bytes":75776,"constants":[],"ir_name":"flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1","kwargs":{"smem_bytes":75776,"validate":false},"threads":192}': 'dispatch_kernel_0118', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":64}': 'dispatch_kernel_0119', '{"computed_smem_bytes":43008,"constants":[],"ir_name":"flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1","kwargs":{"smem_bytes":43008,"validate":false},"threads":192}': 'dispatch_kernel_0121', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":128}': 'dispatch_kernel_0122', '{"computed_smem_bytes":23552,"constants":[],"ir_name":"flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4","kwargs":{"smem_bytes":23552,"validate":false},"threads":192}': 'dispatch_kernel_0126', '{"computed_smem_bytes":52224,"constants":[],"ir_name":"flash_kmeans_assign_microdim_raw_tma_08f9_v1","kwargs":{"smem_bytes":52224,"validate":false},"threads":192}': 'dispatch_kernel_0129', '{"computed_smem_bytes":46592,"constants":[],"ir_name":"flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1","kwargs":{"smem_bytes":46592,"validate":false},"threads":256}': 'dispatch_kernel_0156', '{"computed_smem_bytes":22528,"constants":[],"ir_name":"flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4","kwargs":{"smem_bytes":22528,"validate":false},"threads":192}': 'dispatch_kernel_0229', '{"computed_smem_bytes":26624,"constants":[],"ir_name":"flash_kmeans_assign_d288_exactd_a532_v1","kwargs":{"smem_bytes":26624,"validate":false},"threads":192}': 'dispatch_kernel_0236', '{"computed_smem_bytes":26624,"constants":[],"ir_name":"flash_kmeans_assign_d288_splitk_cta_0438_v1_partial","kwargs":{"smem_bytes":26624,"validate":false},"threads":192}': 'dispatch_kernel_0237', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce","kwargs":{"smem_bytes":0,"validate":false},"threads":128}': 'dispatch_kernel_0238', '{"computed_smem_bytes":22528,"constants":[],"ir_name":"flash_kmeans_assign_d480_splitk_partial_d32k256_v1","kwargs":{"smem_bytes":22528,"validate":false},"threads":192}': 'dispatch_kernel_0258', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_d480_splitk_reduce_d32k256_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":256}': 'dispatch_kernel_0259', '{"computed_smem_bytes":51200,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_partial_8de8_v1","kwargs":{"smem_bytes":51200,"validate":false},"threads":192}': 'dispatch_kernel_0277', '{"computed_smem_bytes":0,"constants":[],"ir_name":"flash_kmeans_assign_highd_splitk_reduce_8de8_v1","kwargs":{"smem_bytes":0,"validate":false},"threads":128}': 'dispatch_kernel_0278', '{"computed_smem_bytes":51200,"constants":[],"ir_name":"flash_kmeans_assign_microdim_direct_9c0d_v1","kwargs":{"smem_bytes":51200,"validate":false},"threads":192}': 'dispatch_kernel_0332', '{"computed_smem_bytes":26624,"constants":[],"ir_name":"flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2","kwargs":{"smem_bytes":26624,"validate":false},"threads":192}': 'dispatch_kernel_0347', '{"computed_smem_bytes":29696,"constants":[],"ir_name":"flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1","kwargs":{"smem_bytes":29696,"validate":false},"threads":160}': 'dispatch_kernel_0353', '{"computed_smem_bytes":43008,"constants":[],"ir_name":"flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1","kwargs":{"smem_bytes":43008,"validate":false},"threads":256}': 'dispatch_kernel_0354', '{"computed_smem_bytes":35840,"constants":[],"ir_name":"flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1","kwargs":{"smem_bytes":35840,"validate":false},"threads":416}': 'dispatch_kernel_0355'}
+
+import ctypes
+import importlib
+import json
+import threading
+import sys
+from contextlib import contextmanager
+from contextvars import ContextVar
+from dataclasses import dataclass, field, replace as _dataclass_replace
+from importlib import resources
+from types import SimpleNamespace
+
+from .kernels import get_kernel
+from ._runtime import launch_stream_context, resolve_launch_defaults
+
+
+_DISPATCH_LAUNCH_OPTIONS = ContextVar("dispatch_launch_options", default=(None, None))
+
+
+@contextmanager
+def dispatch_launch_options(*, stream=None, timeout_ms=None):
+    token = _DISPATCH_LAUNCH_OPTIONS.set((stream, timeout_ms))
+    try:
+        yield
+    finally:
+        _DISPATCH_LAUNCH_OPTIONS.reset(token)
+
+
+def _resolved_launch_options(stream, timeout_ms):
+    default_stream, default_timeout_ms = _DISPATCH_LAUNCH_OPTIONS.get()
+    return (
+        default_stream if stream is None else stream,
+        default_timeout_ms if timeout_ms is None else timeout_ms,
+    )
+
+
+_active_launch_capture = ContextVar("flashlib_active_launch_capture", default=None)
+_pending_tensor_map_recipe = ContextVar("flashlib_pending_tensor_map_recipe", default=None)
+_launch_capture_prepare_lock = threading.RLock()
+
+
+def _replace(value, /, **changes):
+    replacer = getattr(value, "__replace__", None)
+    if callable(replacer):
+        return replacer(**changes)
+    return _dataclass_replace(value, **changes)
+
+
+dc = SimpleNamespace(replace=_replace)
+
+
+def _import_dispatch_module(short_name):
+    return importlib.import_module(f"{__package__}._dispatch.{short_name}")
+
+
+_DISPATCH_OWNED_DICT_SUFFIXES = ("CACHE", "SCRATCH", "INPUTS", "OUTPUTS", "FLAGS")
+
+
+def _cache_value_references_owned_object(value, owned_ids, seen):
+    identity = id(value)
+    if identity in owned_ids:
+        return True
+    if identity in seen:
+        return False
+    seen.add(identity)
+    if isinstance(value, dict):
+        return any(
+            _cache_value_references_owned_object(item, owned_ids, seen)
+            for pair in value.items()
+            for item in pair
+        )
+    if isinstance(value, (tuple, list, set, frozenset)):
+        return any(
+            _cache_value_references_owned_object(item, owned_ids, seen)
+            for item in value
+        )
+    return False
+
+
+def release_dispatch_caches(owned_objects):
+    '''Clear route-owned tensor dictionaries after a prepared sequence binds.
+
+    Generated dispatch modules may temporarily cache tensor-map descriptors and
+    workspaces while a route is prepared.  A bound ``PreparedKernelSequence``
+    retains every CUDA argument, so those module globals are no longer owners.
+    To avoid clearing dispatch registries or scalar statistics, this contract
+    is limited to dict-valued, private, uppercase names with an explicit
+    workspace/cache suffix below this generated package's ``_dispatch``
+    namespace.
+    '''
+
+    prefix = f"{__package__}._dispatch."
+    owned_ids = {
+        id(value)
+        for value in owned_objects
+        if callable(getattr(value, "data_ptr", None))
+    }
+    if not owned_ids:
+        return 0
+    cleared = 0
+    for module_name, module in tuple(sys.modules.items()):
+        if module is None or not module_name.startswith(prefix):
+            continue
+        for name, value in tuple(vars(module).items()):
+            if (
+                name.startswith("_")
+                and name.endswith(_DISPATCH_OWNED_DICT_SUFFIXES)
+                and name.isupper()
+                and isinstance(value, dict)
+            ):
+                removed = False
+                for key, item in tuple(value.items()):
+                    if _cache_value_references_owned_object(item, owned_ids, set()):
+                        value.pop(key, None)
+                        removed = True
+                cleared += int(removed)
+    return cleared
+
+
+def _decode_capture(value):
+    if isinstance(value, dict) and "__ir__" in value:
+        return _ir_proxy(
+            value["__ir__"],
+            value.get("threads", 256),
+            value.get("computed_smem_bytes", 0),
+            value.get("cluster_dims", (1, 1, 1)),
+            value.get("cta_group", 1),
+            value.get("constants", ()),
+            value.get("arg_keys", ()),
+        )
+    if isinstance(value, dict) and set(value) == {"__kernel__"}:
+        return DispatchKernel(value["__kernel__"])
+    if isinstance(value, dict) and set(value) == {"__kernel_source__"}:
+        return value["__kernel_source__"]
+    if isinstance(value, dict) and set(value) == {"__tuple__"}:
+        return tuple(_decode_capture(item) for item in value["__tuple__"])
+    if isinstance(value, dict) and set(value) == {"__dict_items__"}:
+        return {
+            _decode_capture(key): _decode_capture(item)
+            for key, item in value["__dict_items__"]
+        }
+    if isinstance(value, dict):
+        return {key: _decode_capture(item) for key, item in value.items()}
+    if isinstance(value, list):
+        return [_decode_capture(item) for item in value]
+    return value
+
+
+@dataclass(frozen=True)
+class _IRProxy:
+    symbol: str
+    threads: int = 256
+    computed_smem_bytes: int = 0
+    constants: tuple = ()
+    grid: object = None
+    arg_keys: tuple = ()
+
+    def __replace__(self, /, **changes):
+        values = {
+            "symbol": self.symbol,
+            "threads": self.threads,
+            "computed_smem_bytes": self.computed_smem_bytes,
+            "constants": self.constants,
+            "grid": self.grid,
+            "arg_keys": self.arg_keys,
+        }
+        unknown = sorted(set(changes) - set(values))
+        if unknown:
+            raise TypeError(f"unknown frozen WeaveIR field(s): {unknown}")
+        values.update(changes)
+        return _IRProxy(**values)
+
+
+def _ir_proxy(
+    name, threads=256, computed_smem_bytes=0, cluster_dims=(1, 1, 1),
+    cta_group=1, constants=(), arg_keys=(),
+):
+    return _IRProxy(
+        name.rpartition(":")[2], int(threads), int(computed_smem_bytes),
+        tuple(tuple(item) for item in constants),
+        SimpleNamespace(cluster_dims=tuple(cluster_dims), cta_group=int(cta_group)),
+        tuple(arg_keys),
+    )
+
+
+def pack_kernel_args(schedule, /, **bindings):
+    expected = tuple(schedule.arg_keys)
+    missing = sorted(set(expected) - set(bindings))
+    unexpected = sorted(set(bindings) - set(expected))
+    if missing or unexpected:
+        raise ValueError(
+            f"kernel argument bindings do not match frozen WeaveIR.args: "
+            f"missing={missing!r}, unexpected={unexpected!r}"
+        )
+    return [bindings[key] for key in expected]
+
+
+class PreparedKernelSequence:
+    def __init__(
+        self,
+        launches,
+        result,
+        input_bindings=(),
+        result_template=None,
+        tensor_map_bindings=(),
+        input_alias_topology=(),
+        stream=None,
+    ):
+        if not launches:
+            raise RuntimeError("prepared semantic route did not capture a CUDA launch")
+        self._launches = tuple(launches)
+        self._result = result
+        self._input_bindings = tuple(tuple(bindings) for bindings in input_bindings)
+        if self._input_bindings and len(self._input_bindings) != len(self._launches):
+            raise RuntimeError("prepared semantic route has corrupt input bindings")
+        self._result_template = result_template
+        self._input_alias_topology = tuple(
+            tuple(group) for group in input_alias_topology
+        )
+        direct_input_keys = {key for bindings in self._input_bindings for _, key in bindings}
+        self._direct_input_keys = tuple(sorted(direct_input_keys))
+        self._tensor_map_bindings = _own_tensor_map_bindings(
+            self._launches,
+            tuple(tensor_map_bindings),
+            stream=stream,
+        )
+        self._bound_input_keys = tuple(
+            sorted(direct_input_keys | {binding.input_key for binding in self._tensor_map_bindings})
+        )
+        self._input_references_retained = True
+
+    @property
+    def launch_count(self):
+        return len(self._launches)
+
+    @property
+    def bound_input_keys(self):
+        return self._bound_input_keys
+
+    def rebind_inputs(
+        self,
+        inputs,
+        *,
+        stream=None,
+        materialize_result=True,
+        preserve_prepared_stream=False,
+        retain_input_references=True,
+    ):
+        if not isinstance(materialize_result, bool):
+            raise TypeError("materialize_result must be a bool")
+        if not isinstance(preserve_prepared_stream, bool):
+            raise TypeError("preserve_prepared_stream must be a bool")
+        if not isinstance(retain_input_references, bool):
+            raise TypeError("retain_input_references must be a bool")
+        if preserve_prepared_stream and stream is not None:
+            raise ValueError("preserve_prepared_stream requires stream=None")
+        if materialize_result and not retain_input_references:
+            raise ValueError(
+                "materialize_result requires retain_input_references so the result remains valid"
+            )
+        if not any(self._input_bindings) and not self._tensor_map_bindings:
+            raise RuntimeError(
+                "prepared semantic route has no input bindings; "
+                "capture it with capture_kernel_launches(inputs=...)"
+            )
+        missing = sorted(set(self.bound_input_keys) - set(inputs))
+        if missing:
+            raise KeyError(f"missing prepared semantic input binding(s): {missing!r}")
+        _validate_public_tensor_alias_topology(inputs, self._input_alias_topology)
+        pointer_values = None
+        inputs_already_scrubbed = False
+        if not retain_input_references:
+            pointer_values = {}
+            for key in self._direct_input_keys:
+                value = inputs[key]
+                data_ptr = getattr(value, "data_ptr", None)
+                if not callable(data_ptr):
+                    raise TypeError(f"prepared CUDA tensor binding {key!r} is not tensor-like")
+                pointer_values[key] = int(data_ptr())
+            inputs_already_scrubbed = not self._input_references_retained
+        with launch_stream_context(stream):
+            for binding in self._tensor_map_bindings:
+                binding.refresh(inputs[binding.input_key])
+            for launch, bindings in zip(self._launches, self._input_bindings, strict=True):
+                launch.rebind_tensor_arguments(
+                    bindings,
+                    inputs,
+                    stream=stream,
+                    preserve_stream=preserve_prepared_stream,
+                    retain_inputs=retain_input_references,
+                    pointer_values=pointer_values,
+                    inputs_already_scrubbed=inputs_already_scrubbed,
+                )
+        self._input_references_retained = retain_input_references
+        # Stateful public runtimes may own the output independently of the
+        # semantic return tree.  Let those callers skip recursively rebuilding
+        # a result they will not observe while retaining the default behavior
+        # for normal prepared-dispatch callers.
+        if materialize_result and self._result_template is not None:
+            self._result = _materialize_result_template(self._result_template, inputs)
+        return self
+
+    def _rebind_stream_bound_scrubbed_inputs(self, inputs, *, stream):
+        '''Rebind one validated fixed-stream runtime slot without generic checks.
+
+        This private path is valid only after a stateful wrapper selected the
+        sequence through a cache key containing the complete public pointer
+        alias topology, recorded every caller-owned tensor, and scrubbed the
+        sequence's caller references. Public prepared callers continue to use
+        :meth:`rebind_inputs` and its full validation.
+        '''
+        if self._input_references_retained:
+            raise RuntimeError(
+                "fixed-stream semantic rebind requires scrubbed input references"
+            )
+        if stream is None:
+            raise ValueError("fixed-stream semantic rebind requires an explicit stream")
+        pointer_values = {}
+        for key in self._direct_input_keys:
+            value = inputs[key]
+            data_ptr = getattr(value, "data_ptr", None)
+            if not callable(data_ptr):
+                raise TypeError(f"prepared CUDA tensor binding {key!r} is not tensor-like")
+            pointer_values[key] = int(data_ptr())
+        for binding in self._tensor_map_bindings:
+            binding.rebind_stream_bound(inputs[binding.input_key], stream=stream)
+        for launch, bindings in zip(self._launches, self._input_bindings, strict=True):
+            launch.rebind_tensor_arguments(
+                bindings,
+                inputs,
+                preserve_stream=True,
+                retain_inputs=False,
+                pointer_values=pointer_values,
+                inputs_already_scrubbed=True,
+            )
+        return self
+
+    def release_bound_inputs(self):
+        '''Drop caller tensor references after their launch stream was recorded.'''
+        if self._input_references_retained:
+            for launch, bindings in zip(self._launches, self._input_bindings, strict=True):
+                keepalive = list(launch._keepalive)
+                for index, _key in bindings:
+                    value = keepalive[index]
+                    data_ptr = getattr(value, "data_ptr", None)
+                    if callable(data_ptr):
+                        keepalive[index] = int(data_ptr())
+                launch._keepalive = tuple(keepalive)
+            self._input_references_retained = False
+        self._result = None
+
+    def record_stream(self, stream):
+        '''Tie every tensor launch argument, including private scratch, to a stream.'''
+        if stream is None:
+            raise ValueError("prepared semantic record_stream requires an explicit stream")
+        seen = set()
+        for launch in self._launches:
+            for value in launch._keepalive:
+                identity = id(value)
+                record_stream = getattr(value, "record_stream", None)
+                if identity not in seen and callable(record_stream):
+                    seen.add(identity)
+                    record_stream(stream)
+        # Variant-bank descriptor tensors are slot-owned but only the active
+        # variant appears in a launch keepalive; record every variant so a
+        # non-synchronizing release stays allocator-safe.
+        for binding in self._tensor_map_bindings:
+            for value in binding.variants.values():
+                identity = id(value)
+                record_stream = getattr(value, "record_stream", None)
+                if identity not in seen and callable(record_stream):
+                    seen.add(identity)
+                    record_stream(stream)
+
+    def _finish_rebind(self, result):
+        self._result = result
+        return self
+
+    def __call__(self, _inputs=None, *, stream=None, timeout_ms=None):
+        last = len(self._launches) - 1
+        for index, launch in enumerate(self._launches):
+            launch.launch(stream=stream, timeout_ms=timeout_ms if index == last else None)
+        return self._result
+
+
+class KernelLaunchCapture:
+    def __init__(self, *, stream=None, arch=None, inputs=None, rebind=None):
+        if rebind is not None and not isinstance(rebind, PreparedKernelSequence):
+            raise TypeError("rebind must be a PreparedKernelSequence")
+        if inputs is not None and rebind is not None:
+            raise ValueError("inputs and rebind are mutually exclusive capture modes")
+        if rebind is not None:
+            raise RuntimeError(
+                "capture(rebind=...) is unsupported because an in-place topology "
+                "update cannot be transactional; capture a new sequence instead"
+            )
+        self.stream = stream
+        self.arch = arch
+        self._launches = []
+        self._input_bindings = []
+        self._input_key_by_identity = _public_tensor_input_identities(inputs)
+        self._input_key_by_pointer = _public_tensor_input_pointers(inputs)
+        self._input_alias_topology = _public_tensor_alias_topology(inputs)
+        self._tensor_map_bindings = {}
+        self._route_caches_released = False
+        self._rebind = rebind
+        self._rebind_index = 0
+        self.host_data_reads = 0
+
+    @property
+    def host_data_dependent(self):
+        '''True when the route read device memory while its kernels were only
+        being recorded — its host branch decisions cannot be frozen.'''
+        return self.host_data_reads > 0
+
+    @property
+    def rebinding(self):
+        return self._rebind is not None
+
+    def add(self, launch):
+        if self.rebinding:
+            raise RuntimeError("rebind capture requires launch topology, not a newly prepared launch")
+        self._launches.append(launch)
+        self._input_bindings.append(
+            ()
+            if not self._input_key_by_identity
+            else tuple(
+                (index, self._input_key_by_identity[id(arg)])
+                for index, arg in enumerate(launch._keepalive)
+                if id(arg) in self._input_key_by_identity
+            )
+        )
+        for arg in launch._keepalive:
+            recipe = getattr(arg, "_loom_tensor_map_recipe", None)
+            if recipe is None:
+                continue
+            source_pointer = int(recipe[2])
+            input_key = self._input_key_by_pointer.get(source_pointer)
+            if input_key is None:
+                continue
+            self._tensor_map_bindings.setdefault(
+                id(arg),
+                _TensorMapBinding(
+                    input_key=input_key,
+                    tensor=arg,
+                    recipe=tuple(recipe),
+                    pointer=source_pointer,
+                ),
+            )
+
+    def add_kernel_launch(
+        self,
+        exported,
+        *,
+        mode,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem,
+        stream,
+        cluster_dims=None,
+    ):
+        resolved_arch, resolved_stream, _ = resolve_launch_defaults(
+            arch=self.arch,
+            stream=self.stream if self.stream is not None else stream,
+            timeout_ms=None,
+        )
+        with launch_stream_context(resolved_stream):
+            kernel = exported.compile(arch=resolved_arch, options=["--use_fast_math"])
+            kwargs = {
+                "grid": grid,
+                "block": block,
+                "args": tuple(args),
+                "arg_types": arg_types,
+                "shared_mem": shared_mem,
+                "stream": resolved_stream,
+            }
+            if self.rebinding:
+                if self._rebind_index >= self._rebind.launch_count:
+                    raise RuntimeError(
+                        "prepared semantic route launch-count mismatch: "
+                        f"expected {self._rebind.launch_count}, captured more launches"
+                    )
+                prepared = self._rebind._launches[self._rebind_index]
+                if mode == "cluster":
+                    kernel.rebind_launch_cluster(
+                        prepared, cluster_dims=cluster_dims, **kwargs
+                    )
+                elif mode == "cooperative":
+                    kernel.rebind_launch_cooperative(prepared, **kwargs)
+                elif mode == "regular":
+                    kernel.rebind_launch(prepared, **kwargs)
+                else:
+                    raise RuntimeError(f"unsupported captured launch mode: {mode!r}")
+                self._rebind_index += 1
+                return
+            if mode == "cluster":
+                prepared = kernel.prepare_launch_cluster(
+                    cluster_dims=cluster_dims, **kwargs
+                )
+            elif mode == "cooperative":
+                prepared = kernel.prepare_launch_cooperative(**kwargs)
+            elif mode == "regular":
+                prepared = kernel.prepare_launch(**kwargs)
+            else:
+                raise RuntimeError(f"unsupported captured launch mode: {mode!r}")
+            self.add(prepared)
+
+    def bind(self, result):
+        if self.rebinding:
+            if self._rebind_index != self._rebind.launch_count:
+                raise RuntimeError(
+                    "prepared semantic route launch-count mismatch: "
+                    f"expected {self._rebind.launch_count}, captured {self._rebind_index}"
+                )
+            return self._rebind._finish_rebind(result)
+        result_template = _capture_result_template(result, self._input_key_by_identity)
+        route_cache_owned_objects = self._route_cache_owned_objects()
+        sequence = PreparedKernelSequence(
+            self._launches,
+            result,
+            self._input_bindings,
+            result_template,
+            tuple(self._tensor_map_bindings.values()),
+            self._input_alias_topology,
+            self.stream,
+        )
+        self.release_route_caches(route_cache_owned_objects)
+        return sequence
+
+    def _route_cache_owned_objects(self):
+        return tuple(arg for launch in self._launches for arg in launch._keepalive)
+
+    def release_route_caches(self, owned_objects=None):
+        if self._route_caches_released:
+            return 0
+        if owned_objects is None:
+            owned_objects = self._route_cache_owned_objects()
+        self._route_caches_released = True
+        return release_dispatch_caches(tuple(owned_objects))
+
+
+@dataclass(frozen=True)
+class _BoundInputResult:
+    key: str
+
+
+@dataclass
+class _TensorMapBinding:
+    input_key: str
+    tensor: object
+    recipe: tuple
+    pointer: int
+    pointer_carriers: tuple = ()
+    staging_slots: list = field(default_factory=list)
+    variants: dict = field(default_factory=dict)
+    variant_capacity: int = 4
+
+    def __post_init__(self):
+        if not self.variants:
+            self.variants[self.pointer] = self.tensor
+
+    def _acquire_staging_slot(self, torch):
+        for slot in self.staging_slots:
+            if slot.event.query():
+                return slot
+        slot = _TensorMapStagingSlot(
+            host_buffer=torch.empty(128, dtype=torch.uint8, pin_memory=True),
+            event=torch.cuda.Event(blocking=False, interprocess=False),
+        )
+        self.staging_slots.append(slot)
+        return slot
+
+    def _encode_into(self, pointer, tensor, *, stream=None):
+        from cuda.bindings import driver
+        import torch
+
+        arguments = list(self.recipe)
+        arguments[2] = pointer
+        err, tmap = driver.cuTensorMapEncodeTiled(*arguments)
+        if err != 0:
+            raise RuntimeError(f"cuTensorMapEncodeTiled rebind failed: CUresult={err}")
+        slot = self._acquire_staging_slot(torch)
+        ctypes.memmove(
+            int(slot.host_buffer.data_ptr()),
+            int(tmap.getPtr()),
+            128,
+        )
+        tensor.copy_(slot.host_buffer, non_blocking=True)
+        slot.event.record(torch.cuda.current_stream() if stream is None else stream)
+        self.tensor = tensor
+        self.pointer = pointer
+        self.recipe = tuple(arguments)
+        tensor._loom_tensor_map_recipe = self.recipe
+
+    def _activate(self, pointer, tensor):
+        descriptor_pointer = int(tensor.data_ptr())
+        for carrier in self.pointer_carriers:
+            carrier.value = descriptor_pointer
+        arguments = list(self.recipe)
+        arguments[2] = pointer
+        self.tensor = tensor
+        self.pointer = pointer
+        self.recipe = tuple(arguments)
+        tensor._loom_tensor_map_recipe = self.recipe
+
+    def refresh(self, source, *, stream=None):
+        pointer = int(source.data_ptr())
+        if pointer == self.pointer:
+            return
+        self._encode_into(pointer, self.tensor, stream=stream)
+        # Generic public rebinding mutates the active descriptor in place.
+        # Reset the private variant bank so no stale pointer key can name it.
+        self.variants.clear()
+        self.variants[pointer] = self.tensor
+
+    def rebind_stream_bound(self, source, *, stream):
+        if stream is None:
+            raise ValueError("stream-bound tensor-map rebind requires an explicit stream")
+        pointer = int(source.data_ptr())
+        if pointer == self.pointer:
+            return
+        cached = self.variants.pop(pointer, None)
+        if cached is not None:
+            # LRU recency: re-insert the hit so eviction removes the
+            # least-recently-activated variant, not the newest one.
+            self.variants[pointer] = cached
+            self._activate(pointer, cached)
+            return
+
+        import torch
+
+        if len(self.variants) < self.variant_capacity:
+            tensor = torch.empty_like(self.tensor)
+            record_stream = getattr(tensor, "record_stream", None)
+            if callable(record_stream):
+                record_stream(stream)
+        else:
+            tensor = self.variants.pop(next(iter(self.variants)))
+        self._encode_into(pointer, tensor, stream=stream)
+        self.variants[pointer] = tensor
+        self._activate(pointer, tensor)
+
+
+@dataclass
+class _TensorMapStagingSlot:
+    host_buffer: object
+    event: object
+
+
+def _own_tensor_map_bindings(launches, bindings, *, stream):
+    '''Clone cached descriptors and patch every launch to slot-owned storage.'''
+
+    if not bindings:
+        return ()
+    owned_by_identity = {}
+    owned_bindings = []
+    with launch_stream_context(stream):
+        for binding in bindings:
+            original = binding.tensor
+            owned = original.clone()
+            owned._loom_tensor_map_recipe = binding.recipe
+            metadata = getattr(original, "_loom_tma_metadata", None)
+            if metadata is not None:
+                owned._loom_tma_metadata = metadata
+            owned_by_identity[id(original)] = owned
+            pointer_carriers = tuple(
+                launch._packed._prevent_gc[index]
+                for launch in launches
+                for index, arg in enumerate(launch._keepalive)
+                if id(arg) == id(original)
+            )
+            if not pointer_carriers or any(
+                type(carrier) is not ctypes.c_void_p for carrier in pointer_carriers
+            ):
+                raise RuntimeError("captured tensor-map binding has invalid pointer carriers")
+            owned_bindings.append(
+                _TensorMapBinding(
+                    input_key=binding.input_key,
+                    tensor=owned,
+                    recipe=binding.recipe,
+                    pointer=binding.pointer,
+                    pointer_carriers=pointer_carriers,
+                )
+            )
+        for launch in launches:
+            replacements = {
+                index: owned_by_identity[id(arg)]
+                for index, arg in enumerate(launch._keepalive)
+                if id(arg) in owned_by_identity
+            }
+            if replacements:
+                launch.rebind_arguments(replacements, stream=stream)
+    return tuple(owned_bindings)
+
+
+def _public_tensor_input_identities(inputs):
+    if inputs is None:
+        return {}
+    if not hasattr(inputs, "items"):
+        raise TypeError("capture inputs must be a mapping")
+    identities = {}
+    for key, value in inputs.items():
+        if (
+            isinstance(key, str)
+            and not key.startswith("_")
+            and callable(getattr(value, "data_ptr", None))
+        ):
+            identities.setdefault(id(value), key)
+    return identities
+
+
+def _public_tensor_input_pointers(inputs):
+    if inputs is None:
+        return {}
+    pointers = {}
+    for key, value in inputs.items():
+        if (
+            isinstance(key, str)
+            and not key.startswith("_")
+            and callable(getattr(value, "data_ptr", None))
+        ):
+            pointers.setdefault(int(value.data_ptr()), key)
+    return pointers
+
+
+def _public_tensor_alias_topology(inputs, keys=None):
+    '''Return the complete pointer-equality partition of public tensor inputs.'''
+
+    if inputs is None:
+        return ()
+    if not hasattr(inputs, "items"):
+        raise TypeError("capture inputs must be a mapping")
+    if keys is None:
+        selected = [
+            key
+            for key, value in inputs.items()
+            if (
+                isinstance(key, str)
+                and not key.startswith("_")
+                and callable(getattr(value, "data_ptr", None))
+            )
+        ]
+    else:
+        selected = list(keys)
+        missing = sorted(set(selected) - set(inputs))
+        if missing:
+            raise KeyError(f"missing prepared semantic alias binding(s): {missing!r}")
+        invalid = sorted(
+            key
+            for key in selected
+            if not callable(getattr(inputs[key], "data_ptr", None))
+        )
+        if invalid:
+            raise TypeError(
+                f"prepared semantic alias binding(s) must be tensor-like: {invalid!r}"
+            )
+    groups = {}
+    for key in selected:
+        groups.setdefault(int(inputs[key].data_ptr()), []).append(key)
+    return tuple(sorted(tuple(sorted(group)) for group in groups.values()))
+
+
+def _validate_public_tensor_alias_topology(inputs, expected):
+    if not expected:
+        return
+    keys = tuple(key for group in expected for key in group)
+    actual = _public_tensor_alias_topology(inputs, keys)
+    if actual != expected:
+        raise RuntimeError(
+            "prepared semantic public tensor alias topology changed: "
+            f"expected {expected!r}, got {actual!r}; capture a new sequence"
+        )
+
+
+def _capture_result_template(value, input_key_by_identity):
+    key = input_key_by_identity.get(id(value))
+    if key is not None:
+        return _BoundInputResult(key)
+    if isinstance(value, tuple):
+        return tuple(_capture_result_template(item, input_key_by_identity) for item in value)
+    if isinstance(value, list):
+        return [_capture_result_template(item, input_key_by_identity) for item in value]
+    if isinstance(value, dict):
+        return {
+            key: _capture_result_template(item, input_key_by_identity)
+            for key, item in value.items()
+        }
+    return value
+
+
+def _materialize_result_template(value, inputs):
+    if isinstance(value, _BoundInputResult):
+        return inputs[value.key]
+    if isinstance(value, tuple):
+        return tuple(_materialize_result_template(item, inputs) for item in value)
+    if isinstance(value, list):
+        return [_materialize_result_template(item, inputs) for item in value]
+    if isinstance(value, dict):
+        return {key: _materialize_result_template(item, inputs) for key, item in value.items()}
+    return value
+
+
+@contextmanager
+def capture_kernel_launches(*, stream=None, arch=None, inputs=None, rebind=None):
+    import torch
+
+    with _launch_capture_prepare_lock:
+        if _active_launch_capture.get() is not None:
+            raise RuntimeError("nested kernel launch capture is not supported")
+        capture = KernelLaunchCapture(stream=stream, arch=arch, inputs=inputs, rebind=rebind)
+        token = _active_launch_capture.set(capture)
+        # Captured launches are marshalled, not run, so any device read the
+        # route performs mid-traversal (for example an ``overflow_flag.item()``
+        # certification) observes memory its recorded kernels never wrote.
+        # Interpose ``torch.Tensor.item`` for the capture's duration and count
+        # CUDA-tensor reads; a nonzero count marks the capture
+        # ``host_data_dependent`` so the plan builder keeps that signature on
+        # the per-call launcher instead of freezing an unreproducible branch.
+        # Captures are serialized by ``_launch_capture_prepare_lock``, so the
+        # process-global interpose cannot nest. ``.item()`` is the only device
+        # read the vendored dispatch modules perform on their launch paths.
+        # Torch test doubles without a ``Tensor.item`` skip the interpose.
+        original_tensor_item = getattr(getattr(torch, "Tensor", None), "item", None)
+
+        def _observed_item(tensor):
+            if getattr(tensor, "is_cuda", False):
+                capture.host_data_reads += 1
+            return original_tensor_item(tensor)
+
+        if original_tensor_item is not None:
+            torch.Tensor.item = _observed_item
+        try:
+            if stream is None:
+                yield capture
+            else:
+                with torch.cuda.stream(stream):
+                    yield capture
+        finally:
+            if original_tensor_item is not None:
+                torch.Tensor.item = original_tensor_item
+            capture.release_route_caches()
+            _active_launch_capture.reset(token)
+
+
+class DispatchKernel:
+    def __init__(self, alias, symbol=None):
+        self.exported = get_kernel(alias)
+        self.symbol = symbol or self.exported.spec.symbol
+
+    def __enter__(self):
+        return self
+
+    def __exit__(self, *args):
+        return None
+
+    def launch(self, *, grid, block, args, shared_mem=0, stream=None, timeout_ms=None, **kwargs):
+        stream, timeout_ms = _resolved_launch_options(stream, timeout_ms)
+        capture = _active_launch_capture.get()
+        if capture is not None:
+            capture.add_kernel_launch(
+                self.exported,
+                mode="regular",
+                grid=grid,
+                block=block,
+                args=args,
+                arg_types=self.exported.arg_types,
+                shared_mem=shared_mem,
+                stream=stream,
+            )
+            return
+        self.exported.launch(
+            *args, grid=grid, block=block, shared_mem=shared_mem, stream=stream,
+            timeout_ms=timeout_ms, options=["--use_fast_math"],
+        )
+
+    def launch_cluster(
+        self, *, grid, block, args, cluster_dims, shared_mem=0, stream=None,
+        timeout_ms=None, **kwargs
+    ):
+        stream, timeout_ms = _resolved_launch_options(stream, timeout_ms)
+        capture = _active_launch_capture.get()
+        if capture is not None:
+            capture.add_kernel_launch(
+                self.exported,
+                mode="cluster",
+                grid=grid,
+                block=block,
+                args=args,
+                arg_types=self.exported.arg_types,
+                cluster_dims=cluster_dims,
+                shared_mem=shared_mem,
+                stream=stream,
+            )
+            return
+        arch, stream, timeout_ms = resolve_launch_defaults(
+            arch=None,
+            stream=stream,
+            timeout_ms=timeout_ms,
+        )
+        with launch_stream_context(stream):
+            kernel = self.exported.compile(arch=arch, options=["--use_fast_math"])
+            kernel.launch_cluster(
+                grid=grid, block=block, args=tuple(args),
+                arg_types=self.exported.arg_types,
+                cluster_dims=cluster_dims, shared_mem=shared_mem, stream=stream,
+                timeout_ms=timeout_ms,
+            )
+
+    def launch_cooperative(
+        self, *, grid, block, args, shared_mem=0, stream=None, timeout_ms=None, **kwargs
+    ):
+        stream, timeout_ms = _resolved_launch_options(stream, timeout_ms)
+        capture = _active_launch_capture.get()
+        if capture is not None:
+            capture.add_kernel_launch(
+                self.exported,
+                mode="cooperative",
+                grid=grid,
+                block=block,
+                args=args,
+                arg_types=self.exported.arg_types,
+                shared_mem=shared_mem,
+                stream=stream,
+            )
+            return
+        arch, stream, timeout_ms = resolve_launch_defaults(
+            arch=None,
+            stream=stream,
+            timeout_ms=timeout_ms,
+        )
+        with launch_stream_context(stream):
+            kernel = self.exported.compile(arch=arch, options=["--use_fast_math"])
+            kernel.launch_cooperative(
+                grid=grid, block=block, args=tuple(args),
+                arg_types=self.exported.arg_types,
+                shared_mem=shared_mem, stream=stream, timeout_ms=timeout_ms,
+            )
+
+    def prepare_launch(self, **kwargs):
+        return _PreparedDispatchLaunch(self.launch, kwargs)
+
+    def prepare_launch_cluster(self, **kwargs):
+        return _PreparedDispatchLaunch(self.launch_cluster, kwargs)
+
+    def prepare_launch_cooperative(self, **kwargs):
+        return _PreparedDispatchLaunch(self.launch_cooperative, kwargs)
+
+
+class _PreparedDispatchLaunch:
+    def __init__(self, launch, kwargs):
+        self._launch = launch
+        self._kwargs = dict(kwargs)
+
+    def launch(self, timeout_ms=None):
+        kwargs = dict(self._kwargs)
+        if timeout_ms is not None:
+            kwargs["timeout_ms"] = timeout_ms
+        return self._launch(**kwargs)
+
+
+CUDAKernel = DispatchKernel
+
+
+def compile_cuda(source, **kwargs):
+    return source
+
+
+def detect_gpu_arch():
+    import torch
+    major, minor = torch.cuda.get_device_capability()
+    return f"sm_{major}{minor}a"
+
+
+def _cuda_include_dirs():
+    return []
+
+
+def arch_flag_for_cc(major, minor):
+    sm = int(major) * 10 + int(minor)
+    return f"sm_{sm}a" if sm >= 90 else f"sm_{sm}"
+
+
+def _capture_cuTensorMapEncodeTiled(*arguments):
+    '''Encode a tensor map while retaining a pointer-rebind recipe.'''
+    from cuda.bindings import driver
+
+    result = driver.cuTensorMapEncodeTiled(*arguments)
+    if result[0] == 0:
+        _pending_tensor_map_recipe.set(tuple(arguments))
+    else:
+        _pending_tensor_map_recipe.set(None)
+    return result
+
+
+def _tmap_to_device(tmap, metadata=None):
+    import torch
+    del metadata
+    recipe = _pending_tensor_map_recipe.get()
+    _pending_tensor_map_recipe.set(None)
+    host_ptr = tmap.getPtr()
+    raw = bytes((ctypes.c_ubyte * 128).from_address(host_ptr))
+    host = torch.frombuffer(bytearray(raw), dtype=torch.uint8)
+    device = torch.empty(128, dtype=torch.uint8, device="cuda")
+    device.copy_(host)
+    if recipe is not None:
+        device._loom_tensor_map_recipe = recipe
+    return device
+
+
+class Swizzle:
+    # Standalone spellings used only by stripped TMA metadata helpers.
+    SZ_128B = "128B"
+    SZ_64B = "64B"
+    SZ_32B = "32B"
+    NONE = "none"
+
+
+class TensorMapMetadata:
+    # Compatibility carrier; frozen launch packing needs no metadata.
+    def __init__(self, **values):
+        self.__dict__.update(values)
+
+
+def attach_tma_metadata(tensor, metadata):
+    tensor._loom_tensor_map_metadata = metadata
+    return tensor
+
+
+def create_tensor_map(data_ptr, dim0, dim1, box0, box1, stride1_bytes):
+    '''Create a rank-2 BF16 128B-swizzled map with a rebind recipe.'''
+    from cuda.bindings import driver
+
+    err, tmap = _capture_cuTensorMapEncodeTiled(
+        driver.CUtensorMapDataType.CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
+        2,
+        data_ptr,
+        [driver.cuuint64_t(dim0), driver.cuuint64_t(dim1)],
+        [driver.cuuint64_t(stride1_bytes)],
+        [driver.cuuint32_t(box0), driver.cuuint32_t(box1)],
+        [driver.cuuint32_t(1), driver.cuuint32_t(1)],
+        driver.CUtensorMapInterleave.CU_TENSOR_MAP_INTERLEAVE_NONE,
+        driver.CUtensorMapSwizzle.CU_TENSOR_MAP_SWIZZLE_128B,
+        driver.CUtensorMapL2promotion.CU_TENSOR_MAP_L2_PROMOTION_NONE,
+        driver.CUtensorMapFloatOOBfill.CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE,
+    )
+    if err != 0:
+        raise RuntimeError(f"cuTensorMapEncodeTiled (2D BF16) failed: CUresult={err}")
+    return _tmap_to_device(tmap)
+
+
+def _create_tensor_map_3d(data_ptr, global_height, shared_height, width, block_width, swizzle):
+    from cuda.bindings import driver
+    atoms = {"128B": 64, "64B": 32, "32B": 16}
+    swizzles = {
+        "128B": driver.CUtensorMapSwizzle.CU_TENSOR_MAP_SWIZZLE_128B,
+        "64B": driver.CUtensorMapSwizzle.CU_TENSOR_MAP_SWIZZLE_64B,
+        "32B": driver.CUtensorMapSwizzle.CU_TENSOR_MAP_SWIZZLE_32B,
+    }
+    try:
+        atom = atoms[swizzle]
+        swizzle_value = swizzles[swizzle]
+    except KeyError as exc:
+        raise ValueError(f"unsupported 3D tensor-map swizzle: {swizzle}") from exc
+    err, tmap = _capture_cuTensorMapEncodeTiled(
+        driver.CUtensorMapDataType.CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
+        3,
+        data_ptr,
+        [driver.cuuint64_t(atom), driver.cuuint64_t(global_height), driver.cuuint64_t(width // atom)],
+        [driver.cuuint64_t(width * 2), driver.cuuint64_t(atom * 2)],
+        [driver.cuuint32_t(atom), driver.cuuint32_t(shared_height), driver.cuuint32_t(block_width // atom)],
+        [driver.cuuint32_t(1), driver.cuuint32_t(1), driver.cuuint32_t(1)],
+        driver.CUtensorMapInterleave.CU_TENSOR_MAP_INTERLEAVE_NONE,
+        swizzle_value,
+        driver.CUtensorMapL2promotion.CU_TENSOR_MAP_L2_PROMOTION_NONE,
+        driver.CUtensorMapFloatOOBfill.CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE,
+    )
+    if err != 0:
+        raise RuntimeError(f"cuTensorMapEncodeTiled failed: CUresult={err}")
+    return _tmap_to_device(tmap)
+
+
+def create_tensor_map_3d(data_ptr, global_height, shared_height, width, block_width):
+    return _create_tensor_map_3d(data_ptr, global_height, shared_height, width, block_width, "128B")
+
+
+def create_tensor_map_3d_64b(data_ptr, global_height, shared_height, width, block_width):
+    return _create_tensor_map_3d(data_ptr, global_height, shared_height, width, block_width, "64B")
+
+
+def create_tensor_map_3d_32b(data_ptr, global_height, shared_height, width, block_width):
+    return _create_tensor_map_3d(data_ptr, global_height, shared_height, width, block_width, "32B")
+
+
+def generate_kernel(ir, **kwargs):
+    request_key = json.dumps(
+        {
+            "ir_name": ir.symbol,
+            "constants": [[str(name), value] for name, value in ir.constants],
+            "threads": int(ir.threads),
+            "computed_smem_bytes": int(ir.computed_smem_bytes),
+            "kwargs": kwargs,
+        },
+        sort_keys=True, separators=(",", ":"), default=repr,
+    )
+    alias = _KERNEL_ALIAS_BY_REQUEST.get(request_key)
+    if alias is None:
+        alias = _KERNEL_ALIAS_BY_IR_NAME.get(ir.symbol)
+    if alias is None:
+        raise RuntimeError(f"uncaptured dispatcher specialization for {ir.symbol}")
+    return alias
+
+
+def generate_kernel_bundle(*args, **kwargs):
+    raise RuntimeError("uncaptured dispatcher bundle specialization")
+
+
+def _all_shapes():
+    package = __package__ or __name__.rpartition(".")[0]
+    text = resources.files(package).joinpath("_dispatch_shapes.json").read_text(encoding="utf-8")
+    return json.loads(text)
+
+
+class _CanonicalShapes:
+    '''Lazy contract-shape view backed by the exported plan ledger.'''
+
+    def __iter__(self):
+        return iter(_all_shapes())
+
+    def __len__(self):
+        return len(_all_shapes())
+
+    def __getitem__(self, index):
+        return _all_shapes()[index]
+
+
+CANONICAL_SHAPES = _CanonicalShapes()
+
+
+def select_named_shapes(labels):
+    labels = [labels] if isinstance(labels, str) else list(labels)
+    by_label = {row["label"]: row for row in _all_shapes()}
+    return [by_label[label] for label in labels]
+
+
+def evaluate(*args, **kwargs):
+    raise RuntimeError("Cake eval harness is not part of the standalone runtime")
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_shapes.json b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_shapes.json
new file mode 100644
index 00000000..cd982b94
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_dispatch_shapes.json
@@ -0,0 +1,4458 @@
+[
+  {
+    "label": "d895_expanded_heldout_neighborhood_d80_b2_n2176_k1024_d80",
+    "params": {
+      "B": 2,
+      "D": 80,
+      "K": 1024,
+      "N": 2176,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.7696,
+      "evolution_flashlib_ms": 0.402944,
+      "evolution_kernel_ms": 0.176928,
+      "evolution_speedup": 2.2774,
+      "evolution_tflops": 4.0301,
+      "route": "lowdim_e50c_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_miss_fallback_d128_b1_n1408_k512_d128",
+    "params": {
+      "B": 1,
+      "D": 128,
+      "K": 512,
+      "N": 1408,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.53,
+      "evolution_flashlib_ms": 0.348175,
+      "evolution_kernel_ms": 0.144544,
+      "evolution_speedup": 2.4088,
+      "evolution_tflops": 1.2768,
+      "route": "aligned_v10_fallback",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_forced_fallback_d128_b1_n1664_k256_d128",
+    "params": {
+      "B": 1,
+      "D": 128,
+      "K": 256,
+      "N": 1664,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.3924,
+      "evolution_flashlib_ms": 0.277904,
+      "evolution_kernel_ms": 0.142032,
+      "evolution_speedup": 1.9566,
+      "evolution_tflops": 0.7678,
+      "route": "aligned_v10_fallback",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_boundary_d144_b1_n128_k256_d144",
+    "params": {
+      "B": 1,
+      "D": 144,
+      "K": 256,
+      "N": 128,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.0205,
+      "evolution_flashlib_ms": 0.459647,
+      "evolution_kernel_ms": 0.1664,
+      "evolution_speedup": 2.7623,
+      "evolution_tflops": 0.0567,
+      "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_tail_divisibility_d176_b1_n1152_k512_d176",
+    "params": {
+      "B": 1,
+      "D": 176,
+      "K": 512,
+      "N": 1152,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.5253,
+      "evolution_flashlib_ms": 0.395232,
+      "evolution_kernel_ms": 0.174944,
+      "evolution_speedup": 2.2592,
+      "evolution_tflops": 1.1868,
+      "route": "d144_d160_d176_pad192_tail_repair_f9b2_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_guard_overlap_d192_b1_n1024_k768_d192",
+    "params": {
+      "B": 1,
+      "D": 192,
+      "K": 768,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.6618,
+      "evolution_flashlib_ms": 0.45632,
+      "evolution_kernel_ms": 0.17168,
+      "evolution_speedup": 2.658,
+      "evolution_tflops": 1.759,
+      "route": "d192_paired_repeated_mma_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_random_legal_d320_b1_n1280_k512_d320",
+    "params": {
+      "B": 1,
+      "D": 320,
+      "K": 512,
+      "N": 1280,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.826,
+      "evolution_flashlib_ms": 0.507759,
+      "evolution_kernel_ms": 0.152496,
+      "evolution_speedup": 3.3297,
+      "evolution_tflops": 2.7504,
+      "route": "highd_splitd_single_tile_6fcf_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_request_specific_d448_b1_n1280_k1024_d448",
+    "params": {
+      "B": 1,
+      "D": 448,
+      "K": 1024,
+      "N": 1280,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.7411,
+      "evolution_flashlib_ms": 0.674512,
+      "evolution_kernel_ms": 0.173743,
+      "evolution_speedup": 3.8822,
+      "evolution_tflops": 6.7594,
+      "route": "highd_splitd_single_tile_6fcf_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d895_expanded_request_specific_d512_splitk_b1_n512_k8192_d512",
+    "params": {
+      "B": 1,
+      "D": 512,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1375,
+      "evolution_flashlib_ms": 31.230383,
+      "evolution_kernel_ms": 0.257392,
+      "evolution_speedup": 121.3339,
+      "evolution_tflops": 16.6865,
+      "route": "flash_kmeans_assign_no_padding_portfolio_r63_g1_d512n512_v1",
+      "source": "expanded9"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_paired_b2_n4096_k1024_d16",
+    "params": {
+      "B": 2,
+      "D": 16,
+      "K": 1024,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.8529,
+      "evolution_flashlib_ms": 0.314751,
+      "evolution_kernel_ms": 0.175568,
+      "evolution_speedup": 1.7928,
+      "evolution_tflops": 1.529,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_fallback_b3_n2432_k512_d16",
+    "params": {
+      "B": 3,
+      "D": 16,
+      "K": 512,
+      "N": 2432,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.4098,
+      "evolution_flashlib_ms": 0.291712,
+      "evolution_kernel_ms": 0.127456,
+      "evolution_speedup": 2.2887,
+      "evolution_tflops": 0.9379,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_small_b4_n1024_k512_d16",
+    "params": {
+      "B": 4,
+      "D": 16,
+      "K": 512,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1836,
+      "evolution_flashlib_ms": 0.365599,
+      "evolution_kernel_ms": 0.141568,
+      "evolution_speedup": 2.5825,
+      "evolution_tflops": 0.474,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d16_large_b8_n32768_k512_d16",
+    "params": {
+      "B": 8,
+      "D": 16,
+      "K": 512,
+      "N": 32768,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 13.0308,
+      "evolution_flashlib_ms": 0.3296,
+      "evolution_kernel_ms": 0.234416,
+      "evolution_speedup": 1.406,
+      "evolution_tflops": 18.322,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_hugek_b1_n512_k8192_d32",
+    "params": {
+      "B": 1,
+      "D": 32,
+      "K": 8192,
+      "N": 512,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.1923,
+      "evolution_flashlib_ms": 1.396063,
+      "evolution_kernel_ms": 0.224064,
+      "evolution_speedup": 6.2306,
+      "evolution_tflops": 1.198,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_paired_b2_n4096_k1024_d32",
+    "params": {
+      "B": 2,
+      "D": 32,
+      "K": 1024,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.6899,
+      "evolution_flashlib_ms": 0.317696,
+      "evolution_kernel_ms": 0.176672,
+      "evolution_speedup": 1.7982,
+      "evolution_tflops": 3.0388,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_fallback_b3_n2432_k512_d32",
+    "params": {
+      "B": 3,
+      "D": 32,
+      "K": 512,
+      "N": 2432,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.8475,
+      "evolution_flashlib_ms": 0.28208,
+      "evolution_kernel_ms": 0.133824,
+      "evolution_speedup": 2.1078,
+      "evolution_tflops": 1.7865,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d32_small_b4_n1024_k512_d32",
+    "params": {
+      "B": 4,
+      "D": 32,
+      "K": 512,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.3716,
+      "evolution_flashlib_ms": 0.361167,
+      "evolution_kernel_ms": 0.139583,
+      "evolution_speedup": 2.5875,
+      "evolution_tflops": 0.9616,
+      "route": "microdim_hybrid_9c0d_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d64_paired_b2_n4096_k1024_d64",
+    "params": {
+      "B": 2,
+      "D": 64,
+      "K": 1024,
+      "N": 4096,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 3.3518,
+      "evolution_flashlib_ms": 0.320352,
+      "evolution_kernel_ms": 0.070272,
+      "evolution_speedup": 4.5587,
+      "evolution_tflops": 15.2798,
+      "route": "d64_direct_single64_1p2gap_9f2a_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d64_fallback_b3_n2432_k512_d64",
+    "params": {
+      "B": 3,
+      "D": 64,
+      "K": 512,
+      "N": 2432,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 1.6742,
+      "evolution_flashlib_ms": 0.2856,
+      "evolution_kernel_ms": 0.067552,
+      "evolution_speedup": 4.2279,
+      "evolution_tflops": 7.0783,
+      "route": "d64_direct_single64_1p2gap_9f2a_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d64_small_b4_n1024_k512_d64",
+    "params": {
+      "B": 4,
+      "D": 64,
+      "K": 512,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.6741,
+      "evolution_flashlib_ms": 0.398223,
+      "evolution_kernel_ms": 0.06736,
+      "evolution_speedup": 5.9119,
+      "evolution_tflops": 3.9851,
+      "route": "d64_direct_single64_1p2gap_9f2a_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d64_large_b8_n32768_k512_d64",
+    "params": {
+      "B": 8,
+      "D": 64,
+      "K": 512,
+      "N": 32768,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 34.8042,
+      "evolution_flashlib_ms": 0.493615,
+      "evolution_kernel_ms": 0.128672,
+      "evolution_speedup": 3.8362,
+      "evolution_tflops": 133.5168,
+      "route": "d64_direct_single64_1p2gap_9f2a_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d80_paired_b1_n2048_k1024_d80",
+    "params": {
+      "B": 1,
+      "D": 80,
+      "K": 1024,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.8736,
+      "evolution_flashlib_ms": 0.384112,
+      "evolution_kernel_ms": 0.176896,
+      "evolution_speedup": 2.1714,
+      "evolution_tflops": 1.8968,
+      "route": "lowdim_e50c_v1",
+      "source": "full95"
+    },
+    "recorded": {},
+    "runtime_coverage": true
+  },
+  {
+    "label": "d80_small_b2_n1024_k512_d80",
+    "params": {
+      "B": 2,
+      "D": 80,
+      "K": 512,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "evolution_flashlib_equiv_tflops": 0.4431,
+      "evolution_flashlib_ms": 0.378656,
+      "evolution_kernel_ms": 0.173552,
+      "evolution_speedup": 2.1818,
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+    "label": "adjacent_d9d5_d480_heldout_highk_b3_n1024_k4096_d480",
+    "params": {
+      "B": 3,
+      "D": 480,
+      "K": 4096,
+      "N": 1024,
+      "dtype": "bfloat16",
+      "seed": 9548001,
+      "source": "heldout_neighborhood"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 6.283,
+      "evolution_flashlib_ms": 1.92259,
+      "evolution_kernel_ms": 0.297632,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 6.4596,
+      "evolution_tflops": 40.5857
+    }
+  },
+  {
+    "label": "adjacent_ef00_d480_lowk_boundary_b3_n3200_k256_d480",
+    "params": {
+      "B": 3,
+      "D": 480,
+      "K": 256,
+      "N": 3200,
+      "dtype": "bfloat16",
+      "seed": 9004801,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 7.059,
+      "evolution_flashlib_ms": 0.334224,
+      "evolution_kernel_ms": 0.18192,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 1.8372,
+      "evolution_tflops": 12.9689
+    }
+  },
+  {
+    "label": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480",
+    "params": {
+      "B": 4,
+      "D": 480,
+      "K": 512,
+      "N": 1664,
+      "dtype": "bfloat16",
+      "seed": 6848001,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 6.0602,
+      "evolution_flashlib_ms": 0.539839,
+      "evolution_kernel_ms": 0.18536,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 2.9124,
+      "evolution_tflops": 17.6497
+    }
+  },
+  {
+    "label": "post_d895_d480_b4_n8192_k1024_d480",
+    "params": {
+      "B": 4,
+      "D": 480,
+      "K": 1024,
+      "N": 8192,
+      "dtype": "bfloat16",
+      "seed": 248002,
+      "source": "new_high_gap"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 43.8869,
+      "evolution_flashlib_ms": 0.733983,
+      "evolution_kernel_ms": 0.24,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 3.0583,
+      "evolution_tflops": 134.2177
+    }
+  },
+  {
+    "label": "adjacent_c44f_d480_boundary_b5_n2048_k512_d480",
+    "params": {
+      "B": 5,
+      "D": 480,
+      "K": 512,
+      "N": 2048,
+      "dtype": "bfloat16",
+      "seed": 4448001,
+      "source": "guard_boundary"
+    },
+    "recorded": {
+      "evolution_flashlib_equiv_tflops": 10.031,
+      "evolution_flashlib_ms": 0.501759,
+      "evolution_kernel_ms": 0.185136,
+      "evolution_route": "gap_pad_to_supported_seed_v1",
+      "evolution_speedup": 2.7102,
+      "evolution_tflops": 27.1863
+    }
+  }
+]
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_launch_plan.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_launch_plan.py
new file mode 100644
index 00000000..8a99cc8c
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_launch_plan.py
@@ -0,0 +1,540 @@
+from __future__ import annotations
+
+from collections.abc import Callable
+from dataclasses import dataclass, field
+from functools import lru_cache
+from typing import Any
+
+from ._dispatch import flash_kmeans_assign_dispatcher as _root
+from ._dispatch_runtime import _import_dispatch_module, dispatch_launch_options
+
+_WEAVE_PREFIX = 'loom.examples.weave.'
+_ROOT_MODULE = 'flash_kmeans_assign_dispatcher'
+_ROOT_CALLABLE = 'launch_for_eval'
+_EXACT_LAUNCH_SPECS = {}
+
+
+@dataclass(frozen=True)
+class RouteDecision:
+    """Resolved semantic route with a launcher that can be reused directly."""
+
+    route_id: str
+    launch_entrypoint: str
+    launcher: Callable[[dict[str, Any]], Any] = field(repr=False, compare=False)
+    exact_contract: bool = False
+
+    def launch(
+        self,
+        inputs: dict[str, Any],
+        *,
+        stream: Any = None,
+        timeout_ms: float | None = None,
+    ) -> Any:
+        with dispatch_launch_options(stream=stream, timeout_ms=timeout_ms):
+            return self.launcher(inputs)
+
+
+def _route_key(inputs: dict[str, Any]) -> tuple[int, int, int, int, int, str, bool, bool]:
+    dtype = str(inputs.get("dtype", "bfloat16"))
+    if dtype.startswith("torch."):
+        dtype = dtype[6:]
+    return (
+        *(int(inputs[name]) for name in ("B", "Q", "M", "D", "K")),
+        dtype,
+        bool(inputs.get("self_search", False)),
+        bool(inputs.get("force_fallback", False)),
+    )
+
+
+@lru_cache(maxsize=None)
+def _load_launcher(module_name: str, callable_name: str) -> Callable[[dict[str, Any]], Any]:
+    module = _import_dispatch_module(module_name)
+    launcher = getattr(module, callable_name, None)
+    if not callable(launcher):
+        raise RuntimeError(f"resolved dispatcher launcher is not callable: {module_name}:{callable_name}")
+    return launcher
+
+
+@lru_cache(maxsize=None)
+def _make_decision(
+    route_id: str,
+    module_name: str,
+    callable_name: str,
+    exact_contract: bool,
+) -> RouteDecision:
+    return RouteDecision(
+        route_id=route_id,
+        launch_entrypoint=f"{_WEAVE_PREFIX}{module_name}:{callable_name}",
+        launcher=_load_launcher(module_name, callable_name),
+        exact_contract=exact_contract,
+    )
+
+
+def _entrypoint_spec(entrypoint: object) -> tuple[str, str] | None:
+    if not isinstance(entrypoint, str):
+        return None
+    module_name, separator, callable_name = entrypoint.partition(":")
+    if not separator or not module_name.startswith(_WEAVE_PREFIX) or not callable_name.isidentifier():
+        return None
+    return module_name.removeprefix(_WEAVE_PREFIX), callable_name
+
+
+def _generic_decision(inputs: dict[str, Any]) -> RouteDecision:
+    info_fn = getattr(_root, "route_info", None)
+    info = dict(info_fn(inputs)) if callable(info_fn) else {}
+    route_id = info.get("selected_route", info.get("route"))
+    if route_id is None:
+        select_route = getattr(_root, "selected_route", None)
+        route_id = select_route(inputs) if callable(select_route) else _ROOT_CALLABLE
+    # ``resolved_launch_entrypoint`` is an explicit launch contract and may
+    # bypass the root. ``selected_entrypoint`` is seed provenance: it can name
+    # a narrower module whose own guards would silently miss for this
+    # signature (the K11 prefix route reports its K64 seed there, and
+    # launching the seed with K=11 inputs falls through to a slower exact
+    # parent). Signatures without a launch contract go through the root
+    # dispatcher, which reproduces the frozen guard cascade exactly.
+    spec = _entrypoint_spec(info.get("resolved_launch_entrypoint"))
+    if spec is None:
+        spec = (_ROOT_MODULE, _ROOT_CALLABLE)
+    return _make_decision(str(route_id), *spec, False)
+
+
+def resolve_route(inputs: dict[str, Any]) -> RouteDecision:
+    """Resolve once; exact exported shapes never re-enter the root dispatcher."""
+
+    spec = _EXACT_LAUNCH_SPECS.get(_route_key(inputs))
+    if spec is None:
+        return _generic_decision(inputs)
+    return _make_decision(*spec, True)
+
+
+class LaunchPlan:
+    """Per-signature resolved execution state for the exported hot path.
+
+    Migration step 2 of ``PLAN_BASED_EXPORT_RUNTIME.md``: the guard cascade
+    (``resolve_route`` plus one captured dispatcher traversal) runs exactly
+    once, at construction. A hot call overwrites the recorded 8-byte pointer
+    carriers in place, refreshes device tensor-map descriptors only when a
+    bound pointer actually changed, and submits the already-marshalled
+    launches on their construction-time stream — no re-marshalling, no
+    per-launch stream query, no dispatcher re-entry.
+    """
+
+    __slots__ = (
+        "route",
+        "sequence",
+        "torch_stream",
+        "stream_handle",
+        "_launches",
+        "_pointer_writers",
+        "_tma_bindings",
+    )
+
+    def __init__(self, route: RouteDecision, sequence: Any, *, torch_stream: Any, stream_handle: int):
+        launches = tuple(sequence._launches)
+        input_bindings = tuple(sequence._input_bindings)
+        if input_bindings and len(input_bindings) != len(launches):
+            raise RuntimeError("launch plan capture has corrupt input bindings")
+        writers: dict[str, list[Any]] = {}
+        for launch, bindings in zip(launches, input_bindings):
+            carriers = launch._packed._prevent_gc
+            for index, key in bindings:
+                writers.setdefault(key, []).append(carriers[index])
+        self.route = route
+        self.sequence = sequence
+        self.torch_stream = torch_stream
+        self.stream_handle = int(stream_handle)
+        self._launches = launches
+        self._pointer_writers = tuple((key, tuple(items)) for key, items in writers.items())
+        self._tma_bindings = tuple(sequence._tensor_map_bindings)
+
+    @property
+    def launch_count(self) -> int:
+        return len(self._launches)
+
+    @property
+    def bound_input_keys(self) -> tuple[str, ...]:
+        direct = {key for key, _carriers in self._pointer_writers}
+        derived = {binding.input_key for binding in self._tma_bindings}
+        return tuple(sorted(direct | derived))
+
+    def bind_hot(self, bindings: dict[str, Any]) -> None:
+        """Refresh tensor maps and overwrite bound pointer carriers in place.
+
+        This is the host-side half of a hot call. Callers that enqueue their
+        own support launches between the plan's pointer binding and its
+        kernel submission (the KNN-build fused row norms) must call this
+        BEFORE those launches: a fresh-pointer tensor-map re-encode costs
+        host time, and paying it after any kernel is already enqueued turns
+        that host time into a GPU inter-kernel gap.
+
+        Tensor maps go through the per-pointer variant bank: a pointer the
+        bank has seen keeps its device-resident descriptor, so re-activating
+        it is a handful of carrier writes with no ``cuTensorMapEncodeTiled``,
+        no pinned-staging refresh, and no H2D copy. The plan's signature slot
+        is stream-keyed and alias-keyed by the caller, which is the safety
+        contract ``rebind_stream_bound`` requires.
+        """
+
+        for binding in self._tma_bindings:
+            binding.rebind_stream_bound(bindings[binding.input_key], stream=self.torch_stream)
+        for key, carriers in self._pointer_writers:
+            pointer = bindings[key].data_ptr()
+            for carrier in carriers:
+                carrier.value = pointer
+
+    def submit_hot(self, *, timeout_ms: float | None = None) -> None:
+        """Submit every prepared launch on the plan's construction stream."""
+
+        launches = self._launches
+        last_index = len(launches) - 1
+        for index, launch in enumerate(launches):
+            launch.launch(stream=None, timeout_ms=timeout_ms if index == last_index else None)
+
+    def launch_hot(self, bindings: dict[str, Any], *, timeout_ms: float | None = None) -> None:
+        """Patch bound pointer carriers from ``bindings`` and submit every launch."""
+
+        self.bind_hot(bindings)
+        self.submit_hot(timeout_ms=timeout_ms)
+
+    def record_stream(self, stream: Any) -> None:
+        """Tie every plan-held launch argument to ``stream`` before release."""
+
+        self.sequence.record_stream(stream)
+
+
+class PerCallRoutePlan:
+    """Per-signature plan for routes whose host logic reads device results.
+
+    Capture observed the route reading GPU memory (for example an
+    ``overflow_flag.item()`` certification) while its kernels were only being
+    recorded, so a frozen launch list cannot reproduce the route's per-call
+    branch decisions — freezing would bake whichever branch the capture-time
+    garbage selected. These signatures keep the generic per-call launcher:
+    route resolution stays cached and the guard cascade still ran exactly
+    once, but every hot call re-executes the resolved route's host program.
+    Device-side repair (Migration step 3) makes such routes replayable.
+    """
+
+    __slots__ = (
+        "route",
+        "torch_stream",
+        "stream_handle",
+        "launch_count",
+        "host_data_reads",
+        "_static_inputs",
+        "_pending_bindings",
+    )
+
+    def __init__(
+        self,
+        route: RouteDecision,
+        *,
+        torch_stream: Any,
+        stream_handle: int,
+        static_inputs: dict[str, Any],
+        launch_count: int,
+        host_data_reads: int,
+    ):
+        self.route = route
+        self.torch_stream = torch_stream
+        self.stream_handle = int(stream_handle)
+        self.launch_count = int(launch_count)
+        self.host_data_reads = int(host_data_reads)
+        self._static_inputs = dict(static_inputs)
+        self._pending_bindings = None
+
+    def bind_hot(self, bindings: dict[str, Any]) -> None:
+        """Stage this call's tensor bindings for ``submit_hot``.
+
+        Mirrors ``LaunchPlan``'s two-phase hot call so callers with support
+        launches use one code path. The caller's per-signature slot lock
+        serializes bind/submit pairs on a plan instance.
+        """
+
+        self._pending_bindings = dict(bindings)
+
+    def submit_hot(self, *, timeout_ms: float | None = None) -> None:
+        """Re-execute the resolved route with the staged tensor bindings."""
+
+        bindings = self._pending_bindings
+        if bindings is None:
+            raise RuntimeError("PerCallRoutePlan.submit_hot requires a preceding bind_hot")
+        self._pending_bindings = None
+        self.launch_hot(bindings, timeout_ms=timeout_ms)
+
+    def launch_hot(self, bindings: dict[str, Any], *, timeout_ms: float | None = None) -> None:
+        """Re-execute the resolved route with this call's tensor bindings.
+
+        The torch stream context keeps the route's tensor operations (scratch
+        fills, the certification read-back) ordered with its kernel launches
+        on the plan's stream, exactly as the live evaluation path runs it.
+        """
+
+        import torch
+
+        inputs = dict(self._static_inputs)
+        inputs.update(bindings)
+        with torch.cuda.stream(self.torch_stream):
+            self.route.launch(inputs, stream=self.torch_stream, timeout_ms=timeout_ms)
+
+    def record_stream(self, stream: Any) -> None:
+        """Per-call plans hold no launch arguments; nothing to record."""
+
+
+def build_launch_plan(
+    inputs: dict[str, Any],
+    *,
+    stream: Any,
+    arch: str,
+    validate_result: Callable[[Any, dict[str, Any]], None] | None = None,
+    route: Any = None,
+) -> LaunchPlan | PerCallRoutePlan:
+    """Run the guard cascade once and freeze its launches into a LaunchPlan.
+
+    This is the per-signature slow path; ``resolve_route`` remains the single
+    source of routing truth. ``validate_result(result, inputs)`` must raise
+    when the resolved route's outputs cannot be retargeted by pointer
+    rebinding (for example outputs that are not caller-owned tensors).
+    Routes whose host logic read device memory during capture resolve to a
+    ``PerCallRoutePlan`` instead of a frozen launch list.
+
+    ``route`` accepts an already-resolved decision from a sibling routing
+    layer with the same contract (``route_id``/``launch_entrypoint``/
+    ``exact_contract`` plus ``launch(inputs, stream=..., timeout_ms=...)``),
+    for workloads whose exact-contract table lives outside this module (the
+    KNN-build direct-manifest resolver). It must come from that workload's
+    frozen routing surface, never from re-guessing the cascade.
+    """
+
+    from ._dispatch_runtime import capture_kernel_launches
+    from ._runtime import launch_context
+
+    if stream is None:
+        raise ValueError("build_launch_plan requires a resolved torch CUDA stream, not None")
+    if route is None:
+        route = resolve_route(inputs)
+    with capture_kernel_launches(stream=stream, arch=arch, inputs=inputs) as captured:
+        with launch_context(arch=arch, stream=stream, timeout_ms=None):
+            result = route.launch(inputs, stream=stream, timeout_ms=None)
+    if validate_result is not None:
+        validate_result(result, inputs)
+    if captured.host_data_dependent:
+        static_inputs = {
+            key: value for key, value in inputs.items() if not callable(getattr(value, "data_ptr", None))
+        }
+        return PerCallRoutePlan(
+            route,
+            torch_stream=stream,
+            stream_handle=int(stream.cuda_stream),
+            static_inputs=static_inputs,
+            launch_count=len(captured._launches),
+            host_data_reads=captured.host_data_reads,
+        )
+    sequence = captured.bind(result)
+    return LaunchPlan(
+        route,
+        sequence,
+        torch_stream=stream,
+        stream_handle=int(stream.cuda_stream),
+    )
+
+
+class GraphCaptureUnsupported(RuntimeError):
+    """A plan's launches have no validated CUDA-graph capture path."""
+
+
+def _check_cu(err: Any, message: str) -> None:
+    code = err[0] if isinstance(err, tuple) else err
+    if int(code) != 0:
+        raise RuntimeError(f"{message}: CUresult={int(code)}")
+
+
+class GraphExecPlan:
+    """One per-signature CUDA graph over a LaunchPlan plus support launches.
+
+    Migration step 3 of ``PLAN_BASED_EXPORT_RUNTIME.md``: the signature's
+    stable kernel chain (support launches such as fused row norms, then the
+    frozen route launches) is stream-captured once at plan construction. A
+    hot call is host-only binding (the caller's ``plan.bind_hot`` plus
+    support pointer writes into the same persistent packed argument buffers),
+    then ``submit_hot``: every kernel node's packed buffer is pushed through
+    ``cuGraphExecKernelNodeSetParams`` and the chain replays with one
+    ``cuGraphLaunch`` on the plan's construction-time stream. Kernel-node
+    launch attributes recorded at capture (cluster dimensions, scheduling
+    preference) persist across exec-node parameter updates.
+    """
+
+    __slots__ = (
+        "plan",
+        "_launches",
+        "_graph",
+        "_graph_exec",
+        "_node_params",
+        "_cu_stream",
+        "_set_params",
+        "_graph_launch",
+        "_cu_success",
+        "_destroyed",
+    )
+
+    def __init__(self, plan: LaunchPlan, launches, graph, graph_exec, node_params, cu_stream):
+        from cuda.bindings import driver
+
+        self.plan = plan
+        self._launches = tuple(launches)
+        self._graph = graph
+        self._graph_exec = graph_exec
+        self._node_params = tuple(node_params)
+        self._cu_stream = cu_stream
+        self._set_params = driver.cuGraphExecKernelNodeSetParams
+        self._graph_launch = driver.cuGraphLaunch
+        self._cu_success = driver.CUresult.CUDA_SUCCESS
+        self._destroyed = False
+
+    @property
+    def launch_count(self) -> int:
+        return len(self._launches)
+
+    def submit_hot(self, *, timeout_ms: float | None = None) -> None:
+        """Push the persistent packed argument buffers and replay the graph.
+
+        The caller must have completed every pointer/tensor-map bind for this
+        call (``plan.bind_hot`` plus support-launch binds) first; parameter
+        values are copied out of the packed buffers here.
+        """
+
+        if self._destroyed:
+            raise RuntimeError("graph plan was destroyed by a runtime clear()")
+        set_params = self._set_params
+        graph_exec = self._graph_exec
+        success = self._cu_success
+        for node, params in self._node_params:
+            (err,) = set_params(graph_exec, node, params)
+            if err != success:
+                _check_cu(err, "cuGraphExecKernelNodeSetParams failed")
+        (err,) = self._graph_launch(graph_exec, self._cu_stream)
+        if err != success:
+            _check_cu(err, "cuGraphLaunch failed")
+        if timeout_ms is not None:
+            self._launches[-1]._kernel._wait_with_timeout(self._cu_stream, timeout_ms)
+
+    def destroy(self) -> None:
+        """Release the driver graph handles. Device work must be complete."""
+
+        if self._destroyed:
+            return
+        from cuda.bindings import driver
+
+        self._destroyed = True
+        driver.cuGraphExecDestroy(self._graph_exec)
+        driver.cuGraphDestroy(self._graph)
+
+
+def build_graph_exec_plan(plan: Any, *, support_launches: tuple = ()) -> GraphExecPlan:
+    """Capture ``support_launches`` then ``plan``'s launches into one graph.
+
+    The per-signature slow path, run once at plan construction. Launches are
+    replayed onto a dedicated capture stream (graph construction only — no
+    kernel executes), each launch is mapped to its kernel node through the
+    capture stream's leaf-dependency query, and the captured topology is
+    hard-checked to contain exactly the expected kernel nodes so foreign
+    work (for example watchdog event records) can never silently ride along.
+
+    Raises ``GraphCaptureUnsupported`` for plans that cannot replay from a
+    frozen kernel chain (per-call routes) and for launch modes without a
+    validated capture path (cooperative). Any other failure propagates —
+    a capture that should work but does not is an error, not a fallback.
+    """
+
+    import ctypes
+    import sys
+    from contextlib import nullcontext
+
+    import torch
+    from cuda.bindings import driver
+
+    if not isinstance(plan, LaunchPlan):
+        raise GraphCaptureUnsupported(
+            "only frozen LaunchPlans are graph-capturable; per-call routes re-execute host logic"
+        )
+    launches = tuple(support_launches) + tuple(plan._launches)
+    for launch in launches:
+        if launch._mode not in ("regular", "cluster"):
+            raise GraphCaptureUnsupported(
+                f"launch mode {launch._mode!r} has no validated graph-capture path"
+            )
+
+    # Captured launches build graph nodes and do not execute, so loom's CUDA
+    # watchdog (present only when the in-repo runtime shares this process)
+    # must not record completion events for them: the event record would be
+    # captured as a foreign node and the poller would query a captured event.
+    watchdog = sys.modules.get("loom.runtime.cuda_watchdog")
+    suspend = getattr(watchdog, "suspend_tracking", None)
+    suspension = suspend() if callable(suspend) else nullcontext()
+
+    capture_stream = torch.cuda.Stream(device=plan.torch_stream.device)
+    cu_capture = driver.CUstream(capture_stream.cuda_stream)
+    nodes = []
+    with suspension:
+        (err,) = driver.cuStreamBeginCapture(
+            cu_capture, driver.CUstreamCaptureMode.CU_STREAM_CAPTURE_MODE_THREAD_LOCAL
+        )
+        _check_cu(err, "cuStreamBeginCapture failed")
+        try:
+            for launch in launches:
+                launch.launch(stream=capture_stream, timeout_ms=None)
+                info = driver.cuStreamGetCaptureInfo(cu_capture)
+                _check_cu(info[0], "cuStreamGetCaptureInfo failed")
+                status, leaves = info[1], info[4]
+                if (
+                    status != driver.CUstreamCaptureStatus.CU_STREAM_CAPTURE_STATUS_ACTIVE
+                    or len(leaves) != 1
+                ):
+                    raise RuntimeError(
+                        "graph capture did not add exactly one leaf node for a prepared launch"
+                    )
+                nodes.append(leaves[0])
+        except BaseException:
+            driver.cuStreamEndCapture(cu_capture)  # abandon the partial capture
+            raise
+        err, graph = driver.cuStreamEndCapture(cu_capture)
+        _check_cu(err, "cuStreamEndCapture failed")
+
+    try:
+        err, _probe, total_nodes = driver.cuGraphGetNodes(graph, 0)
+        _check_cu(err, "cuGraphGetNodes failed")
+        if int(total_nodes) != len(launches):
+            raise RuntimeError(
+                f"captured graph has {int(total_nodes)} nodes, expected {len(launches)}; "
+                "foreign work was injected into the capture"
+            )
+        for node in nodes:
+            err, node_type = driver.cuGraphNodeGetType(node)
+            _check_cu(err, "cuGraphNodeGetType failed")
+            if node_type != driver.CUgraphNodeType.CU_GRAPH_NODE_TYPE_KERNEL:
+                raise RuntimeError("captured graph node is not a kernel node")
+        err, graph_exec = driver.cuGraphInstantiate(graph, 0)
+        _check_cu(err, "cuGraphInstantiate failed")
+    except BaseException:
+        driver.cuGraphDestroy(graph)
+        raise
+
+    node_params = []
+    for launch, node in zip(launches, nodes):
+        params = driver.CUDA_KERNEL_NODE_PARAMS()
+        params.func = launch._kernel._func
+        params.gridDimX, params.gridDimY, params.gridDimZ = launch._grid
+        params.blockDimX, params.blockDimY, params.blockDimZ = launch._block
+        params.sharedMemBytes = launch._shared_mem
+        params.kernelParams = ctypes.addressof(launch._packed)
+        params.extra = 0
+        node_params.append((node, params))
+    return GraphExecPlan(
+        plan,
+        launches,
+        graph,
+        graph_exec,
+        node_params,
+        driver.CUstream(plan.stream_handle),
+    )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.cu
new file mode 100644
index 00000000..fc69f7b1
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.cu
@@ -0,0 +1,56 @@
+#include <cuda_bf16.h>
+
+extern "C" __global__ void flashlib_cake_bf16_pair_row_norm(
+    const __nv_bfloat16* x,
+    const __nv_bfloat16* centroids,
+    float* x_sq,
+    float* c_sq,
+    long long x_rows,
+    long long c_rows,
+    int dim,
+    int compute_x,
+    int compute_c) {
+  const long long row = static_cast<long long>(blockIdx.x);
+  const bool is_x = row < x_rows;
+  if ((is_x && compute_x == 0) || (!is_x && compute_c == 0)) {
+    return;
+  }
+
+  const long long local_row = is_x ? row : row - x_rows;
+  if (!is_x && local_row >= c_rows) {
+    return;
+  }
+  const __nv_bfloat16* input = is_x ? x : centroids;
+  float* output = is_x ? x_sq : c_sq;
+  const long long row_offset = local_row * static_cast<long long>(dim);
+
+  float sum = 0.0f;
+  for (int column = static_cast<int>(threadIdx.x); column < dim;
+       column += static_cast<int>(blockDim.x)) {
+    const float value = __bfloat162float(input[row_offset + column]);
+    sum += value * value;
+  }
+
+  constexpr unsigned int kFullMask = 0xffffffffu;
+  for (int offset = 16; offset > 0; offset >>= 1) {
+    sum += __shfl_down_sync(kFullMask, sum, offset);
+  }
+
+  __shared__ float warp_sums[8];
+  const int lane = static_cast<int>(threadIdx.x) & 31;
+  const int warp = static_cast<int>(threadIdx.x) >> 5;
+  if (lane == 0) {
+    warp_sums[warp] = sum;
+  }
+  __syncthreads();
+
+  if (warp == 0) {
+    sum = lane < (blockDim.x >> 5) ? warp_sums[lane] : 0.0f;
+    for (int offset = 16; offset > 0; offset >>= 1) {
+      sum += __shfl_down_sync(kFullMask, sum, offset);
+    }
+    if (lane == 0) {
+      output[local_row] = sum;
+    }
+  }
+}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py
new file mode 100644
index 00000000..92905d4f
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py
@@ -0,0 +1,180 @@
+"""Standalone fused BF16 pair row norms; minimum architecture: sm_80."""
+
+from __future__ import annotations
+
+from dataclasses import dataclass
+from typing import Any
+
+from .kernels import ExportedKernel, KernelSpec
+
+_PAIR_ROW_NORM_KERNEL = ExportedKernel(
+    KernelSpec(
+        name="flashlib_cake_bf16_pair_row_norm",
+        symbol="flashlib_cake_bf16_pair_row_norm",
+        source="_row_norm.cu",
+        threads=256,
+        shared_mem_bytes=0,
+        cluster_dims=(1, 1, 1),
+        launch_mode="standard",
+        parameters=(
+            {"name": "x", "ctype": "const __nv_bfloat16 *"},
+            {"name": "centroids", "ctype": "const __nv_bfloat16 *"},
+            {"name": "x_sq", "ctype": "float *"},
+            {"name": "c_sq", "ctype": "float *"},
+            {"name": "x_rows", "ctype": "int64_t"},
+            {"name": "c_rows", "ctype": "int64_t"},
+            {"name": "dim", "ctype": "int32_t"},
+            {"name": "compute_x", "ctype": "int32_t"},
+            {"name": "compute_c", "ctype": "int32_t"},
+        ),
+        specializations={},
+        compile_options=("--std=c++17",),
+    )
+)
+
+
+def _validate(
+    x: Any,
+    centroids: Any,
+    x_sq: Any,
+    c_sq: Any,
+) -> tuple[int, int, int]:
+    import torch
+
+    if not all(isinstance(item, torch.Tensor) and item.is_cuda for item in (x, centroids)):
+        raise TypeError("pair-row-norm inputs must be CUDA torch.Tensor objects")
+    if x.dtype is not torch.bfloat16 or centroids.dtype is not torch.bfloat16:
+        raise TypeError("pair-row-norm inputs must have bfloat16 dtype")
+    if x.ndim != 3 or centroids.ndim != 3 or not x.is_contiguous() or not centroids.is_contiguous():
+        raise ValueError("pair-row-norm inputs must be contiguous [B, rows, D] tensors")
+    bsz, x_rows, dim = map(int, x.shape)
+    c_bsz, c_rows, c_dim = map(int, centroids.shape)
+    if (bsz, dim) != (c_bsz, c_dim) or x.device != centroids.device:
+        raise ValueError("pair-row-norm inputs must have matching batch, feature, and device")
+    for name, output, shape in (
+        ("x_sq", x_sq, (bsz, x_rows)),
+        ("c_sq", c_sq, (bsz, c_rows)),
+    ):
+        if not isinstance(output, torch.Tensor) or not output.is_cuda:
+            raise TypeError(f"{name} must be a CUDA torch.Tensor")
+        if tuple(output.shape) != shape or output.dtype is not torch.float32:
+            raise ValueError(f"{name} must have dtype float32 and shape {shape}")
+        if output.device != x.device or not output.is_contiguous():
+            raise ValueError(f"{name} must be contiguous and on {x.device}")
+    return bsz * x_rows, bsz * c_rows, dim
+
+
+def _threads_for_dim(dim: int) -> int:
+    return min(256, max(32, 1 << (int(dim) - 1).bit_length()))
+
+
+@dataclass
+class PreparedBF16PairRowNorm:
+    """One pointer-rebindable launch for either or both KMeans row norms."""
+
+    launch_plan: Any
+    x_rows: int
+    c_rows: int
+    dim: int
+    compute_x: bool
+    compute_c: bool
+
+    def rebind(
+        self,
+        x: Any,
+        centroids: Any,
+        x_sq: Any,
+        c_sq: Any,
+        *,
+        stream: Any = None,
+    ) -> None:
+        x_rows, c_rows, dim = _validate(x, centroids, x_sq, c_sq)
+        if (x_rows, c_rows, dim) != (self.x_rows, self.c_rows, self.dim):
+            raise RuntimeError("pair-row-norm prepared launch topology changed")
+        self.launch_plan.rebind_arguments(
+            {0: x, 1: centroids, 2: x_sq, 3: c_sq},
+            stream=stream,
+        )
+
+    def launch(self, *, stream: Any = None, timeout_ms: float | None = None) -> None:
+        self.launch_plan.launch(stream=stream, timeout_ms=timeout_ms)
+
+    def release_bound_callers(self, keepalive: Any, *, stream: Any = None) -> None:
+        """Drop caller tensors while retaining one slot-owned scratch tensor."""
+
+        self.launch_plan.rebind_arguments(
+            {0: keepalive, 1: keepalive, 2: keepalive, 3: keepalive},
+            stream=stream,
+        )
+
+
+def prepare_bf16_pair_row_norm(
+    x: Any,
+    centroids: Any,
+    x_sq: Any,
+    c_sq: Any,
+    *,
+    compute_x: bool,
+    compute_c: bool,
+    arch: str | None = None,
+    stream: Any = None,
+) -> PreparedBF16PairRowNorm:
+    if not compute_x and not compute_c:
+        raise ValueError("pair-row-norm preparation requires at least one output")
+    x_rows, c_rows, dim = _validate(x, centroids, x_sq, c_sq)
+    launch_plan = _PAIR_ROW_NORM_KERNEL.prepare_launch(
+        x,
+        centroids,
+        x_sq,
+        c_sq,
+        x_rows,
+        c_rows,
+        dim,
+        int(compute_x),
+        int(compute_c),
+        grid=(x_rows + c_rows, 1, 1),
+        block=(_threads_for_dim(dim), 1, 1),
+        stream=stream,
+        arch=arch,
+    )
+    return PreparedBF16PairRowNorm(
+        launch_plan=launch_plan,
+        x_rows=x_rows,
+        c_rows=c_rows,
+        dim=dim,
+        compute_x=bool(compute_x),
+        compute_c=bool(compute_c),
+    )
+
+
+def launch_bf16_pair_row_norm(
+    x: Any,
+    centroids: Any,
+    x_sq: Any,
+    c_sq: Any,
+    *,
+    compute_x: bool,
+    compute_c: bool,
+    stream: Any,
+    arch: str,
+    timeout_ms: float | None,
+) -> None:
+    """Compute either or both BF16 row-squared norms in one CUDA activity."""
+
+    prepared = prepare_bf16_pair_row_norm(
+        x,
+        centroids,
+        x_sq,
+        c_sq,
+        compute_x=compute_x,
+        compute_c=compute_c,
+        arch=arch,
+        stream=stream,
+    )
+    try:
+        prepared.launch(stream=stream, timeout_ms=timeout_ms)
+    finally:
+        prepared.release_bound_callers(
+            x_sq if compute_x else c_sq,
+            stream=stream,
+        )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_runtime.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_runtime.py
new file mode 100644
index 00000000..64de997a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_runtime.py
@@ -0,0 +1,912 @@
+from __future__ import annotations
+
+import contextlib
+import contextvars
+import ctypes
+import os
+import shutil
+import threading
+import time
+from collections.abc import Iterator, Sequence
+from typing import Any
+
+import torch
+from cuda.bindings import driver, nvrtc
+
+
+_LAUNCH_DEFAULTS: contextvars.ContextVar[tuple[str | None, Any, float | None] | None] = (
+    contextvars.ContextVar("loom_export_launch_defaults", default=None)
+)
+_COMPILATION_CACHE_LOCK = threading.RLock()
+_CUBIN_CACHE: dict[tuple[str, str, tuple[str, ...]], bytes] = {}
+_MODULE_CACHE: dict[tuple[str, str, tuple[str, ...], int], "_LoadedModule"] = {}
+_KERNEL_CACHE: dict[tuple[str, str, tuple[str, ...], int, str], "CUDAKernel"] = {}
+_COMPILATION_CACHE_GENERATION = 0
+_RUNTIME_ACTIVITY_COUNTS = {
+    "source_reads": 0,
+    "nvrtc_compiles": 0,
+    "module_loads": 0,
+}
+
+
+def _record_runtime_activity(name: str) -> None:
+    with _COMPILATION_CACHE_LOCK:
+        _RUNTIME_ACTIVITY_COUNTS[name] += 1
+
+
+def record_source_read() -> None:
+    _record_runtime_activity("source_reads")
+
+
+def runtime_activity_snapshot() -> dict[str, int]:
+    with _COMPILATION_CACHE_LOCK:
+        return dict(_RUNTIME_ACTIVITY_COUNTS)
+
+
+class NVRTCError(RuntimeError):
+    def __init__(self, message: str, log: str):
+        self.log = log
+        super().__init__(f"{message}\n--- NVRTC log ---\n{log}")
+
+
+def _check(err: int, msg: str) -> None:
+    if err != 0:
+        raise RuntimeError(f"{msg}: CUresult={err}")
+
+
+def _nvrtc_check(err: int, msg: str) -> None:
+    if err != 0:
+        raise RuntimeError(f"{msg}: nvrtcResult={err}")
+
+
+def _arch_flag_for_cc(major: int, minor: int) -> str:
+    sm = int(major) * 10 + int(minor)
+    return f"sm_{sm}a" if sm >= 90 else f"sm_{sm}"
+
+
+def detect_gpu_arch() -> str:
+    forced = os.environ.get("LOOM_EXPORTED_FORCE_ARCH") or os.environ.get("LOOM_FORCE_ARCH")
+    if forced:
+        return forced
+    try:
+        (err,) = driver.cuInit(0)
+        if err != 0:
+            return "sm_100a"
+        err, dev = driver.cuDeviceGet(0)
+        if err != 0:
+            return "sm_100a"
+        err, major = driver.cuDeviceGetAttribute(
+            driver.CUdevice_attribute.CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR, dev
+        )
+        err2, minor = driver.cuDeviceGetAttribute(
+            driver.CUdevice_attribute.CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR, dev
+        )
+        if err != 0 or err2 != 0:
+            return "sm_100a"
+        return _arch_flag_for_cc(int(major), int(minor))
+    except Exception:
+        return "sm_100a"
+
+
+def resolve_gpu_arch(arch: str | None) -> str:
+    return detect_gpu_arch() if arch is None else str(arch)
+
+
+def current_cuda_device_index() -> int:
+    return int(torch.cuda.current_device())
+
+
+def _is_torch_stream(stream: Any) -> bool:
+    return isinstance(stream, torch.cuda.Stream)
+
+
+def launch_stream_context(stream: Any):
+    return torch.cuda.stream(stream) if _is_torch_stream(stream) else contextlib.nullcontext()
+
+
+@contextlib.contextmanager
+def launch_context(
+    *,
+    arch: str | None = None,
+    stream: Any = None,
+    timeout_ms: float | None = None,
+) -> Iterator[None]:
+    '''Apply semantic-call launch defaults to every frozen kernel stage.
+
+    The current PyTorch stream is captured lazily once before the first frozen
+    launch when no explicit stream is supplied.  Passing a PyTorch stream also
+    makes dispatcher-side PyTorch tensor operations use that stream, not only
+    the generated driver launches. Context variables keep concurrent threads
+    and nested semantic calls isolated.
+    '''
+    resolved_stream = stream
+    token = _LAUNCH_DEFAULTS.set((arch, resolved_stream, timeout_ms))
+    stream_context = launch_stream_context(resolved_stream)
+    try:
+        with stream_context:
+            yield
+    finally:
+        _LAUNCH_DEFAULTS.reset(token)
+
+
+def resolve_launch_defaults(
+    *,
+    arch: str | None,
+    stream: Any,
+    timeout_ms: float | None,
+) -> tuple[str | None, Any, float | None]:
+    defaults = _LAUNCH_DEFAULTS.get()
+    if defaults is None:
+        return arch, stream, timeout_ms
+    default_arch, default_stream, default_timeout_ms = defaults
+    if stream is None and default_stream is None:
+        default_stream = torch.cuda.current_stream()
+        _LAUNCH_DEFAULTS.set((default_arch, default_stream, default_timeout_ms))
+    return (
+        default_arch if arch is None else arch,
+        default_stream if stream is None else stream,
+        default_timeout_ms if timeout_ms is None else timeout_ms,
+    )
+
+
+def compilation_cache_generation() -> int:
+    return _COMPILATION_CACHE_GENERATION
+
+
+def _cuda_include_dirs() -> list[str]:
+    candidates = ["/usr/local/cuda/include"]
+    nvcc = shutil.which("nvcc")
+    if nvcc:
+        candidates.insert(0, os.path.join(os.path.dirname(os.path.dirname(nvcc)), "include"))
+    return [d for d in candidates if os.path.isdir(d)]
+
+
+def _get_compile_log(prog: nvrtc.nvrtcProgram) -> str:
+    err, size = nvrtc.nvrtcGetProgramLogSize(prog)
+    if err != 0 or size <= 1:
+        return ""
+    log = b"\x00" * size
+    nvrtc.nvrtcGetProgramLog(prog, log)
+    return log.decode(errors="replace").rstrip("\x00")
+
+
+def compile_cuda(
+    source: str,
+    *,
+    arch: str | None = None,
+    name: str = "kernel.cu",
+    options: list[str] | None = None,
+) -> bytes:
+    _record_runtime_activity("nvrtc_compiles")
+    if arch is None:
+        arch = detect_gpu_arch()
+    opts = [
+        f"--gpu-architecture={arch}",
+        "-std=c++17",
+        "-default-device",
+    ]
+    for include_dir in _cuda_include_dirs():
+        opts.append(f"-I{include_dir}")
+        cccl = os.path.join(include_dir, "cccl")
+        if os.path.exists(os.path.join(cccl, "cuda", "std")):
+            opts.append(f"-I{cccl}")
+    if options:
+        opts.extend(options)
+
+    err, prog = nvrtc.nvrtcCreateProgram(source.encode(), name.encode(), 0, [], [])
+    _nvrtc_check(err, "nvrtcCreateProgram failed")
+    try:
+        encoded_opts = [opt.encode() for opt in opts]
+        (err,) = nvrtc.nvrtcCompileProgram(prog, len(encoded_opts), encoded_opts)
+        if err != 0:
+            raise NVRTCError(f"Compilation failed for {name!r}", _get_compile_log(prog))
+        err, size = nvrtc.nvrtcGetCUBINSize(prog)
+        _nvrtc_check(err, "nvrtcGetCUBINSize failed")
+        cubin = b"\x00" * size
+        (err,) = nvrtc.nvrtcGetCUBIN(prog, cubin)
+        _nvrtc_check(err, "nvrtcGetCUBIN failed")
+        return cubin
+    finally:
+        nvrtc.nvrtcDestroyProgram(prog)
+
+
+def _is_tensor(arg: Any) -> bool:
+    return isinstance(arg, torch.Tensor)
+
+
+def _marshal_arg(arg: Any, ctype: str) -> ctypes._SimpleCData:
+    normalized = " ".join(ctype.replace("__restrict__", "").split())
+    if "*" in normalized:
+        if _is_tensor(arg):
+            return ctypes.c_void_p(arg.data_ptr())
+        if isinstance(arg, ctypes.c_void_p):
+            return arg
+        if isinstance(arg, int) and not isinstance(arg, bool):
+            return ctypes.c_void_p(arg)
+        raise TypeError(f"Pointer argument {ctype!r} requires a CUDA tensor or integer device pointer, got {type(arg)}")
+    if normalized in {"bool", "_Bool"}:
+        if not isinstance(arg, bool):
+            raise TypeError(f"Scalar argument {ctype!r} requires bool, got {type(arg)}")
+        return ctypes.c_bool(arg)
+    integer_abis = {
+        "int8_t": (ctypes.c_int8, -(1 << 7), (1 << 7) - 1),
+        "signed char": (ctypes.c_int8, -(1 << 7), (1 << 7) - 1),
+        "uint8_t": (ctypes.c_uint8, 0, (1 << 8) - 1),
+        "unsigned char": (ctypes.c_uint8, 0, (1 << 8) - 1),
+        "int16_t": (ctypes.c_int16, -(1 << 15), (1 << 15) - 1),
+        "short": (ctypes.c_int16, -(1 << 15), (1 << 15) - 1),
+        "short int": (ctypes.c_int16, -(1 << 15), (1 << 15) - 1),
+        "uint16_t": (ctypes.c_uint16, 0, (1 << 16) - 1),
+        "unsigned short": (ctypes.c_uint16, 0, (1 << 16) - 1),
+        "unsigned short int": (ctypes.c_uint16, 0, (1 << 16) - 1),
+        "int32_t": (ctypes.c_int32, -(1 << 31), (1 << 31) - 1),
+        "int": (ctypes.c_int32, -(1 << 31), (1 << 31) - 1),
+        "signed int": (ctypes.c_int32, -(1 << 31), (1 << 31) - 1),
+        "uint32_t": (ctypes.c_uint32, 0, (1 << 32) - 1),
+        "unsigned int": (ctypes.c_uint32, 0, (1 << 32) - 1),
+        "int64_t": (ctypes.c_int64, -(1 << 63), (1 << 63) - 1),
+        "long long": (ctypes.c_int64, -(1 << 63), (1 << 63) - 1),
+        "uint64_t": (ctypes.c_uint64, 0, (1 << 64) - 1),
+        "unsigned long long": (ctypes.c_uint64, 0, (1 << 64) - 1),
+        "size_t": (ctypes.c_uint64, 0, (1 << 64) - 1),
+    }
+    integer_abi = integer_abis.get(normalized)
+    if integer_abi is not None:
+        if not isinstance(arg, int) or isinstance(arg, bool):
+            raise TypeError(f"Scalar argument {ctype!r} requires int, got {type(arg)}")
+        scalar_ctype, minimum, maximum = integer_abi
+        if arg < minimum or arg > maximum:
+            raise OverflowError(f"Scalar argument {ctype!r} is out of range: {arg}")
+        return scalar_ctype(arg)
+    if normalized in {"float", "double"}:
+        if not isinstance(arg, (int, float)) or isinstance(arg, bool):
+            raise TypeError(f"Scalar argument {ctype!r} requires int or float, got {type(arg)}")
+        return ctypes.c_float(arg) if normalized == "float" else ctypes.c_double(arg)
+    raise TypeError(f"Unsupported scalar ABI type {ctype!r}")
+
+
+def _pack_args(args: Sequence[Any], arg_types: Sequence[str]) -> ctypes.Array:
+    if len(args) != len(arg_types):
+        raise ValueError(f"Argument count mismatch: got {len(args)}, expected {len(arg_types)}")
+    c_args = [_marshal_arg(arg, ctype) for arg, ctype in zip(args, arg_types, strict=True)]
+    ptrs = (ctypes.c_void_p * len(c_args))(*(ctypes.cast(ctypes.pointer(arg), ctypes.c_void_p) for arg in c_args))
+    ptrs._prevent_gc = c_args  # type: ignore[attr-defined]
+    return ptrs
+
+
+class PreparedCUDAKernelLaunch:
+    # A fully marshalled generated-runtime launch reusable on the hot path.
+
+    def __init__(
+        self,
+        kernel,
+        *,
+        mode,
+        grid,
+        block,
+        arg_types,
+        packed,
+        keepalive,
+        shared_mem,
+        cu_stream,
+        cluster_dims=None,
+        config=None,
+    ):
+        self._kernel = kernel
+        self._mode = mode
+        self._grid = tuple(grid)
+        self._block = tuple(block)
+        self._arg_types = tuple(arg_types)
+        self._packed = packed
+        self._keepalive = keepalive
+        self._shared_mem = shared_mem
+        self._cu_stream = cu_stream
+        self._cluster_dims = None if cluster_dims is None else tuple(cluster_dims)
+        self._config = config
+
+    def rebind(
+        self,
+        kernel,
+        *,
+        mode,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem,
+        stream=None,
+        cluster_dims=None,
+    ):
+        # Reuse the existing void** and scalar carriers while replacing values.
+
+        candidate_grid = tuple(grid)
+        candidate_block = tuple(block)
+        candidate_arg_types = tuple(arg_types)
+        candidate_cluster_dims = None if cluster_dims is None else tuple(cluster_dims)
+        mismatches = []
+        if kernel is not self._kernel:
+            mismatches.append("kernel")
+        if mode != self._mode:
+            mismatches.append(f"mode ({self._mode!r} != {mode!r})")
+        if candidate_grid != self._grid:
+            mismatches.append(f"grid ({self._grid!r} != {candidate_grid!r})")
+        if candidate_block != self._block:
+            mismatches.append(f"block ({self._block!r} != {candidate_block!r})")
+        if int(shared_mem) != self._shared_mem:
+            mismatches.append(f"shared_mem ({self._shared_mem!r} != {int(shared_mem)!r})")
+        if candidate_cluster_dims != self._cluster_dims:
+            mismatches.append(
+                f"cluster_dims ({self._cluster_dims!r} != {candidate_cluster_dims!r})"
+            )
+        if candidate_arg_types != self._arg_types:
+            mismatches.append("arg_types")
+        if mismatches:
+            raise RuntimeError(
+                "prepared CUDA launch topology mismatch: " + ", ".join(mismatches)
+            )
+
+        if len(args) != len(self._arg_types):
+            raise RuntimeError(
+                f"prepared CUDA launch argument count mismatch: "
+                f"expected {len(self._arg_types)}, got {len(args)}"
+            )
+        return self.rebind_arguments(dict(enumerate(args)), stream=stream)
+
+    def rebind_arguments(self, replacements, *, stream=None):
+        # Update selected ABI carriers without rebuilding or traversing the launch.
+
+        old_c_args = self._packed._prevent_gc
+        if len(old_c_args) != len(self._arg_types):
+            raise RuntimeError("prepared CUDA launch has a corrupt packed argument array")
+        rebound = []
+        for index, arg in replacements.items():
+            if type(index) is not int or index < 0 or index >= len(self._arg_types):
+                raise IndexError(f"prepared CUDA launch argument index is out of range: {index!r}")
+            new_arg = _marshal_arg(arg, self._arg_types[index])
+            old_arg = old_c_args[index]
+            if type(old_arg) is not type(new_arg):
+                raise RuntimeError(
+                    f"prepared CUDA launch ABI mismatch at argument {index}: "
+                    f"{type(old_arg).__name__} != {type(new_arg).__name__}"
+                )
+            rebound.append((index, arg, old_arg, new_arg))
+
+        cu_stream = self._kernel._cu_stream(stream)
+        keepalive = list(self._keepalive)
+        for index, arg, old_arg, new_arg in rebound:
+            old_arg.value = new_arg.value
+            keepalive[index] = arg
+        self._keepalive = tuple(keepalive)
+        self._cu_stream = cu_stream
+        return self
+
+    def rebind_tensor_arguments(
+        self,
+        bindings,
+        inputs,
+        *,
+        stream=None,
+        preserve_stream=False,
+        retain_inputs=True,
+        pointer_values=None,
+        inputs_already_scrubbed=False,
+    ):
+        # Captured public bindings are pointer-only. Update their existing
+        # c_void_p carriers directly instead of rematerializing ctypes objects.
+
+        if not isinstance(preserve_stream, bool):
+            raise TypeError("preserve_stream must be a bool")
+        if not isinstance(retain_inputs, bool):
+            raise TypeError("retain_inputs must be a bool")
+        if not isinstance(inputs_already_scrubbed, bool):
+            raise TypeError("inputs_already_scrubbed must be a bool")
+        if inputs_already_scrubbed and retain_inputs:
+            raise ValueError("inputs_already_scrubbed requires retain_inputs=False")
+        if pointer_values is not None and retain_inputs:
+            raise ValueError("pointer_values requires retain_inputs=False")
+        old_c_args = self._packed._prevent_gc
+        if len(old_c_args) != len(self._arg_types):
+            raise RuntimeError("prepared CUDA launch has a corrupt packed argument array")
+        replacements = []
+        for index, key in bindings:
+            if type(index) is not int or index < 0 or index >= len(self._arg_types):
+                raise IndexError(f"prepared CUDA launch argument index is out of range: {index!r}")
+            arg = None
+            if pointer_values is None:
+                try:
+                    arg = inputs[key]
+                except KeyError:
+                    raise KeyError(f"missing prepared CUDA tensor binding: {key!r}") from None
+                data_ptr = getattr(arg, "data_ptr", None)
+                if not callable(data_ptr):
+                    raise TypeError(f"prepared CUDA tensor binding {key!r} is not tensor-like")
+                pointer = int(data_ptr())
+            else:
+                try:
+                    pointer = pointer_values[key]
+                except KeyError:
+                    raise KeyError(f"missing prepared CUDA pointer binding: {key!r}") from None
+                if type(pointer) is not int:
+                    raise TypeError(f"prepared CUDA pointer binding {key!r} is not an int")
+            old_arg = old_c_args[index]
+            if type(old_arg) is not ctypes.c_void_p:
+                raise RuntimeError(
+                    f"prepared CUDA tensor binding {key!r} does not target a pointer carrier"
+                )
+            if inputs_already_scrubbed and type(self._keepalive[index]) is not int:
+                raise RuntimeError(
+                    f"prepared CUDA tensor binding {key!r} retained an unexpected caller reference"
+                )
+            replacements.append((index, key, arg, pointer, old_arg))
+
+        keepalive = None if inputs_already_scrubbed else list(self._keepalive)
+        for index, key, arg, pointer, old_arg in replacements:
+            old_arg.value = pointer
+            if keepalive is not None:
+                if retain_inputs and arg is None:
+                    arg = inputs[key]
+                keepalive[index] = arg if retain_inputs else pointer
+        if keepalive is not None:
+            self._keepalive = tuple(keepalive)
+        if not preserve_stream:
+            self._cu_stream = self._kernel._cu_stream(stream)
+        return self
+
+    def _scrub_stream_bound_pointer_keepalives(self, bindings):
+        '''Drop selected tensor references without changing carriers or stream.'''
+
+        old_c_args = self._packed._prevent_gc
+        if len(old_c_args) != len(self._arg_types):
+            raise RuntimeError("prepared CUDA launch has a corrupt packed argument array")
+        scrubbed = list(self._keepalive)
+        program = []
+        for index, key in bindings:
+            if type(index) is not int or index < 0 or index >= len(self._arg_types):
+                raise IndexError(f"prepared CUDA launch argument index is out of range: {index!r}")
+            carrier = old_c_args[index]
+            if type(carrier) is not ctypes.c_void_p:
+                raise RuntimeError(
+                    f"prepared CUDA tensor binding {key!r} does not target a pointer carrier"
+                )
+            value = scrubbed[index]
+            data_ptr = getattr(value, "data_ptr", None)
+            if not callable(data_ptr):
+                raise RuntimeError(
+                    f"prepared CUDA tensor binding {key!r} retained an unexpected value"
+                )
+            pointer = int(data_ptr())
+            if carrier.value != pointer:
+                raise RuntimeError(
+                    f"prepared CUDA tensor binding {key!r} carrier disagrees with its keepalive"
+                )
+            scrubbed[index] = pointer
+            program.append((key, carrier))
+        self._keepalive = tuple(scrubbed)
+        return tuple(program)
+
+    def launch(self, *, stream=None, timeout_ms=None):
+        kernel = self._kernel
+        if kernel._closed:
+            raise RuntimeError("Kernel has been unloaded")
+        cu_stream = self._cu_stream if stream is None else kernel._cu_stream(stream)
+        if self._mode == "cluster":
+            self._config.hStream = cu_stream
+            (err,) = driver.cuLaunchKernelEx(self._config, kernel._func, self._packed, 0)
+            api = "cuLaunchKernelEx"
+        elif self._mode == "cooperative":
+            (err,) = driver.cuLaunchCooperativeKernel(
+                kernel._func,
+                *self._grid,
+                *self._block,
+                self._shared_mem,
+                cu_stream,
+                self._packed,
+            )
+            api = "cuLaunchCooperativeKernel"
+        else:
+            (err,) = driver.cuLaunchKernel(
+                kernel._func,
+                *self._grid,
+                *self._block,
+                self._shared_mem,
+                cu_stream,
+                self._packed,
+                0,
+            )
+            api = "cuLaunchKernel"
+        _check(err, f"{api} failed for {kernel._func_name!r}")
+        if timeout_ms is not None:
+            kernel._wait_with_timeout(cu_stream, timeout_ms)
+
+
+class _LoadedModule:
+    def __init__(self, cubin: bytes):
+        _record_runtime_activity("module_loads")
+        torch.empty(0, device="cuda")
+        err, self._module = driver.cuModuleLoadData(cubin)
+        _check(err, "cuModuleLoadData failed")
+        self._functions: dict[str, Any] = {}
+        self._closed = False
+
+    @property
+    def handle(self):
+        return self._module
+
+    @property
+    def closed(self) -> bool:
+        return self._closed
+
+    def function(self, func_name: str):
+        if self._closed:
+            raise RuntimeError("CUDA module has been unloaded")
+        function = self._functions.get(func_name)
+        if function is None:
+            err, function = driver.cuModuleGetFunction(self._module, func_name.encode())
+            _check(err, f"cuModuleGetFunction failed for {func_name!r}")
+            self._functions[func_name] = function
+        return function
+
+    def close(self) -> None:
+        if not self._closed:
+            driver.cuModuleUnload(self._module)
+            self._closed = True
+
+
+class CUDAKernel:
+    def __init__(self, cubin: bytes, func_name: str):
+        self._module_owner = _LoadedModule(cubin)
+        self._owns_module = True
+        self._initialize_from_module(func_name)
+
+    @classmethod
+    def from_loaded_module(cls, module: _LoadedModule, func_name: str) -> "CUDAKernel":
+        kernel = cls.__new__(cls)
+        kernel._module_owner = module
+        kernel._owns_module = False
+        kernel._initialize_from_module(func_name)
+        return kernel
+
+    def _initialize_from_module(self, func_name: str) -> None:
+        self._closed = True
+        self._func_name = func_name
+        self._module = self._module_owner.handle
+        self._func = self._module_owner.function(func_name)
+        self._dynamic_smem_opt_in_bytes = 0
+        self._closed = False
+
+    @property
+    def closed(self) -> bool:
+        return self._closed
+
+    def _ensure_dynamic_smem_opt_in(self, shared_mem: int) -> None:
+        if shared_mem <= 48 * 1024 or shared_mem <= self._dynamic_smem_opt_in_bytes:
+            return
+        (err,) = driver.cuFuncSetAttribute(
+            self._func,
+            driver.CUfunction_attribute.CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,
+            shared_mem,
+        )
+        _check(err, "cuFuncSetAttribute MAX_DYNAMIC_SHARED_SIZE_BYTES failed")
+        self._dynamic_smem_opt_in_bytes = max(self._dynamic_smem_opt_in_bytes, shared_mem)
+
+    def _cu_stream(self, stream=None):
+        if stream is None:
+            stream = torch.cuda.current_stream()
+        handle = getattr(stream, "cuda_stream", stream)
+        return driver.CUstream(int(handle))
+
+    def _wait_with_timeout(self, cu_stream: driver.CUstream, timeout_ms: float) -> None:
+        deadline = time.monotonic() + timeout_ms / 1000.0
+        while True:
+            (err,) = driver.cuStreamQuery(cu_stream)
+            if err == 0:
+                return
+            if err != 600:
+                _check(err, f"cuStreamQuery failed for {self._func_name!r}")
+            if time.monotonic() >= deadline:
+                raise TimeoutError(f"Kernel {self._func_name!r} did not complete within {timeout_ms:.0f} ms")
+            time.sleep(0.001)
+
+    def launch(
+        self,
+        *,
+        grid: tuple[int, int, int],
+        block: tuple[int, int, int],
+        args: Sequence[Any],
+        arg_types: Sequence[str],
+        shared_mem: int = 0,
+        stream=None,
+        timeout_ms: float | None = None,
+    ) -> None:
+        self.prepare_launch(
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            shared_mem=shared_mem,
+            stream=stream,
+        ).launch(timeout_ms=timeout_ms)
+
+    def prepare_launch(
+        self,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem=0,
+        stream=None,
+    ):
+        if self._closed:
+            raise RuntimeError("Kernel has been unloaded")
+        self._ensure_dynamic_smem_opt_in(shared_mem)
+        return PreparedCUDAKernelLaunch(
+            self,
+            mode="regular",
+            grid=grid,
+            block=block,
+            arg_types=arg_types,
+            packed=_pack_args(args, arg_types),
+            keepalive=tuple(args),
+            shared_mem=shared_mem,
+            cu_stream=self._cu_stream(stream),
+        )
+
+    def rebind_launch(
+        self,
+        prepared,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem=0,
+        stream=None,
+    ):
+        if not isinstance(prepared, PreparedCUDAKernelLaunch):
+            raise TypeError("prepared must be a PreparedCUDAKernelLaunch")
+        return prepared.rebind(
+            self,
+            mode="regular",
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            shared_mem=shared_mem,
+            stream=stream,
+        )
+
+    def launch_cluster(
+        self,
+        *,
+        grid: tuple[int, int, int],
+        block: tuple[int, int, int],
+        args: Sequence[Any],
+        arg_types: Sequence[str],
+        cluster_dims: tuple[int, int, int],
+        shared_mem: int = 0,
+        stream=None,
+        timeout_ms: float | None = None,
+    ) -> None:
+        self.prepare_launch_cluster(
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            cluster_dims=cluster_dims,
+            shared_mem=shared_mem,
+            stream=stream,
+        ).launch(timeout_ms=timeout_ms)
+
+    def prepare_launch_cluster(
+        self,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        cluster_dims,
+        shared_mem=0,
+        stream=None,
+    ):
+        if self._closed:
+            raise RuntimeError("Kernel has been unloaded")
+        self._ensure_dynamic_smem_opt_in(shared_mem)
+        packed = _pack_args(args, arg_types)
+        cu_stream = self._cu_stream(stream)
+
+        attr_cluster = driver.CUlaunchAttribute()
+        attr_cluster.id = driver.CUlaunchAttributeID.CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION
+        attr_cluster.value.clusterDim.x = cluster_dims[0]
+        attr_cluster.value.clusterDim.y = cluster_dims[1]
+        attr_cluster.value.clusterDim.z = cluster_dims[2]
+
+        attr_sched = driver.CUlaunchAttribute()
+        attr_sched.id = driver.CUlaunchAttributeID.CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE
+        attr_sched.value.clusterSchedulingPolicyPreference = (
+            driver.CUclusterSchedulingPolicy.CU_CLUSTER_SCHEDULING_POLICY_SPREAD
+        )
+
+        config = driver.CUlaunchConfig()
+        config.gridDimX = grid[0]
+        config.gridDimY = grid[1]
+        config.gridDimZ = grid[2]
+        config.blockDimX = block[0]
+        config.blockDimY = block[1]
+        config.blockDimZ = block[2]
+        config.sharedMemBytes = shared_mem
+        config.hStream = cu_stream
+        config.attrs = [attr_cluster, attr_sched]
+        config.numAttrs = 2
+        return PreparedCUDAKernelLaunch(
+            self,
+            mode="cluster",
+            grid=grid,
+            block=block,
+            arg_types=arg_types,
+            packed=packed,
+            keepalive=tuple(args),
+            shared_mem=shared_mem,
+            cu_stream=cu_stream,
+            cluster_dims=cluster_dims,
+            config=config,
+        )
+
+    def rebind_launch_cluster(
+        self,
+        prepared,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        cluster_dims,
+        shared_mem=0,
+        stream=None,
+    ):
+        if not isinstance(prepared, PreparedCUDAKernelLaunch):
+            raise TypeError("prepared must be a PreparedCUDAKernelLaunch")
+        return prepared.rebind(
+            self,
+            mode="cluster",
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            cluster_dims=cluster_dims,
+            shared_mem=shared_mem,
+            stream=stream,
+        )
+
+    def launch_cooperative(
+        self,
+        *,
+        grid: tuple[int, int, int],
+        block: tuple[int, int, int],
+        args: Sequence[Any],
+        arg_types: Sequence[str],
+        shared_mem: int = 0,
+        stream=None,
+        timeout_ms: float | None = None,
+    ) -> None:
+        self.prepare_launch_cooperative(
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            shared_mem=shared_mem,
+            stream=stream,
+        ).launch(timeout_ms=timeout_ms)
+
+    def prepare_launch_cooperative(
+        self,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem=0,
+        stream=None,
+    ):
+        if self._closed:
+            raise RuntimeError("Kernel has been unloaded")
+        self._ensure_dynamic_smem_opt_in(shared_mem)
+        return PreparedCUDAKernelLaunch(
+            self,
+            mode="cooperative",
+            grid=grid,
+            block=block,
+            arg_types=arg_types,
+            packed=_pack_args(args, arg_types),
+            keepalive=tuple(args),
+            shared_mem=shared_mem,
+            cu_stream=self._cu_stream(stream),
+        )
+
+    def rebind_launch_cooperative(
+        self,
+        prepared,
+        *,
+        grid,
+        block,
+        args,
+        arg_types,
+        shared_mem=0,
+        stream=None,
+    ):
+        if not isinstance(prepared, PreparedCUDAKernelLaunch):
+            raise TypeError("prepared must be a PreparedCUDAKernelLaunch")
+        return prepared.rebind(
+            self,
+            mode="cooperative",
+            grid=grid,
+            block=block,
+            args=args,
+            arg_types=arg_types,
+            shared_mem=shared_mem,
+            stream=stream,
+        )
+
+    def close(self) -> None:
+        if not self._closed:
+            if self._owns_module:
+                self._module_owner.close()
+            self._closed = True
+
+    def __del__(self):
+        try:
+            self.close()
+        except Exception:
+            pass
+
+
+def load_cached_kernel(
+    source: str,
+    *,
+    source_digest: str,
+    func_name: str,
+    arch: str,
+    device_index: int,
+    name: str,
+    options: Sequence[str] = (),
+) -> CUDAKernel:
+    '''Compile/load one content-addressed kernel shared by equivalent aliases.
+
+    Identical source, architecture, and options share NVRTC output.  The active
+    device is added for module loading, and the function symbol only for the
+    final wrapper, so a multi-entrypoint translation unit loads one module per
+    device without conflating its functions.
+    '''
+    option_tuple = tuple(options)
+    cubin_key = (source_digest, arch, option_tuple)
+    module_key = (*cubin_key, int(device_index))
+    kernel_key = (*module_key, func_name)
+    with _COMPILATION_CACHE_LOCK:
+        kernel = _KERNEL_CACHE.get(kernel_key)
+        if kernel is not None and not kernel.closed:
+            return kernel
+        cubin = _CUBIN_CACHE.get(cubin_key)
+        if cubin is None:
+            cubin = compile_cuda(source, arch=arch, name=name, options=list(option_tuple))
+            _CUBIN_CACHE[cubin_key] = cubin
+        module = _MODULE_CACHE.get(module_key)
+        if module is None or module.closed:
+            module = _LoadedModule(cubin)
+            _MODULE_CACHE[module_key] = module
+        kernel = CUDAKernel.from_loaded_module(module, func_name)
+        _KERNEL_CACHE[kernel_key] = kernel
+        return kernel
+
+
+def clear_compilation_cache() -> None:
+    '''Clear process-local cubin/module caches (primarily for diagnostics).'''
+    global _COMPILATION_CACHE_GENERATION
+    with _COMPILATION_CACHE_LOCK:
+        for kernel in _KERNEL_CACHE.values():
+            kernel._closed = True
+        for module in _MODULE_CACHE.values():
+            module.close()
+        _KERNEL_CACHE.clear()
+        _MODULE_CACHE.clear()
+        _CUBIN_CACHE.clear()
+        _COMPILATION_CACHE_GENERATION += 1
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0000.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0000.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0000.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0001.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0001.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0001.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0002.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0002.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0002.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0003.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0003.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0003.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0004.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0004.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0004.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0005.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0005.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0005.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0006.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0006.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0006.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0007.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0007.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0007.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0008.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0008.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0008.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0009.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0009.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0009.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0010.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0010.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0010.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0011.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0011.cu
new file mode 100644
index 00000000..f6311654
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0011.cu
@@ -0,0 +1,535 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 41984
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 43008
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 41984);
+    const int smem_csq_addr = smem + 41984;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice * 2;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 2; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1 * 2;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 2; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2 * 2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 2; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0012.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0012.cu
new file mode 100644
index 00000000..461424c3
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0012.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0013.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0013.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0013.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0014.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0014.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0014.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0015.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0015.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0015.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0016.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0016.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0016.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0017.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0017.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0017.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0018.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0018.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0018.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0019.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0019.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0019.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0020.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0020.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0020.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0021.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0021.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0021.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0022.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0022.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0022.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0023.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0023.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0023.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0024.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0024.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0024.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0025.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0025.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0025.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0026.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0026.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0026.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0027.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0027.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0027.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0028.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0028.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0028.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0029.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0029.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0029.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0030.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0030.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0030.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0031.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0031.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0031.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0032.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0032.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0032.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0033.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0033.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0033.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0034.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0034.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0034.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0035.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0035.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0035.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0036.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0036.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0036.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0037.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0037.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0037.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0038.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0038.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0038.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0039.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0039.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0039.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0040.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0040.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0040.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0041.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0041.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0041.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0042.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0042.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0042.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0043.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0043.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0043.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0044.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0044.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0044.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0045.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0045.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0045.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0046.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0046.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0046.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0047.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0047.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0047.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0048.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0048.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0048.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0049.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0049.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0049.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0050.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0050.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0050.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0051.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0051.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0051.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0052.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0052.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0052.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0053.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0053.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0053.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0054.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0054.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0054.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0055.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0055.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0055.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0056.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0056.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0056.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0057.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0057.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0057.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0058.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0058.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0058.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0059.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0059.cu
new file mode 100644
index 00000000..fcaac275
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0059.cu
@@ -0,0 +1,535 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 41984
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 43008
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 41984);
+    const int smem_csq_addr = smem + 41984;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 1; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 1; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 1; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0060.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0060.cu
new file mode 100644
index 00000000..254d8e9d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0060.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0061.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0061.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0061.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0062.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0062.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0062.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0063.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0063.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0063.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0064.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0064.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0064.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0065.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0065.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0065.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0066.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0066.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0066.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0067.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0067.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0067.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0068.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0068.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0068.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0069.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0069.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0069.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0070.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0070.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0070.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0071.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0071.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0071.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0072.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0072.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0072.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0073.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0073.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0073.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0074.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0074.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0074.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0075.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0075.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0075.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0076.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0076.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0076.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0077.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0077.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0077.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0078.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0078.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0078.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0079.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0079.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0079.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0080.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0080.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0080.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0081.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0081.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0081.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0082.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0082.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0082.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0083.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0083.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0083.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0084.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0084.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0084.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0085.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0085.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0085.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0086.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0086.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0086.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0087.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0087.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0087.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0088.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0088.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0088.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0089.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0089.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0089.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0090.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0090.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0090.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0091.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0091.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0091.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0092.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0092.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0092.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0093.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0093.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0093.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0094.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0094.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0094.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0095.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0095.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0095.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0096.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0096.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0096.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0097.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0097.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0097.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0098.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0098.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0098.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0099.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0099.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0099.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0100.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0100.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0100.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0101.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0101.cu
new file mode 100644
index 00000000..ea986bdf
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0101.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0102.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0102.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0102.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0103.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0103.cu
new file mode 100644
index 00000000..ea986bdf
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0103.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0104.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0104.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0104.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0105.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0105.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0105.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0106.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0106.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0106.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0107.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0107.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0107.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0108.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0108.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0108.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0109.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0109.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0109.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0110.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0110.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0110.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0111.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0111.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0111.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0112.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0112.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0112.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0113.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0113.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0113.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0114.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0114.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0114.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0115.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0115.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0115.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0116.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0116.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0116.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0117.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0117.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0117.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0118.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0118.cu
new file mode 100644
index 00000000..885f8507
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0118.cu
@@ -0,0 +1,649 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM0_OFFSET 0
+#define TMEM_SCORE_TMEM1_OFFSET 256
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C0_OFF 9216
+#define SMEM_SMEM_C0_STAGE_BYTES 32768
+#define SMEM_SMEM_C0_STRIDE 32768
+#define SMEM_SMEM_C1_OFF 41984
+#define SMEM_SMEM_C1_STAGE_BYTES 32768
+#define SMEM_SMEM_C1_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 74752
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 75776
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_paired_xreuse_dualtmem_producer_r47_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, unsigned long long* __restrict__ partial_keys, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c0_addr = smem + 9216;
+    __nv_bfloat16* smem_c1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 41984);
+    const int smem_c1_addr = smem + 41984;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 74752);
+    const int smem_csq_addr = smem + 74752;
+
+    // Mbarrier init (8 groups, 8 barriers)
+    // Mbarriers at smem_raw[0..64)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 64);
+    if (warp == 0) {
+        int _tmem_hold = smem + 64;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c0_full_addr (mbar_base + 16)
+    #define c0_empty_addr (mbar_base + 24)
+    #define c1_full_addr (mbar_base + 32)
+    #define c1_empty_addr (mbar_base + 40)
+    #define score_full_addr (mbar_base + 48)
+    #define score_empty_addr (mbar_base + 56)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem0 = taddr;
+    const int tmem_score_tmem1 = taddr + 256;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice * 2;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                int off_k0 = slice_k_start * 256;
+                int off_k1 = off_k0 + 256;
+                if ((float)compute_tid < 64.0f) {
+                    int csq_base0 = compute_tid * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k0 + csq_base0);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half0[4];
+                    csq_half0[0] = 0.5f * _vec_load_0[0];
+                    csq_half0[1] = 0.5f * _vec_load_0[1];
+                    csq_half0[2] = 0.5f * _vec_load_0[2];
+                    csq_half0[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base0 * 4), "f"(csq_half0[0]), "f"(csq_half0[1]), "f"(csq_half0[2]), "f"(csq_half0[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                #pragma unroll
+                for (int score_base = 0; score_base < 256; score_base += 128) {
+                    float _tmem_load_0[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                        : "r"(taddr + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int rep = 0; rep < 16.0f; rep++) {
+                        int local_reg = rep * 4;
+                        int col_base = score_base + rep * 8 + lane_pair * 2;
+                        float csq0 = smem_csq[col_base];
+                        float csq1 = smem_csq[col_base + 1];
+                        float d0 = _tmem_load_0[local_reg] - csq0;
+                        if (d0 > best0) {
+                            best0 = d0;
+                            idx0 = off_k0 + col_base;
+                        }
+                        float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                        if (d1 > best0) {
+                            best0 = d1;
+                            idx0 = off_k0 + col_base + 1;
+                        }
+                        float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                        if (d2 > best1) {
+                            best1 = d2;
+                            idx1 = off_k0 + col_base;
+                        }
+                        float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                        if (d3 > best1) {
+                            best1 = d3;
+                            idx1 = off_k0 + col_base + 1;
+                        }
+                    }
+                }
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if ((float)compute_tid < 64.0f) {
+                    int csq_base1 = compute_tid * 4;
+                    float _vec_load_1[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k1 + csq_base1);
+                        _vec_load_1[0 + 0] = _v4.x;
+                        _vec_load_1[0 + 1] = _v4.y;
+                        _vec_load_1[0 + 2] = _v4.z;
+                        _vec_load_1[0 + 3] = _v4.w;
+                    }
+                    float csq_half1[4];
+                    csq_half1[0] = 0.5f * _vec_load_1[0];
+                    csq_half1[1] = 0.5f * _vec_load_1[1];
+                    csq_half1[2] = 0.5f * _vec_load_1[2];
+                    csq_half1[3] = 0.5f * _vec_load_1[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base1 * 4), "f"(csq_half1[0]), "f"(csq_half1[1]), "f"(csq_half1[2]), "f"(csq_half1[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                #pragma unroll
+                for (int score_base_1 = 0; score_base_1 < 256; score_base_1 += 128) {
+                    float _tmem_load_1[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_1[63]))
+                        : "r"(taddr + 256 + (unsigned int)score_base_1)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int rep_1 = 0; rep_1 < 16.0f; rep_1++) {
+                        int local_reg_1 = rep_1 * 4;
+                        int col_base_1 = score_base_1 + rep_1 * 8 + lane_pair * 2;
+                        float csq0_1 = smem_csq[col_base_1];
+                        float csq1_1 = smem_csq[col_base_1 + 1];
+                        float d0_1 = _tmem_load_1[local_reg_1] - csq0_1;
+                        if (d0_1 > best0) {
+                            best0 = d0_1;
+                            idx0 = off_k1 + col_base_1;
+                        }
+                        float d1_1 = _tmem_load_1[local_reg_1 + 1] - csq1_1;
+                        if (d1_1 > best0) {
+                            best0 = d1_1;
+                            idx0 = off_k1 + col_base_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[local_reg_1 + 2] - csq0_1;
+                        if (d2_1 > best1) {
+                            best1 = d2_1;
+                            idx1 = off_k1 + col_base_1;
+                        }
+                        float d3_1 = _tmem_load_1[local_reg_1 + 3] - csq1_1;
+                        if (d3_1 > best1) {
+                            best1 = d3_1;
+                            idx1 = off_k1 + col_base_1 + 1;
+                        }
+                    }
+                }
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long shift32 = 32;
+                    unsigned long long mask64 = 4294967295;
+                    uint32_t _amf_u_0 = __float_as_uint(best0);
+                    uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+                    unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+                    unsigned long long key0 = (unsigned long long)_amf_enc_0 << shift32 | mask64 - (unsigned long long)idx0;
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((unsigned long long*)(partial_keys + partial_offset0)) = key0;
+                    uint32_t _amf_u_1 = __float_as_uint(best1);
+                    uint32_t _amf_mask_1 = -int32_t(_amf_u_1 >> 31) | 0x80000000u;
+                    unsigned int _amf_enc_1 = _amf_u_1 ^ _amf_mask_1;
+                    unsigned long long key1 = (unsigned long long)_amf_enc_1 << shift32 | mask64 - (unsigned long long)idx1;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((unsigned long long*)(partial_keys + partial_offset1)) = key1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c0_empty_0 = 1;
+            unsigned int _phase_c1_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1 * 2;
+                    int iter_k0 = slice_k_start_1;
+                    int iter_k1 = slice_k_start_1 + 1;
+                    int c_row0 = batch_1 * K + iter_k0 * 256;
+                    int c_row1 = batch_1 * K + iter_k1 * 256;
+                    #pragma unroll 7
+                    for (int feat_tile = 0; feat_tile < 7; feat_tile++) {
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                        mbarrier_wait(c0_empty_addr, _phase_c0_empty_0);
+                        _phase_c0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_c0_addr, c_tmap, 0, c_row0, feat_tile, c0_full_addr);
+                        mbarrier_arrive_expect_tx(c0_full_addr, 32768);
+                        mbarrier_wait(c1_empty_addr, _phase_c1_empty_0);
+                        _phase_c1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_c1_addr, c_tmap, 0, c_row1, feat_tile, c1_full_addr);
+                        mbarrier_arrive_expect_tx(c1_full_addr, 32768);
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c0_full_0 = 0;
+            unsigned int _phase_c1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 7
+                for (int feat_tile_1 = 0; feat_tile_1 < 7; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c0_full_addr, _phase_c0_full_0);
+                    _phase_c0_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c0_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem0), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(c0_empty_addr);
+                    mbarrier_wait(c1_full_addr, _phase_c1_full_0);
+                    _phase_c1_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c1_addr;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem1), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(c1_empty_addr);
+                    elect_commit(x_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0119.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0119.cu
new file mode 100644
index 00000000..c94c14c1
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0119.cu
@@ -0,0 +1,63 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 64
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(64) void
+kernel_flash_kmeans_assign_highd_paired_ownerreduce_r39_reduce1_unroll_v1(unsigned long long* __restrict__ partial_keys, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        unsigned long long best_key = 0;
+        #pragma unroll 8
+        for (int iter_slice = 0; iter_slice < 8; iter_slice++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            unsigned long long key = partial_keys[partial_offset];
+            if (key > best_key) {
+                best_key = key;
+            }
+        }
+        unsigned long long mask64 = 4294967295;
+        unsigned long long inv_idx = best_key & mask64;
+        unsigned long long idx_u64 = mask64 - inv_idx;
+        int idx = (int)idx_u64;
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0120.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0120.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0120.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0121.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0121.cu
new file mode 100644
index 00000000..0d005883
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0121.cu
@@ -0,0 +1,543 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 41984
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 43008
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_paired_packedpartial_producer_7b3c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, unsigned long long* __restrict__ partial_keys, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 41984);
+    const int smem_csq_addr = smem + 41984;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice * 2;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 2; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long shift32 = 32;
+                    unsigned long long mask64 = 4294967295;
+                    uint32_t _amf_u_0 = __float_as_uint(best0);
+                    uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+                    unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+                    unsigned long long key0 = (unsigned long long)_amf_enc_0 << shift32 | mask64 - (unsigned long long)idx0;
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((unsigned long long*)(partial_keys + partial_offset0)) = key0;
+                    uint32_t _amf_u_1 = __float_as_uint(best1);
+                    uint32_t _amf_mask_1 = -int32_t(_amf_u_1 >> 31) | 0x80000000u;
+                    unsigned int _amf_enc_1 = _amf_u_1 ^ _amf_mask_1;
+                    unsigned long long key1 = (unsigned long long)_amf_enc_1 << shift32 | mask64 - (unsigned long long)idx1;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((unsigned long long*)(partial_keys + partial_offset1)) = key1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1 * 2;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 2; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2 * 2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 2; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0122.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0122.cu
new file mode 100644
index 00000000..cf89ea2d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0122.cu
@@ -0,0 +1,71 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_paired_packedpartial_reduce_r2_7b3c_v1(unsigned long long* __restrict__ partial_keys, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 2;
+    int row_lane = tid % 2;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        unsigned long long best_key = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 2) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            unsigned long long key = partial_keys[partial_offset];
+            if (key > best_key) {
+                best_key = key;
+            }
+        }
+        unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+        unsigned long long peer_key = _shfl_xor_0;
+        if (peer_key > best_key) {
+            best_key = peer_key;
+        }
+        if (row_lane == 0) {
+            unsigned long long mask64 = 4294967295;
+            unsigned long long inv_idx = best_key & mask64;
+            unsigned long long idx_u64 = mask64 - inv_idx;
+            int idx = (int)idx_u64;
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0123.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0123.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0123.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0124.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0124.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0124.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0125.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0125.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0125.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0126.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0126.cu
new file mode 100644
index 00000000..3e4e2222
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0126.cu
@@ -0,0 +1,483 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORES_OFFSET 0
+#define NUM_X_PIPE_STAGES 3
+#define NUM_C_PIPE_STAGES 4
+#define NUM_SCORE_PIPE_STAGES 4
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 13312
+#define SMEM_SMEM_C_STAGE_BYTES 2048
+#define SMEM_SMEM_C_STRIDE 2048
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 2048
+#define SMEM_SMEM_CSQ_STRIDE 2048
+#define SMEM_TOTAL 23552
+#define THREADS 192
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 13312);
+    const int smem_c_addr = smem + 13312;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 22 barriers)
+    // Mbarriers at smem_raw[0..176)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // --- pipeline 'x_pipe' ---
+        // x_full: 3 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        mbarrier_init_pred(smem + 8, 1, leader);
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x_empty: 3 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        mbarrier_init_pred(smem + 32, 1, leader);
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // --- pipeline 'c_pipe' ---
+        // c_full: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        mbarrier_init_pred(smem + 56, 1, leader);
+        mbarrier_init_pred(smem + 64, 1, leader);
+        mbarrier_init_pred(smem + 72, 1, leader);
+        // c_empty: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 80, 1, leader);
+        mbarrier_init_pred(smem + 88, 1, leader);
+        mbarrier_init_pred(smem + 96, 1, leader);
+        mbarrier_init_pred(smem + 104, 1, leader);
+        // --- pipeline 'score_pipe' ---
+        // score_full: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 112, 1, leader);
+        mbarrier_init_pred(smem + 120, 1, leader);
+        mbarrier_init_pred(smem + 128, 1, leader);
+        mbarrier_init_pred(smem + 136, 1, leader);
+        // score_empty: 4 barriers, init_count=4
+        mbarrier_init_pred(smem + 144, 4, leader);
+        mbarrier_init_pred(smem + 152, 4, leader);
+        mbarrier_init_pred(smem + 160, 4, leader);
+        mbarrier_init_pred(smem + 168, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 176);
+    if (warp == 0) {
+        int _tmem_hold = smem + 176;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 48)
+    #define c_empty_addr (mbar_base + 80)
+    #define score_full_addr (mbar_base + 112)
+    #define score_empty_addr (mbar_base + 144)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_scores = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            unsigned int x_stage = 0;
+            unsigned int c_stage = 0;
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty = 1;
+            unsigned int _phase_c_empty = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int x_row = batch * N + n_tile * 128;
+                        mbarrier_wait(x_empty_addr + (x_stage) * 8, _phase_x_empty);
+                        tma_3d_gmem2smem(smem_x_addr + x_stage * 4096, x_tmap, 0, x_row, 0, x_full_addr + (x_stage) * 8);
+                        mbarrier_arrive_expect_tx(x_full_addr + (x_stage) * 8, 4096);
+                        x_stage = (x_stage + 1) % 3;
+                        if (x_stage == 0) { _phase_x_empty ^= 1; }
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int c_row = batch * K + iter_k * 64;
+                            mbarrier_wait(c_empty_addr + (c_stage) * 8, _phase_c_empty);
+                            tma_3d_gmem2smem(smem_c_addr + c_stage * 2048, c_tmap, 0, c_row, 0, c_full_addr + (c_stage) * 8);
+                            mbarrier_arrive_expect_tx(c_full_addr + (c_stage) * 8, 2048);
+                            c_stage = (c_stage + 1) % 4;
+                            if (c_stage == 0) { _phase_c_empty ^= 1; }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            unsigned int x_stage_1 = 0;
+            unsigned int c_stage_1 = 0;
+            unsigned int score_stage = 0;
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full = 0;
+            unsigned int _phase_c_full = 0;
+            unsigned int _phase_score_empty = 1;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr + (x_stage_1) * 8, _phase_x_full);
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(c_full_addr + (c_stage_1) * 8, _phase_c_full);
+                    mbarrier_wait(score_empty_addr + (score_stage) * 8, _phase_score_empty);
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr + x_stage_1 * 4096;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr + c_stage_1 * 2048;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    mma_ss_step(_mma_a_lo_0, _mma_b_lo_0, (tmem_scores + (score_stage * 64)), 135267472, 0, 0xC0004010U, 0xC0004010U);
+                    elect_commit(score_full_addr + (score_stage) * 8);
+                    elect_commit(c_empty_addr + (c_stage_1) * 8);
+                    c_stage_1 = (c_stage_1 + 1) % 4;
+                    if (c_stage_1 == 0) { _phase_c_full ^= 1; }
+                    score_stage = (score_stage + 1) % 4;
+                    if (score_stage == 0) { _phase_score_empty ^= 1; }
+                }
+                if (elect_sync()) {
+                    mbarrier_arrive(x_empty_addr + (x_stage_1) * 8);
+                }
+                x_stage_1 = (x_stage_1 + 1) % 3;
+                if (x_stage_1 == 0) { _phase_x_full ^= 1; }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            unsigned int score_stage_1 = 0;
+            int num_tiles_2 = B * num_n_tiles;
+            int row = warp % 4 * 32 + lane;
+            int row_base = warp % 4 * 32 << 16;
+            unsigned int _phase_score_full = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int out_offset = batch_1 * N + n_tile_1 * 128 + row;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                float best2 = -3.4e+38f;
+                float best3 = -3.4e+38f;
+                int idx0 = 0;
+                int idx1 = 0;
+                int idx2 = 0;
+                int idx3 = 0;
+                int csq_base = row * 4;
+                float _vec_load_0[4];
+                {
+                    float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + csq_base);
+                    _vec_load_0[0 + 0] = _v4.x;
+                    _vec_load_0[0 + 1] = _v4.y;
+                    _vec_load_0[0 + 2] = _v4.z;
+                    _vec_load_0[0 + 3] = _v4.w;
+                }
+                float csq_half[4];
+                csq_half[0] = 0.5f * _vec_load_0[0];
+                csq_half[1] = 0.5f * _vec_load_0[1];
+                csq_half[2] = 0.5f * _vec_load_0[2];
+                csq_half[3] = 0.5f * _vec_load_0[3];
+                asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(smem_csq_addr + (unsigned int)(csq_base * 4)), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int k_base = iter_k_1 * 64;
+                    mbarrier_wait(score_full_addr + (score_stage_1) * 8, _phase_score_full);
+                    float _tmem_load_0[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x64.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63])
+                        : "r"(taddr + (unsigned int)row_base + score_stage_1 * 64)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int j_base = 0; j_base < 64; j_base += 4) {
+                        float d0 = _tmem_load_0[j_base] - smem_csq[k_base + j_base];
+                        if (d0 > best0) {
+                            best0 = d0;
+                            idx0 = k_base + j_base;
+                        }
+                        float d1 = _tmem_load_0[j_base + 1] - smem_csq[k_base + j_base + 1];
+                        if (d1 > best1) {
+                            best1 = d1;
+                            idx1 = k_base + j_base + 1;
+                        }
+                        float d2 = _tmem_load_0[j_base + 2] - smem_csq[k_base + j_base + 2];
+                        if (d2 > best2) {
+                            best2 = d2;
+                            idx2 = k_base + j_base + 2;
+                        }
+                        float d3 = _tmem_load_0[j_base + 3] - smem_csq[k_base + j_base + 3];
+                        if (d3 > best3) {
+                            best3 = d3;
+                            idx3 = k_base + j_base + 3;
+                        }
+                    }
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr + (score_stage_1) * 8);
+                    }
+                    score_stage_1 = (score_stage_1 + 1) % 4;
+                    if (score_stage_1 == 0) { _phase_score_full ^= 1; }
+                }
+                if (best1 > best0) {
+                    best0 = best1;
+                    idx0 = idx1;
+                }
+                if (best3 > best2) {
+                    best2 = best3;
+                    idx2 = idx3;
+                }
+                if (best2 > best0) {
+                    best0 = best2;
+                    idx0 = idx2;
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                *((int*)(out + out_offset)) = idx0;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0127.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0127.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0127.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0128.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0128.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0128.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0129.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0129.cu
new file mode 100644
index 00000000..3778419b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0129.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 2048
+#define SMEM_SMEM_CSQ_STRIDE 2048
+#define SMEM_TOTAL 52224
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_2d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.2d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3}], [%4];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_2d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_2d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                int csq_base = (warp % 4 * 32 + lane) * 4;
+                float _vec_load_0[4];
+                {
+                    float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + csq_base);
+                    _vec_load_0[0 + 0] = _v4.x;
+                    _vec_load_0[0 + 1] = _v4.y;
+                    _vec_load_0[0 + 2] = _v4.z;
+                    _vec_load_0[0 + 3] = _v4.w;
+                }
+                float csq_half[4];
+                csq_half[0] = 0.5f * _vec_load_0[0];
+                csq_half[1] = 0.5f * _vec_load_0[1];
+                csq_half[2] = 0.5f * _vec_load_0[2];
+                csq_half[3] = 0.5f * _vec_load_0[3];
+                asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (off_k_1 + score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (off_k_1 + score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0130.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0130.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0130.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0131.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0131.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0131.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0132.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0132.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0132.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0133.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0133.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0133.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0134.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0134.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0134.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0135.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0135.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0135.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0136.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0136.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0136.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0137.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0137.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0137.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0138.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0138.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0138.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0139.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0139.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0139.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0140.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0140.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0140.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0141.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0141.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0141.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0142.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0142.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0142.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0143.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0143.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0143.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0144.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0144.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0144.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0145.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0145.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0145.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0146.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0146.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0146.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0147.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0147.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0147.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0148.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0148.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0148.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0149.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0149.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0149.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0150.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0150.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0150.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0151.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0151.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0151.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0152.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0152.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0152.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0153.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0153.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0153.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0154.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0154.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0154.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0155.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0155.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0155.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0159.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0159.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0159.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0160.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0160.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0160.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0163.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0163.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0163.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0164.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0164.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0164.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0166.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0166.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0166.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0167.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0167.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0167.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0168.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0168.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0168.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0169.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0169.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0169.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0170.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0170.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0170.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0171.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0171.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0171.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0172.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0172.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0172.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0173.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0173.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0173.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0174.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0174.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0174.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0175.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0175.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0175.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0176.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0176.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0176.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0177.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0177.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0177.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0178.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0178.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0178.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0179.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0179.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0179.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0180.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0180.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0180.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0181.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0181.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0181.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0182.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0182.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0182.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0183.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0183.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0183.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0184.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0184.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0184.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0185.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0185.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0185.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0186.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0186.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0186.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0187.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0187.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0187.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0188.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0188.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0188.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0189.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0189.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0189.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0190.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0190.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0190.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0191.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0191.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0191.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0192.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0192.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0192.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0193.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0193.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0193.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0194.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0194.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0194.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0195.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0195.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0195.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0196.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0196.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0196.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0197.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0197.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0197.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0198.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0198.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0198.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0199.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0199.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0199.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0200.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0200.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0200.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0201.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0201.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0201.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0202.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0202.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0202.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0203.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0203.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0203.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0204.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0204.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0204.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0205.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0205.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0205.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0206.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0206.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0206.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0207.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0207.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0207.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0208.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0208.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0208.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0209.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0209.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0209.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0210.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0210.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0210.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0211.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0211.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0211.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0212.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0212.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0212.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0213.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0213.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0213.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0214.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0214.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0214.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0215.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0215.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0215.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0216.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0216.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0216.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0217.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0217.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0217.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0218.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0218.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0218.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0219.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0219.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0219.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0220.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0220.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0220.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0221.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0221.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0221.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0222.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0222.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0222.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0223.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0223.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0223.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0224.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0224.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0224.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0225.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0225.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0225.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0226.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0226.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0226.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0227.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0227.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0227.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0228.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0228.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0228.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0229.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0229.cu
new file mode 100644
index 00000000..fcc7623c
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0229.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 5120
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 22528
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 5120);
+    const int smem_c_addr = smem + 5120;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int num_tiles = B * num_n_tiles;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                int batch = tile_idx / (unsigned int)num_n_tiles;
+                int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                int off_n = n_tile * 64;
+                int global_n0 = off_n + row0;
+                int global_n1 = off_n + row1;
+                int out_offset0 = batch * N + global_n0;
+                int out_offset1 = batch * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = 0;
+                int idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    if (global_n0 < N) {
+                        *((int*)(out + out_offset0)) = idx0;
+                    }
+                    if (global_n1 < N) {
+                        *((int*)(out + out_offset1)) = idx1;
+                    }
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                    int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                    int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                    int off_n_1 = n_tile_1 * 64;
+                    int x_row = batch_1 * N + off_n_1;
+                    #pragma unroll 1
+                    for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int iter_d = 0; iter_d < 7; iter_d++) {
+                            int d_group = iter_d;
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 4096);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 7; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0230.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0230.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0230.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0231.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0231.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0231.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0232.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0232.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0232.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0233.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0233.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0233.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0234.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0234.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0234.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0235.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0235.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0235.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0236.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0236.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0236.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0237.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0237.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0237.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0238.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0238.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0238.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0239.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0239.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0239.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0240.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0240.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0240.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0241.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0241.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0241.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0242.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0242.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0242.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0243.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0243.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0243.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0244.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0244.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0244.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0245.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0245.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0245.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0246.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0246.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0246.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0247.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0247.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0247.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0248.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0248.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0248.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0249.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0249.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0249.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0250.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0250.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0250.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0251.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0251.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0251.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0252.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0252.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0252.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0253.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0253.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0253.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0254.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0254.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0254.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0255.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0255.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0255.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0256.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0256.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0256.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0257.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0257.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0257.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0258.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0258.cu
new file mode 100644
index 00000000..3f16db31
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0258.cu
@@ -0,0 +1,525 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 5120
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 22528
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d480_splitk_partial_d32k256_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 5120);
+    const int smem_c_addr = smem + 5120;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 1; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 32;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 1; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 4096);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 32;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 1; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0259.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0259.cu
new file mode 100644
index 00000000..c242dff7
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0259.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d480_splitk_reduce_d32k256_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0260.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0260.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0260.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0261.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0261.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0261.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0262.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0262.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0262.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0263.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0263.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0263.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0264.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0264.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0264.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0265.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0265.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0265.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0266.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0266.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0266.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0267.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0267.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0267.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0268.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0268.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0268.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0269.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0269.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0269.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0270.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0270.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0270.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0271.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0271.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0271.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0272.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0272.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0272.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0273.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0273.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0273.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0274.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0274.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0274.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0275.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0275.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0275.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0276.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0276.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0276.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0277.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0277.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0277.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0278.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0278.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0278.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0279.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0279.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0279.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0280.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0280.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0280.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0281.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0281.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0281.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0282.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0282.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0282.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0283.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0283.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0283.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0284.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0284.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0284.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0285.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0285.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0285.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0286.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0286.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0286.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0287.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0287.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0287.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0288.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0288.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0288.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0289.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0289.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0289.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0290.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0290.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0290.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0291.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0291.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0291.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0292.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0292.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0292.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0293.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0293.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0293.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0294.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0294.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0294.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0295.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0295.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0295.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0296.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0296.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0296.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0297.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0297.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0297.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0298.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0298.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0298.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0299.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0299.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0299.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0300.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0300.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0300.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0301.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0301.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0301.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0302.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0302.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0302.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0303.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0303.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0303.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0304.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0304.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0304.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0305.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0305.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0305.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0306.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0306.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0306.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0307.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0307.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0307.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0308.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0308.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0308.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0309.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0309.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0309.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0310.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0310.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0310.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0311.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0311.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0311.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0312.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0312.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0312.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0313.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0313.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0313.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0314.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0314.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0314.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0315.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0315.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0315.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0316.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0316.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0316.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0317.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0317.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0317.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0318.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0318.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0318.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0319.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0319.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0319.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0320.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0320.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0320.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0321.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0321.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0321.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0322.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0322.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0322.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0323.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0323.cu
new file mode 100644
index 00000000..f6311654
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0323.cu
@@ -0,0 +1,535 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 41984
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 43008
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g2r4_b5a6_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 41984);
+    const int smem_csq_addr = smem + 41984;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice * 2;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 2; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1 * 2;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 2; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2 * 2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 2; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0324.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0324.cu
new file mode 100644
index 00000000..461424c3
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0324.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g2r4_b5a6_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0325.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0325.cu
new file mode 100644
index 00000000..6d37a9aa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0325.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_8de8_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0326.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0326.cu
new file mode 100644
index 00000000..c552357a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0326.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_8de8_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0327.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0327.cu
new file mode 100644
index 00000000..3c2f58da
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0327.cu
@@ -0,0 +1,531 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitd_6fcf_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0328.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0328.cu
new file mode 100644
index 00000000..fcaac275
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0328.cu
@@ -0,0 +1,535 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 41984
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 43008
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_highd_splitk_partial_blockn64_g1r4_streamdep_r63_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 41984);
+    const int smem_csq_addr = smem + 41984;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 1; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 64;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 1; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 64;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 1; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0329.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0329.cu
new file mode 100644
index 00000000..254d8e9d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0329.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_highd_splitk_reduce_blockn64_g1r4_streamdep_r63_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0330.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0330.cu
new file mode 100644
index 00000000..3e4e2222
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0330.cu
@@ -0,0 +1,483 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORES_OFFSET 0
+#define NUM_X_PIPE_STAGES 3
+#define NUM_C_PIPE_STAGES 4
+#define NUM_SCORE_PIPE_STAGES 4
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 13312
+#define SMEM_SMEM_C_STAGE_BYTES 2048
+#define SMEM_SMEM_C_STRIDE 2048
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 2048
+#define SMEM_SMEM_CSQ_STRIDE 2048
+#define SMEM_TOTAL 23552
+#define THREADS 192
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_d16_pipeline4_08f9_v4(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 13312);
+    const int smem_c_addr = smem + 13312;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 22 barriers)
+    // Mbarriers at smem_raw[0..176)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // --- pipeline 'x_pipe' ---
+        // x_full: 3 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        mbarrier_init_pred(smem + 8, 1, leader);
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x_empty: 3 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        mbarrier_init_pred(smem + 32, 1, leader);
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // --- pipeline 'c_pipe' ---
+        // c_full: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        mbarrier_init_pred(smem + 56, 1, leader);
+        mbarrier_init_pred(smem + 64, 1, leader);
+        mbarrier_init_pred(smem + 72, 1, leader);
+        // c_empty: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 80, 1, leader);
+        mbarrier_init_pred(smem + 88, 1, leader);
+        mbarrier_init_pred(smem + 96, 1, leader);
+        mbarrier_init_pred(smem + 104, 1, leader);
+        // --- pipeline 'score_pipe' ---
+        // score_full: 4 barriers, init_count=1
+        mbarrier_init_pred(smem + 112, 1, leader);
+        mbarrier_init_pred(smem + 120, 1, leader);
+        mbarrier_init_pred(smem + 128, 1, leader);
+        mbarrier_init_pred(smem + 136, 1, leader);
+        // score_empty: 4 barriers, init_count=4
+        mbarrier_init_pred(smem + 144, 4, leader);
+        mbarrier_init_pred(smem + 152, 4, leader);
+        mbarrier_init_pred(smem + 160, 4, leader);
+        mbarrier_init_pred(smem + 168, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 176);
+    if (warp == 0) {
+        int _tmem_hold = smem + 176;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 48)
+    #define c_empty_addr (mbar_base + 80)
+    #define score_full_addr (mbar_base + 112)
+    #define score_empty_addr (mbar_base + 144)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_scores = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            unsigned int x_stage = 0;
+            unsigned int c_stage = 0;
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty = 1;
+            unsigned int _phase_c_empty = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int x_row = batch * N + n_tile * 128;
+                        mbarrier_wait(x_empty_addr + (x_stage) * 8, _phase_x_empty);
+                        tma_3d_gmem2smem(smem_x_addr + x_stage * 4096, x_tmap, 0, x_row, 0, x_full_addr + (x_stage) * 8);
+                        mbarrier_arrive_expect_tx(x_full_addr + (x_stage) * 8, 4096);
+                        x_stage = (x_stage + 1) % 3;
+                        if (x_stage == 0) { _phase_x_empty ^= 1; }
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int c_row = batch * K + iter_k * 64;
+                            mbarrier_wait(c_empty_addr + (c_stage) * 8, _phase_c_empty);
+                            tma_3d_gmem2smem(smem_c_addr + c_stage * 2048, c_tmap, 0, c_row, 0, c_full_addr + (c_stage) * 8);
+                            mbarrier_arrive_expect_tx(c_full_addr + (c_stage) * 8, 2048);
+                            c_stage = (c_stage + 1) % 4;
+                            if (c_stage == 0) { _phase_c_empty ^= 1; }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            unsigned int x_stage_1 = 0;
+            unsigned int c_stage_1 = 0;
+            unsigned int score_stage = 0;
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full = 0;
+            unsigned int _phase_c_full = 0;
+            unsigned int _phase_score_empty = 1;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr + (x_stage_1) * 8, _phase_x_full);
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(c_full_addr + (c_stage_1) * 8, _phase_c_full);
+                    mbarrier_wait(score_empty_addr + (score_stage) * 8, _phase_score_empty);
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr + x_stage_1 * 4096;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr + c_stage_1 * 2048;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    mma_ss_step(_mma_a_lo_0, _mma_b_lo_0, (tmem_scores + (score_stage * 64)), 135267472, 0, 0xC0004010U, 0xC0004010U);
+                    elect_commit(score_full_addr + (score_stage) * 8);
+                    elect_commit(c_empty_addr + (c_stage_1) * 8);
+                    c_stage_1 = (c_stage_1 + 1) % 4;
+                    if (c_stage_1 == 0) { _phase_c_full ^= 1; }
+                    score_stage = (score_stage + 1) % 4;
+                    if (score_stage == 0) { _phase_score_empty ^= 1; }
+                }
+                if (elect_sync()) {
+                    mbarrier_arrive(x_empty_addr + (x_stage_1) * 8);
+                }
+                x_stage_1 = (x_stage_1 + 1) % 3;
+                if (x_stage_1 == 0) { _phase_x_full ^= 1; }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            unsigned int score_stage_1 = 0;
+            int num_tiles_2 = B * num_n_tiles;
+            int row = warp % 4 * 32 + lane;
+            int row_base = warp % 4 * 32 << 16;
+            unsigned int _phase_score_full = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int out_offset = batch_1 * N + n_tile_1 * 128 + row;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                float best2 = -3.4e+38f;
+                float best3 = -3.4e+38f;
+                int idx0 = 0;
+                int idx1 = 0;
+                int idx2 = 0;
+                int idx3 = 0;
+                int csq_base = row * 4;
+                float _vec_load_0[4];
+                {
+                    float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + csq_base);
+                    _vec_load_0[0 + 0] = _v4.x;
+                    _vec_load_0[0 + 1] = _v4.y;
+                    _vec_load_0[0 + 2] = _v4.z;
+                    _vec_load_0[0 + 3] = _v4.w;
+                }
+                float csq_half[4];
+                csq_half[0] = 0.5f * _vec_load_0[0];
+                csq_half[1] = 0.5f * _vec_load_0[1];
+                csq_half[2] = 0.5f * _vec_load_0[2];
+                csq_half[3] = 0.5f * _vec_load_0[3];
+                asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(smem_csq_addr + (unsigned int)(csq_base * 4)), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int k_base = iter_k_1 * 64;
+                    mbarrier_wait(score_full_addr + (score_stage_1) * 8, _phase_score_full);
+                    float _tmem_load_0[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x64.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63])
+                        : "r"(taddr + (unsigned int)row_base + score_stage_1 * 64)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int j_base = 0; j_base < 64; j_base += 4) {
+                        float d0 = _tmem_load_0[j_base] - smem_csq[k_base + j_base];
+                        if (d0 > best0) {
+                            best0 = d0;
+                            idx0 = k_base + j_base;
+                        }
+                        float d1 = _tmem_load_0[j_base + 1] - smem_csq[k_base + j_base + 1];
+                        if (d1 > best1) {
+                            best1 = d1;
+                            idx1 = k_base + j_base + 1;
+                        }
+                        float d2 = _tmem_load_0[j_base + 2] - smem_csq[k_base + j_base + 2];
+                        if (d2 > best2) {
+                            best2 = d2;
+                            idx2 = k_base + j_base + 2;
+                        }
+                        float d3 = _tmem_load_0[j_base + 3] - smem_csq[k_base + j_base + 3];
+                        if (d3 > best3) {
+                            best3 = d3;
+                            idx3 = k_base + j_base + 3;
+                        }
+                    }
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr + (score_stage_1) * 8);
+                    }
+                    score_stage_1 = (score_stage_1 + 1) % 4;
+                    if (score_stage_1 == 0) { _phase_score_full ^= 1; }
+                }
+                if (best1 > best0) {
+                    best0 = best1;
+                    idx0 = idx1;
+                }
+                if (best3 > best2) {
+                    best2 = best3;
+                    idx2 = idx3;
+                }
+                if (best2 > best0) {
+                    best0 = best2;
+                    idx0 = idx2;
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                *((int*)(out + out_offset)) = idx0;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0331.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0331.cu
new file mode 100644
index 00000000..3778419b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0331.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 2048
+#define SMEM_SMEM_CSQ_STRIDE 2048
+#define SMEM_TOTAL 52224
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_2d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.2d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3}], [%4];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_raw_tma_08f9_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_2d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_2d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                int csq_base = (warp % 4 * 32 + lane) * 4;
+                float _vec_load_0[4];
+                {
+                    float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + csq_base);
+                    _vec_load_0[0 + 0] = _v4.x;
+                    _vec_load_0[0 + 1] = _v4.y;
+                    _vec_load_0[0 + 2] = _v4.z;
+                    _vec_load_0[0 + 3] = _v4.w;
+                }
+                float csq_half[4];
+                csq_half[0] = 0.5f * _vec_load_0[0];
+                csq_half[1] = 0.5f * _vec_load_0[1];
+                csq_half[2] = 0.5f * _vec_load_0[2];
+                csq_half[3] = 0.5f * _vec_load_0[3];
+                asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (off_k_1 + score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (off_k_1 + score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0332.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0332.cu
new file mode 100644
index 00000000..fe28d85a
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0332.cu
@@ -0,0 +1,577 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_direct_9c0d_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            int lane_start = tid;
+            const int x_vecs = 1024;
+            const int c_vecs = 2048;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                int batch = tile_idx / (unsigned int)num_n_tiles;
+                int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                int off_n = n_tile * 128;
+                int x_row_base = batch * N + off_n;
+                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                _phase_x_empty_0 ^= 1;
+                #pragma unroll 1
+                for (unsigned int vec_idx = lane_start; vec_idx < x_vecs; vec_idx += 32) {
+                    int d_pad = vec_idx % 8 * 8;
+                    int row = vec_idx / 8;
+                    float vals[8];
+                    unsigned int packed[4];
+                    if (d_pad < D) {
+                        {
+                            const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + ((x_row_base + row) * D + d_pad) + 0);
+                            uint4 _vld_0[1];
+                            #pragma unroll
+                            for (int _blk = 0; _blk < 1; _blk++) {
+                                _vld_0[_blk] = _vptr_0[_blk];
+                                __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                                #pragma unroll
+                                for (int _j = 0; _j < 8; _j++)
+                                    vals[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                            }
+                        }
+                    } else {
+                        #pragma unroll
+                        for (int vi = 0; vi < 8; vi++) {
+                            vals[vi] = 0.0f;
+                        }
+                    }
+                    #pragma unroll
+                    for (int _lp = 0; _lp < 4; _lp++) {
+                        __nv_bfloat162 _bf2 = __float22bfloat162_rn(make_float2(vals[_lp*2 + 0], vals[_lp*2+1 + 0]));
+                        packed[_lp] = *(uint32_t*)&_bf2;
+                    }
+                    int x_addr = (smem_x_addr + (unsigned int)(d_pad / 64 * 16384 + row * 128 + d_pad % 64 * 2 ^ (d_pad / 64 * 16384 + row * 128 + d_pad % 64 * 2 >> 7 & 7) << 4));
+                    asm volatile("st.shared.v4.b32 [%0], {%1,%2,%3,%4};" :: "r"(x_addr), "r"(packed[0]), "r"(packed[1]), "r"(packed[2]), "r"(packed[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(32));
+                if (warp == 0) {
+                    if (elect_sync()) {
+                        asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                        mbarrier_arrive(x_full_addr);
+                    }
+                }
+                #pragma unroll 1
+                for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                    int off_k = iter_k * 256;
+                    int c_row_base = batch * K + off_k;
+                    mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                    _phase_c_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (unsigned int vec_idx_1 = lane_start; vec_idx_1 < c_vecs; vec_idx_1 += 32) {
+                        int d_pad_1 = vec_idx_1 % 8 * 8;
+                        int row_1 = vec_idx_1 / 8;
+                        float vals_1[8];
+                        unsigned int packed_1[4];
+                        if (d_pad_1 < D) {
+                            {
+                                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + ((c_row_base + row_1) * D + d_pad_1) + 0);
+                                uint4 _vld_1[1];
+                                #pragma unroll
+                                for (int _blk = 0; _blk < 1; _blk++) {
+                                    _vld_1[_blk] = _vptr_1[_blk];
+                                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                                    #pragma unroll
+                                    for (int _j = 0; _j < 8; _j++)
+                                        vals_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                                }
+                            }
+                        } else {
+                            #pragma unroll
+                            for (int vi_1 = 0; vi_1 < 8; vi_1++) {
+                                vals_1[vi_1] = 0.0f;
+                            }
+                        }
+                        #pragma unroll
+                        for (int _lp = 0; _lp < 4; _lp++) {
+                            __nv_bfloat162 _bf2 = __float22bfloat162_rn(make_float2(vals_1[_lp*2 + 0], vals_1[_lp*2+1 + 0]));
+                            packed_1[_lp] = *(uint32_t*)&_bf2;
+                        }
+                        int c_addr = (smem_c_addr + (unsigned int)(d_pad_1 / 64 * 32768 + row_1 * 128 + d_pad_1 % 64 * 2 ^ (d_pad_1 / 64 * 32768 + row_1 * 128 + d_pad_1 % 64 * 2 >> 7 & 7) << 4));
+                        asm volatile("st.shared.v4.b32 [%0], {%1,%2,%3,%4};" :: "r"(c_addr), "r"(packed_1[0]), "r"(packed_1[1]), "r"(packed_1[2]), "r"(packed_1[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(32));
+                    if (warp == 0) {
+                        if (elect_sync()) {
+                            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                            mbarrier_arrive(c_full_addr);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 10, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0333.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0333.cu
new file mode 100644
index 00000000..5b836885
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0333.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_microdim_pack_6cd2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 8 * 8;
+        int row = vec_idx / 8;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 8 * 8;
+        int row_1 = vec_idx_1 / 8;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0334.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0334.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0334.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0335.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0335.cu
new file mode 100644
index 00000000..df9612f5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0335.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_lowdim_pack_e50c_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 16 * 8;
+        int row = vec_idx / 16;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 16 * 8;
+        int row_1 = vec_idx_1 / 16;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0336.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0336.cu
new file mode 100644
index 00000000..1c18f40d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0336.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_microdim_6cd2_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0337.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0337.cu
new file mode 100644
index 00000000..bd103c07
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0337.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_lowdim_e50c_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0338.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0338.cu
new file mode 100644
index 00000000..b0ab1f24
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0338.cu
@@ -0,0 +1,139 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_gap_pad_pack_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int D_PAD, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int d_pad_vecs = D_PAD / 8;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % (unsigned int)d_pad_vecs * 8;
+        int row = vec_idx / (unsigned int)d_pad_vecs;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % (unsigned int)d_pad_vecs * 8;
+        int row_1 = vec_idx_1 / (unsigned int)d_pad_vecs;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0339.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0339.cu
new file mode 100644
index 00000000..a6df74d2
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0339.cu
@@ -0,0 +1,522 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 16384
+#define SMEM_SMEM_X_STRIDE 16384
+#define SMEM_SMEM_C_OFF 17408
+#define SMEM_SMEM_C_STAGE_BYTES 32768
+#define SMEM_SMEM_C_STRIDE 32768
+#define SMEM_SMEM_CSQ_OFF 50176
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 51200
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d64_direct_1p2gap_9f2a_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17408);
+    const int smem_c_addr = smem + 17408;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 50176);
+    const int smem_csq_addr = smem + 50176;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 16384);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 32768);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _tile_idx = bid; _tile_idx < num_tiles_1; _tile_idx += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int _iter_k = 0; _iter_k < K_tiles; _iter_k++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_2; tile_idx_1 += num_bids) {
+                int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    int off_k_1 = iter_k_1 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0340.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0340.cu
new file mode 100644
index 00000000..d5f77bfa
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0340.cu
@@ -0,0 +1,1133 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 32768
+#define SMEM_SMEM_X0_STRIDE 32768
+#define SMEM_SMEM_X1_OFF 33792
+#define SMEM_SMEM_X1_STAGE_BYTES 32768
+#define SMEM_SMEM_X1_STRIDE 32768
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 132096
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 133120
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v15(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_x1_addr = smem + 33792;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 132096);
+    const int smem_csq_addr = smem + 132096;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 32768);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x1_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr + 16384;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 32768;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0341.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0341.cu
new file mode 100644
index 00000000..de141964
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0341.cu
@@ -0,0 +1,561 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 32768
+#define SMEM_SMEM_X_STRIDE 32768
+#define SMEM_SMEM_C_OFF 33792
+#define SMEM_SMEM_C_STAGE_BYTES 65536
+#define SMEM_SMEM_C_STRIDE 65536
+#define SMEM_SMEM_CSQ_OFF 99328
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 100352
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_v10(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 33792);
+    const int smem_c_addr = smem + 33792;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 99328);
+    const int smem_csq_addr = smem + 99328;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 32768);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 65536);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0342.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0342.cu
new file mode 100644
index 00000000..bf486f4b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0342.cu
@@ -0,0 +1,639 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 65536
+#define SMEM_SMEM_X_STRIDE 65536
+#define SMEM_SMEM_C_OFF 66560
+#define SMEM_SMEM_C_STAGE_BYTES 131072
+#define SMEM_SMEM_C_STRIDE 131072
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d256_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 66560);
+    const int smem_c_addr = smem + 66560;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 65536);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 131072);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x_addr + 49152;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr + 98304;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0343.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0343.cu
new file mode 100644
index 00000000..17caae28
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0343.cu
@@ -0,0 +1,1211 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 512
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X0_OFF 1024
+#define SMEM_SMEM_X0_STAGE_BYTES 49152
+#define SMEM_SMEM_X0_STRIDE 49152
+#define SMEM_SMEM_X1_OFF 50176
+#define SMEM_SMEM_X1_STAGE_BYTES 49152
+#define SMEM_SMEM_X1_STRIDE 49152
+#define SMEM_SMEM_C_OFF 99328
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 197632
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 198656
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_splitd_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x0_addr = smem + 1024;
+    __nv_bfloat16* smem_x1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_x1_addr = smem + 50176;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 99328);
+    const int smem_c_addr = smem + 99328;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 197632);
+    const int smem_csq_addr = smem + 197632;
+
+    // Mbarrier init (10 groups, 10 barriers)
+    // Mbarriers at smem_raw[0..80)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x0_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // x1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // x1_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        // score0_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // score0_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 56, 4, leader);
+        // score1_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // score1_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 72, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (512 columns, 512 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 80);
+    if (warp == 0) {
+        int _tmem_hold = smem + 80;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(512) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x0_full_addr (mbar_base + 0)
+    #define x0_empty_addr (mbar_base + 8)
+    #define x1_full_addr (mbar_base + 16)
+    #define x1_empty_addr (mbar_base + 24)
+    #define c_full_addr (mbar_base + 32)
+    #define c_empty_addr (mbar_base + 40)
+    #define score0_full_addr (mbar_base + 48)
+    #define score0_empty_addr (mbar_base + 56)
+    #define score1_full_addr (mbar_base + 64)
+    #define score1_empty_addr (mbar_base + 72)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int pair_n_tiles = num_n_tiles / 2;
+            int num_tiles = B * pair_n_tiles;
+            unsigned int _phase_x0_empty_0 = 1;
+            unsigned int _phase_x1_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)pair_n_tiles;
+                        int pair_tile = tile_idx % (unsigned int)pair_n_tiles;
+                        int off_n0 = pair_tile * 256;
+                        int off_n1 = off_n0 + 128;
+                        int x_row0 = batch * N + off_n0;
+                        int x_row1 = batch * N + off_n1;
+                        mbarrier_wait(x0_empty_addr, _phase_x0_empty_0);
+                        _phase_x0_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x0_addr, x_tmap, 0, x_row0, 0, x0_full_addr);
+                        mbarrier_arrive_expect_tx(x0_full_addr, 49152);
+                        mbarrier_wait(x1_empty_addr, _phase_x1_empty_0);
+                        _phase_x1_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x1_addr, x_tmap, 0, x_row1, 0, x1_full_addr);
+                        mbarrier_arrive_expect_tx(x1_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int pair_n_tiles_1 = num_n_tiles / 2;
+            int num_tiles_1 = B * pair_n_tiles_1;
+            unsigned int _phase_x0_full_0 = 0;
+            unsigned int _phase_x1_full_0 = 0;
+            unsigned int _phase_score0_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            unsigned int _phase_score1_empty_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x0_full_addr, _phase_x0_full_0);
+                _phase_x0_full_0 ^= 1;
+                mbarrier_wait(x1_full_addr, _phase_x1_full_0);
+                _phase_x1_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score0_empty_addr, _phase_score0_empty_0);
+                    _phase_score0_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x0_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"((tmem_score_tmem + (256))), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x0_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"((tmem_score_tmem + (256))), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x0_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"((tmem_score_tmem + (256))), "r"(1));
+                    elect_commit(score0_full_addr);
+                    mbarrier_wait(score1_empty_addr, _phase_score1_empty_0);
+                    _phase_score1_empty_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_3 = smem_x1_addr;
+                    int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                    int _mma_b_addr_3 = smem_c_addr;
+                    int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_3), "r"(_mma_b_lo_3), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_4 = smem_x1_addr + 16384;
+                    int _mma_a_lo_4 = make_warp_uniform((_mma_a_addr_4 >> 4) & 0x3FFF);
+                    int _mma_b_addr_4 = smem_c_addr + 32768;
+                    int _mma_b_lo_4 = make_warp_uniform((_mma_b_addr_4 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_4), "r"(_mma_b_lo_4), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_5 = smem_x1_addr + 32768;
+                    int _mma_a_lo_5 = make_warp_uniform((_mma_a_addr_5 >> 4) & 0x3FFF);
+                    int _mma_b_addr_5 = smem_c_addr + 65536;
+                    int _mma_b_lo_5 = make_warp_uniform((_mma_b_addr_5 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_5), "r"(_mma_b_lo_5), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score1_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x0_empty_addr);
+                elect_commit(x1_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int pair_n_tiles_2 = num_n_tiles / 2;
+            int num_tiles_2 = B * pair_n_tiles_2;
+            unsigned int _phase_score0_full_0 = 0;
+            unsigned int _phase_score1_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)pair_n_tiles_2;
+                int pair_tile_1 = tile_idx_2 % (unsigned int)pair_n_tiles_2;
+                int off_n0_1 = pair_tile_1 * 256;
+                int off_n1_1 = off_n0_1 + 128;
+                int global_n0 = off_n0_1 + (warp % 4 * 32 + lane);
+                int global_n1 = off_n1_1 + (warp % 4 * 32 + lane);
+                int out_offset0 = batch_1 * N + global_n0;
+                int out_offset1 = batch_1 * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score0 = -3.4e+38f;
+                int best_idx0 = 0;
+                float best_score1 = -3.4e+38f;
+                int best_idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score0_full_addr, _phase_score0_full_0);
+                    _phase_score0_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 16) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        float csq_vals_hi[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 4) * 4));
+                        float d4 = _tmem_load_0[kk + 4] - csq_vals_hi[0];
+                        float d5 = _tmem_load_0[kk + 5] - csq_vals_hi[1];
+                        float best_45 = d4;
+                        int idx_45 = off_k_1 + score_base + kk + 4;
+                        if (d5 > best_45) {
+                            best_45 = d5;
+                            idx_45 = off_k_1 + score_base + kk + 5;
+                        }
+                        float d6 = _tmem_load_0[kk + 6] - csq_vals_hi[2];
+                        float d7 = _tmem_load_0[kk + 7] - csq_vals_hi[3];
+                        float best_67 = d6;
+                        int idx_67 = off_k_1 + score_base + kk + 6;
+                        if (d7 > best_67) {
+                            best_67 = d7;
+                            idx_67 = off_k_1 + score_base + kk + 7;
+                        }
+                        float best_hi = best_45;
+                        int idx_hi = idx_45;
+                        if (best_67 > best_hi) {
+                            best_hi = best_67;
+                            idx_hi = idx_67;
+                        }
+                        if (best_hi > best_group) {
+                            best_group = best_hi;
+                            idx_group = idx_hi;
+                        }
+                        float csq_vals_next[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 8) * 4));
+                        float d8 = _tmem_load_0[kk + 8] - csq_vals_next[0];
+                        float d9 = _tmem_load_0[kk + 9] - csq_vals_next[1];
+                        float best_89 = d8;
+                        int idx_89 = off_k_1 + score_base + kk + 8;
+                        if (d9 > best_89) {
+                            best_89 = d9;
+                            idx_89 = off_k_1 + score_base + kk + 9;
+                        }
+                        float d10 = _tmem_load_0[kk + 10] - csq_vals_next[2];
+                        float d11 = _tmem_load_0[kk + 11] - csq_vals_next[3];
+                        float best_1011 = d10;
+                        int idx_1011 = off_k_1 + score_base + kk + 10;
+                        if (d11 > best_1011) {
+                            best_1011 = d11;
+                            idx_1011 = off_k_1 + score_base + kk + 11;
+                        }
+                        float best_next = best_89;
+                        int idx_next = idx_89;
+                        if (best_1011 > best_next) {
+                            best_next = best_1011;
+                            idx_next = idx_1011;
+                        }
+                        float csq_vals_tail[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk + 12) * 4));
+                        float d12 = _tmem_load_0[kk + 12] - csq_vals_tail[0];
+                        float d13 = _tmem_load_0[kk + 13] - csq_vals_tail[1];
+                        float best_1213 = d12;
+                        int idx_1213 = off_k_1 + score_base + kk + 12;
+                        if (d13 > best_1213) {
+                            best_1213 = d13;
+                            idx_1213 = off_k_1 + score_base + kk + 13;
+                        }
+                        float d14 = _tmem_load_0[kk + 14] - csq_vals_tail[2];
+                        float d15 = _tmem_load_0[kk + 15] - csq_vals_tail[3];
+                        float best_1415 = d14;
+                        int idx_1415 = off_k_1 + score_base + kk + 14;
+                        if (d15 > best_1415) {
+                            best_1415 = d15;
+                            idx_1415 = off_k_1 + score_base + kk + 15;
+                        }
+                        float best_tail = best_1213;
+                        int idx_tail = idx_1213;
+                        if (best_1415 > best_tail) {
+                            best_tail = best_1415;
+                            idx_tail = idx_1415;
+                        }
+                        if (best_tail > best_next) {
+                            best_next = best_tail;
+                            idx_next = idx_tail;
+                        }
+                        if (best_next > best_group) {
+                            best_group = best_next;
+                            idx_group = idx_next;
+                        }
+                        if (best_group > best_score0) {
+                            best_score0 = best_group;
+                            best_idx0 = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + 256 + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score0_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 16) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        float csq_vals_hi_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 4) * 4));
+                        float d4_1 = _tmem_load_1[kk_1 + 4] - csq_vals_hi_1[0];
+                        float d5_1 = _tmem_load_1[kk_1 + 5] - csq_vals_hi_1[1];
+                        float best_45_1 = d4_1;
+                        int idx_45_1 = off_k_1 + score_base + kk_1 + 4;
+                        if (d5_1 > best_45_1) {
+                            best_45_1 = d5_1;
+                            idx_45_1 = off_k_1 + score_base + kk_1 + 5;
+                        }
+                        float d6_1 = _tmem_load_1[kk_1 + 6] - csq_vals_hi_1[2];
+                        float d7_1 = _tmem_load_1[kk_1 + 7] - csq_vals_hi_1[3];
+                        float best_67_1 = d6_1;
+                        int idx_67_1 = off_k_1 + score_base + kk_1 + 6;
+                        if (d7_1 > best_67_1) {
+                            best_67_1 = d7_1;
+                            idx_67_1 = off_k_1 + score_base + kk_1 + 7;
+                        }
+                        float best_hi_1 = best_45_1;
+                        int idx_hi_1 = idx_45_1;
+                        if (best_67_1 > best_hi_1) {
+                            best_hi_1 = best_67_1;
+                            idx_hi_1 = idx_67_1;
+                        }
+                        if (best_hi_1 > best_group_1) {
+                            best_group_1 = best_hi_1;
+                            idx_group_1 = idx_hi_1;
+                        }
+                        float csq_vals_next_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 8) * 4));
+                        float d8_1 = _tmem_load_1[kk_1 + 8] - csq_vals_next_1[0];
+                        float d9_1 = _tmem_load_1[kk_1 + 9] - csq_vals_next_1[1];
+                        float best_89_1 = d8_1;
+                        int idx_89_1 = off_k_1 + score_base + kk_1 + 8;
+                        if (d9_1 > best_89_1) {
+                            best_89_1 = d9_1;
+                            idx_89_1 = off_k_1 + score_base + kk_1 + 9;
+                        }
+                        float d10_1 = _tmem_load_1[kk_1 + 10] - csq_vals_next_1[2];
+                        float d11_1 = _tmem_load_1[kk_1 + 11] - csq_vals_next_1[3];
+                        float best_1011_1 = d10_1;
+                        int idx_1011_1 = off_k_1 + score_base + kk_1 + 10;
+                        if (d11_1 > best_1011_1) {
+                            best_1011_1 = d11_1;
+                            idx_1011_1 = off_k_1 + score_base + kk_1 + 11;
+                        }
+                        float best_next_1 = best_89_1;
+                        int idx_next_1 = idx_89_1;
+                        if (best_1011_1 > best_next_1) {
+                            best_next_1 = best_1011_1;
+                            idx_next_1 = idx_1011_1;
+                        }
+                        float csq_vals_tail_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1 + 12) * 4));
+                        float d12_1 = _tmem_load_1[kk_1 + 12] - csq_vals_tail_1[0];
+                        float d13_1 = _tmem_load_1[kk_1 + 13] - csq_vals_tail_1[1];
+                        float best_1213_1 = d12_1;
+                        int idx_1213_1 = off_k_1 + score_base + kk_1 + 12;
+                        if (d13_1 > best_1213_1) {
+                            best_1213_1 = d13_1;
+                            idx_1213_1 = off_k_1 + score_base + kk_1 + 13;
+                        }
+                        float d14_1 = _tmem_load_1[kk_1 + 14] - csq_vals_tail_1[2];
+                        float d15_1 = _tmem_load_1[kk_1 + 15] - csq_vals_tail_1[3];
+                        float best_1415_1 = d14_1;
+                        int idx_1415_1 = off_k_1 + score_base + kk_1 + 14;
+                        if (d15_1 > best_1415_1) {
+                            best_1415_1 = d15_1;
+                            idx_1415_1 = off_k_1 + score_base + kk_1 + 15;
+                        }
+                        float best_tail_1 = best_1213_1;
+                        int idx_tail_1 = idx_1213_1;
+                        if (best_1415_1 > best_tail_1) {
+                            best_tail_1 = best_1415_1;
+                            idx_tail_1 = idx_1415_1;
+                        }
+                        if (best_tail_1 > best_next_1) {
+                            best_next_1 = best_tail_1;
+                            idx_next_1 = idx_tail_1;
+                        }
+                        if (best_next_1 > best_group_1) {
+                            best_group_1 = best_next_1;
+                            idx_group_1 = idx_next_1;
+                        }
+                        if (best_group_1 > best_score0) {
+                            best_score0 = best_group_1;
+                            best_idx0 = idx_group_1;
+                        }
+                    }
+                    mbarrier_wait(score1_full_addr, _phase_score1_full_0);
+                    _phase_score1_full_0 ^= 1;
+                    score_base = 0;
+                    float _tmem_load_2[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_2[0]), "=f"(_tmem_load_2[1]), "=f"(_tmem_load_2[2]), "=f"(_tmem_load_2[3]), "=f"(_tmem_load_2[4]), "=f"(_tmem_load_2[5]), "=f"(_tmem_load_2[6]), "=f"(_tmem_load_2[7]), "=f"(_tmem_load_2[8]), "=f"(_tmem_load_2[9]), "=f"(_tmem_load_2[10]), "=f"(_tmem_load_2[11]), "=f"(_tmem_load_2[12]), "=f"(_tmem_load_2[13]), "=f"(_tmem_load_2[14]), "=f"(_tmem_load_2[15]), "=f"(_tmem_load_2[16]), "=f"(_tmem_load_2[17]), "=f"(_tmem_load_2[18]), "=f"(_tmem_load_2[19]), "=f"(_tmem_load_2[20]), "=f"(_tmem_load_2[21]), "=f"(_tmem_load_2[22]), "=f"(_tmem_load_2[23]), "=f"(_tmem_load_2[24]), "=f"(_tmem_load_2[25]), "=f"(_tmem_load_2[26]), "=f"(_tmem_load_2[27]), "=f"(_tmem_load_2[28]), "=f"(_tmem_load_2[29]), "=f"(_tmem_load_2[30]), "=f"(_tmem_load_2[31]), "=f"(_tmem_load_2[32]), "=f"(_tmem_load_2[33]), "=f"(_tmem_load_2[34]), "=f"(_tmem_load_2[35]), "=f"(_tmem_load_2[36]), "=f"(_tmem_load_2[37]), "=f"(_tmem_load_2[38]), "=f"(_tmem_load_2[39]), "=f"(_tmem_load_2[40]), "=f"(_tmem_load_2[41]), "=f"(_tmem_load_2[42]), "=f"(_tmem_load_2[43]), "=f"(_tmem_load_2[44]), "=f"(_tmem_load_2[45]), "=f"(_tmem_load_2[46]), "=f"(_tmem_load_2[47]), "=f"(_tmem_load_2[48]), "=f"(_tmem_load_2[49]), "=f"(_tmem_load_2[50]), "=f"(_tmem_load_2[51]), "=f"(_tmem_load_2[52]), "=f"(_tmem_load_2[53]), "=f"(_tmem_load_2[54]), "=f"(_tmem_load_2[55]), "=f"(_tmem_load_2[56]), "=f"(_tmem_load_2[57]), "=f"(_tmem_load_2[58]), "=f"(_tmem_load_2[59]), "=f"(_tmem_load_2[60]), "=f"(_tmem_load_2[61]), "=f"(_tmem_load_2[62]), "=f"(_tmem_load_2[63]), "=f"(_tmem_load_2[64]), "=f"(_tmem_load_2[65]), "=f"(_tmem_load_2[66]), "=f"(_tmem_load_2[67]), "=f"(_tmem_load_2[68]), "=f"(_tmem_load_2[69]), "=f"(_tmem_load_2[70]), "=f"(_tmem_load_2[71]), "=f"(_tmem_load_2[72]), "=f"(_tmem_load_2[73]), "=f"(_tmem_load_2[74]), "=f"(_tmem_load_2[75]), "=f"(_tmem_load_2[76]), "=f"(_tmem_load_2[77]), "=f"(_tmem_load_2[78]), "=f"(_tmem_load_2[79]), "=f"(_tmem_load_2[80]), "=f"(_tmem_load_2[81]), "=f"(_tmem_load_2[82]), "=f"(_tmem_load_2[83]), "=f"(_tmem_load_2[84]), "=f"(_tmem_load_2[85]), "=f"(_tmem_load_2[86]), "=f"(_tmem_load_2[87]), "=f"(_tmem_load_2[88]), "=f"(_tmem_load_2[89]), "=f"(_tmem_load_2[90]), "=f"(_tmem_load_2[91]), "=f"(_tmem_load_2[92]), "=f"(_tmem_load_2[93]), "=f"(_tmem_load_2[94]), "=f"(_tmem_load_2[95]), "=f"(_tmem_load_2[96]), "=f"(_tmem_load_2[97]), "=f"(_tmem_load_2[98]), "=f"(_tmem_load_2[99]), "=f"(_tmem_load_2[100]), "=f"(_tmem_load_2[101]), "=f"(_tmem_load_2[102]), "=f"(_tmem_load_2[103]), "=f"(_tmem_load_2[104]), "=f"(_tmem_load_2[105]), "=f"(_tmem_load_2[106]), "=f"(_tmem_load_2[107]), "=f"(_tmem_load_2[108]), "=f"(_tmem_load_2[109]), "=f"(_tmem_load_2[110]), "=f"(_tmem_load_2[111]), "=f"(_tmem_load_2[112]), "=f"(_tmem_load_2[113]), "=f"(_tmem_load_2[114]), "=f"(_tmem_load_2[115]), "=f"(_tmem_load_2[116]), "=f"(_tmem_load_2[117]), "=f"(_tmem_load_2[118]), "=f"(_tmem_load_2[119]), "=f"(_tmem_load_2[120]), "=f"(_tmem_load_2[121]), "=f"(_tmem_load_2[122]), "=f"(_tmem_load_2[123]), "=f"(_tmem_load_2[124]), "=f"(_tmem_load_2[125]), "=f"(_tmem_load_2[126]), "=f"(_tmem_load_2[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk_2 = 0; kk_2 < 128; kk_2 += 16) {
+                        float csq_vals_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2) * 4));
+                        float d0_2 = _tmem_load_2[kk_2] - csq_vals_2[0];
+                        float d1_2 = _tmem_load_2[kk_2 + 1] - csq_vals_2[1];
+                        float best_01_2 = d0_2;
+                        int idx_01_2 = off_k_1 + score_base + kk_2;
+                        if (d1_2 > best_01_2) {
+                            best_01_2 = d1_2;
+                            idx_01_2 = off_k_1 + score_base + kk_2 + 1;
+                        }
+                        float d2_2 = _tmem_load_2[kk_2 + 2] - csq_vals_2[2];
+                        float d3_2 = _tmem_load_2[kk_2 + 3] - csq_vals_2[3];
+                        float best_23_2 = d2_2;
+                        int idx_23_2 = off_k_1 + score_base + kk_2 + 2;
+                        if (d3_2 > best_23_2) {
+                            best_23_2 = d3_2;
+                            idx_23_2 = off_k_1 + score_base + kk_2 + 3;
+                        }
+                        float best_group_2 = best_01_2;
+                        int idx_group_2 = idx_01_2;
+                        if (best_23_2 > best_group_2) {
+                            best_group_2 = best_23_2;
+                            idx_group_2 = idx_23_2;
+                        }
+                        float csq_vals_hi_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 4) * 4));
+                        float d4_2 = _tmem_load_2[kk_2 + 4] - csq_vals_hi_2[0];
+                        float d5_2 = _tmem_load_2[kk_2 + 5] - csq_vals_hi_2[1];
+                        float best_45_2 = d4_2;
+                        int idx_45_2 = off_k_1 + score_base + kk_2 + 4;
+                        if (d5_2 > best_45_2) {
+                            best_45_2 = d5_2;
+                            idx_45_2 = off_k_1 + score_base + kk_2 + 5;
+                        }
+                        float d6_2 = _tmem_load_2[kk_2 + 6] - csq_vals_hi_2[2];
+                        float d7_2 = _tmem_load_2[kk_2 + 7] - csq_vals_hi_2[3];
+                        float best_67_2 = d6_2;
+                        int idx_67_2 = off_k_1 + score_base + kk_2 + 6;
+                        if (d7_2 > best_67_2) {
+                            best_67_2 = d7_2;
+                            idx_67_2 = off_k_1 + score_base + kk_2 + 7;
+                        }
+                        float best_hi_2 = best_45_2;
+                        int idx_hi_2 = idx_45_2;
+                        if (best_67_2 > best_hi_2) {
+                            best_hi_2 = best_67_2;
+                            idx_hi_2 = idx_67_2;
+                        }
+                        if (best_hi_2 > best_group_2) {
+                            best_group_2 = best_hi_2;
+                            idx_group_2 = idx_hi_2;
+                        }
+                        float csq_vals_next_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 8) * 4));
+                        float d8_2 = _tmem_load_2[kk_2 + 8] - csq_vals_next_2[0];
+                        float d9_2 = _tmem_load_2[kk_2 + 9] - csq_vals_next_2[1];
+                        float best_89_2 = d8_2;
+                        int idx_89_2 = off_k_1 + score_base + kk_2 + 8;
+                        if (d9_2 > best_89_2) {
+                            best_89_2 = d9_2;
+                            idx_89_2 = off_k_1 + score_base + kk_2 + 9;
+                        }
+                        float d10_2 = _tmem_load_2[kk_2 + 10] - csq_vals_next_2[2];
+                        float d11_2 = _tmem_load_2[kk_2 + 11] - csq_vals_next_2[3];
+                        float best_1011_2 = d10_2;
+                        int idx_1011_2 = off_k_1 + score_base + kk_2 + 10;
+                        if (d11_2 > best_1011_2) {
+                            best_1011_2 = d11_2;
+                            idx_1011_2 = off_k_1 + score_base + kk_2 + 11;
+                        }
+                        float best_next_2 = best_89_2;
+                        int idx_next_2 = idx_89_2;
+                        if (best_1011_2 > best_next_2) {
+                            best_next_2 = best_1011_2;
+                            idx_next_2 = idx_1011_2;
+                        }
+                        float csq_vals_tail_2[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_2[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_2 + 12) * 4));
+                        float d12_2 = _tmem_load_2[kk_2 + 12] - csq_vals_tail_2[0];
+                        float d13_2 = _tmem_load_2[kk_2 + 13] - csq_vals_tail_2[1];
+                        float best_1213_2 = d12_2;
+                        int idx_1213_2 = off_k_1 + score_base + kk_2 + 12;
+                        if (d13_2 > best_1213_2) {
+                            best_1213_2 = d13_2;
+                            idx_1213_2 = off_k_1 + score_base + kk_2 + 13;
+                        }
+                        float d14_2 = _tmem_load_2[kk_2 + 14] - csq_vals_tail_2[2];
+                        float d15_2 = _tmem_load_2[kk_2 + 15] - csq_vals_tail_2[3];
+                        float best_1415_2 = d14_2;
+                        int idx_1415_2 = off_k_1 + score_base + kk_2 + 14;
+                        if (d15_2 > best_1415_2) {
+                            best_1415_2 = d15_2;
+                            idx_1415_2 = off_k_1 + score_base + kk_2 + 15;
+                        }
+                        float best_tail_2 = best_1213_2;
+                        int idx_tail_2 = idx_1213_2;
+                        if (best_1415_2 > best_tail_2) {
+                            best_tail_2 = best_1415_2;
+                            idx_tail_2 = idx_1415_2;
+                        }
+                        if (best_tail_2 > best_next_2) {
+                            best_next_2 = best_tail_2;
+                            idx_next_2 = idx_tail_2;
+                        }
+                        if (best_next_2 > best_group_2) {
+                            best_group_2 = best_next_2;
+                            idx_group_2 = idx_next_2;
+                        }
+                        if (best_group_2 > best_score1) {
+                            best_score1 = best_group_2;
+                            best_idx1 = idx_group_2;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_3[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_3[0]), "=f"(_tmem_load_3[1]), "=f"(_tmem_load_3[2]), "=f"(_tmem_load_3[3]), "=f"(_tmem_load_3[4]), "=f"(_tmem_load_3[5]), "=f"(_tmem_load_3[6]), "=f"(_tmem_load_3[7]), "=f"(_tmem_load_3[8]), "=f"(_tmem_load_3[9]), "=f"(_tmem_load_3[10]), "=f"(_tmem_load_3[11]), "=f"(_tmem_load_3[12]), "=f"(_tmem_load_3[13]), "=f"(_tmem_load_3[14]), "=f"(_tmem_load_3[15]), "=f"(_tmem_load_3[16]), "=f"(_tmem_load_3[17]), "=f"(_tmem_load_3[18]), "=f"(_tmem_load_3[19]), "=f"(_tmem_load_3[20]), "=f"(_tmem_load_3[21]), "=f"(_tmem_load_3[22]), "=f"(_tmem_load_3[23]), "=f"(_tmem_load_3[24]), "=f"(_tmem_load_3[25]), "=f"(_tmem_load_3[26]), "=f"(_tmem_load_3[27]), "=f"(_tmem_load_3[28]), "=f"(_tmem_load_3[29]), "=f"(_tmem_load_3[30]), "=f"(_tmem_load_3[31]), "=f"(_tmem_load_3[32]), "=f"(_tmem_load_3[33]), "=f"(_tmem_load_3[34]), "=f"(_tmem_load_3[35]), "=f"(_tmem_load_3[36]), "=f"(_tmem_load_3[37]), "=f"(_tmem_load_3[38]), "=f"(_tmem_load_3[39]), "=f"(_tmem_load_3[40]), "=f"(_tmem_load_3[41]), "=f"(_tmem_load_3[42]), "=f"(_tmem_load_3[43]), "=f"(_tmem_load_3[44]), "=f"(_tmem_load_3[45]), "=f"(_tmem_load_3[46]), "=f"(_tmem_load_3[47]), "=f"(_tmem_load_3[48]), "=f"(_tmem_load_3[49]), "=f"(_tmem_load_3[50]), "=f"(_tmem_load_3[51]), "=f"(_tmem_load_3[52]), "=f"(_tmem_load_3[53]), "=f"(_tmem_load_3[54]), "=f"(_tmem_load_3[55]), "=f"(_tmem_load_3[56]), "=f"(_tmem_load_3[57]), "=f"(_tmem_load_3[58]), "=f"(_tmem_load_3[59]), "=f"(_tmem_load_3[60]), "=f"(_tmem_load_3[61]), "=f"(_tmem_load_3[62]), "=f"(_tmem_load_3[63]), "=f"(_tmem_load_3[64]), "=f"(_tmem_load_3[65]), "=f"(_tmem_load_3[66]), "=f"(_tmem_load_3[67]), "=f"(_tmem_load_3[68]), "=f"(_tmem_load_3[69]), "=f"(_tmem_load_3[70]), "=f"(_tmem_load_3[71]), "=f"(_tmem_load_3[72]), "=f"(_tmem_load_3[73]), "=f"(_tmem_load_3[74]), "=f"(_tmem_load_3[75]), "=f"(_tmem_load_3[76]), "=f"(_tmem_load_3[77]), "=f"(_tmem_load_3[78]), "=f"(_tmem_load_3[79]), "=f"(_tmem_load_3[80]), "=f"(_tmem_load_3[81]), "=f"(_tmem_load_3[82]), "=f"(_tmem_load_3[83]), "=f"(_tmem_load_3[84]), "=f"(_tmem_load_3[85]), "=f"(_tmem_load_3[86]), "=f"(_tmem_load_3[87]), "=f"(_tmem_load_3[88]), "=f"(_tmem_load_3[89]), "=f"(_tmem_load_3[90]), "=f"(_tmem_load_3[91]), "=f"(_tmem_load_3[92]), "=f"(_tmem_load_3[93]), "=f"(_tmem_load_3[94]), "=f"(_tmem_load_3[95]), "=f"(_tmem_load_3[96]), "=f"(_tmem_load_3[97]), "=f"(_tmem_load_3[98]), "=f"(_tmem_load_3[99]), "=f"(_tmem_load_3[100]), "=f"(_tmem_load_3[101]), "=f"(_tmem_load_3[102]), "=f"(_tmem_load_3[103]), "=f"(_tmem_load_3[104]), "=f"(_tmem_load_3[105]), "=f"(_tmem_load_3[106]), "=f"(_tmem_load_3[107]), "=f"(_tmem_load_3[108]), "=f"(_tmem_load_3[109]), "=f"(_tmem_load_3[110]), "=f"(_tmem_load_3[111]), "=f"(_tmem_load_3[112]), "=f"(_tmem_load_3[113]), "=f"(_tmem_load_3[114]), "=f"(_tmem_load_3[115]), "=f"(_tmem_load_3[116]), "=f"(_tmem_load_3[117]), "=f"(_tmem_load_3[118]), "=f"(_tmem_load_3[119]), "=f"(_tmem_load_3[120]), "=f"(_tmem_load_3[121]), "=f"(_tmem_load_3[122]), "=f"(_tmem_load_3[123]), "=f"(_tmem_load_3[124]), "=f"(_tmem_load_3[125]), "=f"(_tmem_load_3[126]), "=f"(_tmem_load_3[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score1_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_3 = 0; kk_3 < 128; kk_3 += 16) {
+                        float csq_vals_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3) * 4));
+                        float d0_3 = _tmem_load_3[kk_3] - csq_vals_3[0];
+                        float d1_3 = _tmem_load_3[kk_3 + 1] - csq_vals_3[1];
+                        float best_01_3 = d0_3;
+                        int idx_01_3 = off_k_1 + score_base + kk_3;
+                        if (d1_3 > best_01_3) {
+                            best_01_3 = d1_3;
+                            idx_01_3 = off_k_1 + score_base + kk_3 + 1;
+                        }
+                        float d2_3 = _tmem_load_3[kk_3 + 2] - csq_vals_3[2];
+                        float d3_3 = _tmem_load_3[kk_3 + 3] - csq_vals_3[3];
+                        float best_23_3 = d2_3;
+                        int idx_23_3 = off_k_1 + score_base + kk_3 + 2;
+                        if (d3_3 > best_23_3) {
+                            best_23_3 = d3_3;
+                            idx_23_3 = off_k_1 + score_base + kk_3 + 3;
+                        }
+                        float best_group_3 = best_01_3;
+                        int idx_group_3 = idx_01_3;
+                        if (best_23_3 > best_group_3) {
+                            best_group_3 = best_23_3;
+                            idx_group_3 = idx_23_3;
+                        }
+                        float csq_vals_hi_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_hi_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 4) * 4));
+                        float d4_3 = _tmem_load_3[kk_3 + 4] - csq_vals_hi_3[0];
+                        float d5_3 = _tmem_load_3[kk_3 + 5] - csq_vals_hi_3[1];
+                        float best_45_3 = d4_3;
+                        int idx_45_3 = off_k_1 + score_base + kk_3 + 4;
+                        if (d5_3 > best_45_3) {
+                            best_45_3 = d5_3;
+                            idx_45_3 = off_k_1 + score_base + kk_3 + 5;
+                        }
+                        float d6_3 = _tmem_load_3[kk_3 + 6] - csq_vals_hi_3[2];
+                        float d7_3 = _tmem_load_3[kk_3 + 7] - csq_vals_hi_3[3];
+                        float best_67_3 = d6_3;
+                        int idx_67_3 = off_k_1 + score_base + kk_3 + 6;
+                        if (d7_3 > best_67_3) {
+                            best_67_3 = d7_3;
+                            idx_67_3 = off_k_1 + score_base + kk_3 + 7;
+                        }
+                        float best_hi_3 = best_45_3;
+                        int idx_hi_3 = idx_45_3;
+                        if (best_67_3 > best_hi_3) {
+                            best_hi_3 = best_67_3;
+                            idx_hi_3 = idx_67_3;
+                        }
+                        if (best_hi_3 > best_group_3) {
+                            best_group_3 = best_hi_3;
+                            idx_group_3 = idx_hi_3;
+                        }
+                        float csq_vals_next_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_next_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 8) * 4));
+                        float d8_3 = _tmem_load_3[kk_3 + 8] - csq_vals_next_3[0];
+                        float d9_3 = _tmem_load_3[kk_3 + 9] - csq_vals_next_3[1];
+                        float best_89_3 = d8_3;
+                        int idx_89_3 = off_k_1 + score_base + kk_3 + 8;
+                        if (d9_3 > best_89_3) {
+                            best_89_3 = d9_3;
+                            idx_89_3 = off_k_1 + score_base + kk_3 + 9;
+                        }
+                        float d10_3 = _tmem_load_3[kk_3 + 10] - csq_vals_next_3[2];
+                        float d11_3 = _tmem_load_3[kk_3 + 11] - csq_vals_next_3[3];
+                        float best_1011_3 = d10_3;
+                        int idx_1011_3 = off_k_1 + score_base + kk_3 + 10;
+                        if (d11_3 > best_1011_3) {
+                            best_1011_3 = d11_3;
+                            idx_1011_3 = off_k_1 + score_base + kk_3 + 11;
+                        }
+                        float best_next_3 = best_89_3;
+                        int idx_next_3 = idx_89_3;
+                        if (best_1011_3 > best_next_3) {
+                            best_next_3 = best_1011_3;
+                            idx_next_3 = idx_1011_3;
+                        }
+                        float csq_vals_tail_3[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_tail_3[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_3 + 12) * 4));
+                        float d12_3 = _tmem_load_3[kk_3 + 12] - csq_vals_tail_3[0];
+                        float d13_3 = _tmem_load_3[kk_3 + 13] - csq_vals_tail_3[1];
+                        float best_1213_3 = d12_3;
+                        int idx_1213_3 = off_k_1 + score_base + kk_3 + 12;
+                        if (d13_3 > best_1213_3) {
+                            best_1213_3 = d13_3;
+                            idx_1213_3 = off_k_1 + score_base + kk_3 + 13;
+                        }
+                        float d14_3 = _tmem_load_3[kk_3 + 14] - csq_vals_tail_3[2];
+                        float d15_3 = _tmem_load_3[kk_3 + 15] - csq_vals_tail_3[3];
+                        float best_1415_3 = d14_3;
+                        int idx_1415_3 = off_k_1 + score_base + kk_3 + 14;
+                        if (d15_3 > best_1415_3) {
+                            best_1415_3 = d15_3;
+                            idx_1415_3 = off_k_1 + score_base + kk_3 + 15;
+                        }
+                        float best_tail_3 = best_1213_3;
+                        int idx_tail_3 = idx_1213_3;
+                        if (best_1415_3 > best_tail_3) {
+                            best_tail_3 = best_1415_3;
+                            idx_tail_3 = idx_1415_3;
+                        }
+                        if (best_tail_3 > best_next_3) {
+                            best_next_3 = best_tail_3;
+                            idx_next_3 = idx_tail_3;
+                        }
+                        if (best_next_3 > best_group_3) {
+                            best_group_3 = best_next_3;
+                            idx_group_3 = idx_next_3;
+                        }
+                        if (best_group_3 > best_score1) {
+                            best_score1 = best_group_3;
+                            best_idx1 = idx_group_3;
+                        }
+                    }
+                }
+                if (global_n0 < N) {
+                    *((int*)(out + out_offset0)) = best_idx0;
+                }
+                if (global_n1 < N) {
+                    *((int*)(out + out_offset1)) = best_idx1;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(512));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0344.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0344.cu
new file mode 100644
index 00000000..7070fa90
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0344.cu
@@ -0,0 +1,600 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 49152
+#define SMEM_SMEM_X_STRIDE 49152
+#define SMEM_SMEM_C_OFF 50176
+#define SMEM_SMEM_C_STAGE_BYTES 98304
+#define SMEM_SMEM_C_STRIDE 98304
+#define SMEM_SMEM_CSQ_OFF 148480
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 149504
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d192_single_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 50176);
+    const int smem_c_addr = smem + 50176;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 148480);
+    const int smem_csq_addr = smem + 148480;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                        _phase_x_empty_0 ^= 1;
+                        tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, 0, x_full_addr);
+                        mbarrier_arrive_expect_tx(x_full_addr, 49152);
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, 0, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 98304);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                mbarrier_wait(x_full_addr, _phase_x_full_0);
+                _phase_x_full_0 ^= 1;
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(0));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_1 = smem_x_addr + 16384;
+                    int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                    int _mma_b_addr_1 = smem_c_addr + 32768;
+                    int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_1), "r"(_mma_b_lo_1), "r"(tmem_score_tmem), "r"(1));
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = smem_x_addr + 32768;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = smem_c_addr + 65536;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x40004040;\n\t"
+                    "mov.b32 bdhi, 0x40004040;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_2), "r"(_mma_b_lo_2), "r"(tmem_score_tmem), "r"(1));
+                    elect_commit(score_full_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(x_empty_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0345.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0345.cu
new file mode 100644
index 00000000..3f16db31
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0345.cu
@@ -0,0 +1,525 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 5120
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 22528
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d480_splitk_partial_d32k256_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 5120);
+    const int smem_c_addr = smem + 5120;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int total_work = B * num_n_tiles * K_slices;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                int iter_slice = work_idx % (unsigned int)K_slices;
+                int point_tile_idx = work_idx / (unsigned int)K_slices;
+                int batch = point_tile_idx / num_n_tiles;
+                int slice_k_start = iter_slice;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = slice_k_start * 256;
+                int idx1 = idx0;
+                #pragma unroll 1
+                for (int local_k = 0; local_k < 1; local_k++) {
+                    int iter_k = slice_k_start + local_k;
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    int partial_offset0 = work_idx * 64 + (unsigned int)row0;
+                    *((float*)(partial_scores + partial_offset0)) = best0;
+                    *((int*)(partial_indices + partial_offset0)) = idx0;
+                    int partial_offset1 = work_idx * 64 + (unsigned int)row1;
+                    *((float*)(partial_scores + partial_offset1)) = best1;
+                    *((int*)(partial_indices + partial_offset1)) = idx1;
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int total_work_1 = B * num_n_tiles * K_slices;
+            int feature_tiles = D / 32;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_1; work_idx_1 += num_bids) {
+                    int iter_slice_1 = work_idx_1 % (unsigned int)K_slices;
+                    int point_tile_idx_1 = work_idx_1 / (unsigned int)K_slices;
+                    int batch_1 = point_tile_idx_1 / num_n_tiles;
+                    int n_tile = point_tile_idx_1 % num_n_tiles;
+                    int off_n = n_tile * 64;
+                    int x_row = batch_1 * N + off_n;
+                    int slice_k_start_1 = iter_slice_1;
+                    #pragma unroll 1
+                    for (int local_k_1 = 0; local_k_1 < 1; local_k_1++) {
+                        int iter_k_1 = slice_k_start_1 + local_k_1;
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 4096);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int total_work_2 = B * num_n_tiles * K_slices;
+            int feature_tiles_1 = D / 32;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_2 = bid; work_idx_2 < total_work_2; work_idx_2 += num_bids) {
+                int iter_slice_2 = work_idx_2 % (unsigned int)K_slices;
+                int slice_k_start_2 = iter_slice_2;
+                #pragma unroll 1
+                for (int local_k_2 = 0; local_k_2 < 1; local_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0346.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0346.cu
new file mode 100644
index 00000000..c242dff7
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0346.cu
@@ -0,0 +1,81 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d480_splitk_reduce_d32k256_v1(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_slices)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid / 4;
+    int row_lane = tid % 4;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 64 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_slice = row_lane; iter_slice < K_slices; iter_slice += 4) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_slices + (unsigned int)iter_slice) * 64 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_score, 1);
+        float peer_score = _shfl_xor_0;
+        int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 1);
+        int peer_idx = _shfl_xor_1;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best_score, 2);
+        peer_score = _shfl_xor_2;
+        int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, best_idx, 2);
+        peer_idx = _shfl_xor_3;
+        if (peer_score > best_score) {
+            best_score = peer_score;
+            best_idx = peer_idx;
+        }
+        if (row_lane == 0) {
+            int out_offset = batch * N + global_n;
+            *((int*)(out + out_offset)) = best_idx;
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0347.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0347.cu
new file mode 100644
index 00000000..190f65dc
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0347.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d416_exactd_splitd_a4a579d1_v2(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < D / 32; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < D / 32; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0348.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0348.cu
new file mode 100644
index 00000000..edfe179b
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0348.cu
@@ -0,0 +1,512 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_partial(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, float* __restrict__ partial_scores, int* __restrict__ partial_indices, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int total_work = B * num_n_tiles * K_tiles;
+            int feature_tiles = 9;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int work_idx = bid; work_idx < total_work; work_idx += num_bids) {
+                        int iter_k = work_idx % (unsigned int)K_tiles;
+                        int point_tile_idx = work_idx / (unsigned int)K_tiles;
+                        int batch = point_tile_idx / num_n_tiles;
+                        int n_tile = point_tile_idx % num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int off_k = iter_k * 256;
+                        int x_row = batch * N + off_n;
+                        int c_row = batch * K + off_k;
+                        #pragma unroll 1
+                        for (int feat_tile = 0; feat_tile < feature_tiles; feat_tile++) {
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, feat_tile, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, feat_tile, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int total_work_1 = B * num_n_tiles * K_tiles;
+            int feature_tiles_1 = 9;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int _work_idx = bid; _work_idx < total_work_1; _work_idx += num_bids) {
+                mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                _phase_score_empty_0 ^= 1;
+                #pragma unroll 1
+                for (int feat_tile_1 = 0; feat_tile_1 < feature_tiles_1; feat_tile_1++) {
+                    mbarrier_wait(x_full_addr, _phase_x_full_0);
+                    _phase_x_full_0 ^= 1;
+                    mbarrier_wait(c_full_addr, _phase_c_full_0);
+                    _phase_c_full_0 ^= 1;
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int init_flag = ((feat_tile_1 == 0) ? 1 : 0);
+                    int _mma_a_addr_0 = smem_x_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = smem_c_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                    elect_commit(x_empty_addr);
+                    elect_commit(c_empty_addr);
+                }
+                elect_commit(score_full_addr);
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int total_work_2 = B * num_n_tiles * K_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int work_idx_1 = bid; work_idx_1 < total_work_2; work_idx_1 += num_bids) {
+                int iter_k_1 = work_idx_1 % (unsigned int)K_tiles;
+                int point_tile_idx_1 = work_idx_1 / (unsigned int)K_tiles;
+                int batch_1 = point_tile_idx_1 / num_n_tiles;
+                int off_k_1 = iter_k_1 * 256;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = off_k_1;
+                if (warp % 4 * 32 + lane < 64) {
+                    int csq_base = (warp % 4 * 32 + lane) * 4;
+                    float _vec_load_0[4];
+                    {
+                        float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                        _vec_load_0[0 + 0] = _v4.x;
+                        _vec_load_0[0 + 1] = _v4.y;
+                        _vec_load_0[0 + 2] = _v4.z;
+                        _vec_load_0[0 + 3] = _v4.w;
+                    }
+                    float csq_half[4];
+                    csq_half[0] = 0.5f * _vec_load_0[0];
+                    csq_half[1] = 0.5f * _vec_load_0[1];
+                    csq_half[2] = 0.5f * _vec_load_0[2];
+                    csq_half[3] = 0.5f * _vec_load_0[3];
+                    asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                }
+                asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                mbarrier_wait(score_full_addr, _phase_score_full_0);
+                _phase_score_full_0 ^= 1;
+                int score_base = 0;
+                float _tmem_load_0[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                #pragma unroll
+                for (int kk = 0; kk < 128; kk += 4) {
+                    float csq_vals[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk) * 4));
+                    float d0 = _tmem_load_0[kk] - csq_vals[0];
+                    float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                    float best_01 = d0;
+                    int idx_01 = off_k_1 + score_base + kk;
+                    if (d1 > best_01) {
+                        best_01 = d1;
+                        idx_01 = off_k_1 + score_base + kk + 1;
+                    }
+                    float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                    float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                    float best_23 = d2;
+                    int idx_23 = off_k_1 + score_base + kk + 2;
+                    if (d3 > best_23) {
+                        best_23 = d3;
+                        idx_23 = off_k_1 + score_base + kk + 3;
+                    }
+                    float best_group = best_01;
+                    int idx_group = idx_01;
+                    if (best_23 > best_group) {
+                        best_group = best_23;
+                        idx_group = idx_23;
+                    }
+                    if (best_group > best_score) {
+                        best_score = best_group;
+                        best_idx = idx_group;
+                    }
+                }
+                score_base = 128;
+                float _tmem_load_1[128];
+                asm volatile(
+                    "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                    " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                    : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                    : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                    : "memory");
+                asm volatile("tcgen05.wait::ld.sync.aligned;");
+                asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                if (elect_sync()) {
+                    mbarrier_arrive(score_empty_addr);
+                }
+                #pragma unroll
+                for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                    float csq_vals_1[4];
+                    asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                        : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                        : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                    float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                    float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                    float best_01_1 = d0_1;
+                    int idx_01_1 = off_k_1 + score_base + kk_1;
+                    if (d1_1 > best_01_1) {
+                        best_01_1 = d1_1;
+                        idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                    }
+                    float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                    float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                    float best_23_1 = d2_1;
+                    int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                    if (d3_1 > best_23_1) {
+                        best_23_1 = d3_1;
+                        idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                    }
+                    float best_group_1 = best_01_1;
+                    int idx_group_1 = idx_01_1;
+                    if (best_23_1 > best_group_1) {
+                        best_group_1 = best_23_1;
+                        idx_group_1 = idx_23_1;
+                    }
+                    if (best_group_1 > best_score) {
+                        best_score = best_group_1;
+                        best_idx = idx_group_1;
+                    }
+                }
+                int partial_offset = work_idx_1 * 128 + (unsigned int)(warp % 4 * 32 + lane);
+                *((float*)(partial_scores + partial_offset)) = best_score;
+                *((int*)(partial_indices + partial_offset)) = best_idx;
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0349.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0349.cu
new file mode 100644
index 00000000..0249cc88
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0349.cu
@@ -0,0 +1,62 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 128
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(128) void
+kernel_flash_kmeans_assign_d288_splitk_cta_0438_v1_reduce(float* __restrict__ partial_scores, int* __restrict__ partial_indices, int* __restrict__ out, int B, int N, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int row = tid;
+    int total_point_tiles = B * num_n_tiles;
+    #pragma unroll 1
+    for (unsigned int point_tile_idx = bid; point_tile_idx < total_point_tiles; point_tile_idx += num_bids) {
+        int batch = point_tile_idx / (unsigned int)num_n_tiles;
+        int n_tile = point_tile_idx % (unsigned int)num_n_tiles;
+        int global_n = n_tile * 128 + row;
+        float best_score = -3.4e+38f;
+        int best_idx = 0;
+        #pragma unroll 1
+        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+            int partial_offset = (point_tile_idx * (unsigned int)K_tiles + (unsigned int)iter_k) * 128 + (unsigned int)row;
+            float score = partial_scores[partial_offset];
+            int idx = partial_indices[partial_offset];
+            if (score > best_score) {
+                best_score = score;
+                best_idx = idx;
+            }
+        }
+        int out_offset = batch * N + global_n;
+        *((int*)(out + out_offset)) = best_idx;
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0350.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0350.cu
new file mode 100644
index 00000000..f2293d4d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0350.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 8192
+#define SMEM_SMEM_X_STRIDE 8192
+#define SMEM_SMEM_C_OFF 9216
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 25600
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 26624
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d288_exactd_a532_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 9216);
+    const int smem_c_addr = smem + 9216;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 25600);
+    const int smem_csq_addr = smem + 25600;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int num_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (warp == 0) {
+                if (elect_sync()) {
+                    #pragma unroll 1
+                    for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                        int batch = tile_idx / (unsigned int)num_n_tiles;
+                        int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                        int off_n = n_tile * 128;
+                        int x_row = batch * N + off_n;
+                        #pragma unroll 1
+                        for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                            int off_k = iter_k * 256;
+                            int c_row = batch * K + off_k;
+                            #pragma unroll 1
+                            for (int iter_d = 0; iter_d < 9; iter_d++) {
+                                int d_group = iter_d;
+                                mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                                _phase_x_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                                mbarrier_arrive_expect_tx(x_full_addr, 8192);
+                                mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                                _phase_c_empty_0 ^= 1;
+                                tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                                mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 1) {
+        { // mma_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 9; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 138413200;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 2 && warp <= 5) {
+        { // compute_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                int batch_1 = tile_idx_2 / (unsigned int)num_n_tiles;
+                int n_tile_1 = tile_idx_2 % (unsigned int)num_n_tiles;
+                int off_n_1 = n_tile_1 * 128;
+                int global_n = off_n_1 + (warp % 4 * 32 + lane);
+                int out_offset = batch_1 * N + global_n;
+                int csq_smem_addr = smem_csq_addr;
+                float best_score = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    int off_k_1 = iter_k_2 * 256;
+                    if (warp % 4 * 32 + lane < 64) {
+                        int csq_base = (warp % 4 * 32 + lane) * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch_1 * K + off_k_1 + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    int score_base = 0;
+                    float _tmem_load_0[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63]), "=f"(_tmem_load_0[64]), "=f"(_tmem_load_0[65]), "=f"(_tmem_load_0[66]), "=f"(_tmem_load_0[67]), "=f"(_tmem_load_0[68]), "=f"(_tmem_load_0[69]), "=f"(_tmem_load_0[70]), "=f"(_tmem_load_0[71]), "=f"(_tmem_load_0[72]), "=f"(_tmem_load_0[73]), "=f"(_tmem_load_0[74]), "=f"(_tmem_load_0[75]), "=f"(_tmem_load_0[76]), "=f"(_tmem_load_0[77]), "=f"(_tmem_load_0[78]), "=f"(_tmem_load_0[79]), "=f"(_tmem_load_0[80]), "=f"(_tmem_load_0[81]), "=f"(_tmem_load_0[82]), "=f"(_tmem_load_0[83]), "=f"(_tmem_load_0[84]), "=f"(_tmem_load_0[85]), "=f"(_tmem_load_0[86]), "=f"(_tmem_load_0[87]), "=f"(_tmem_load_0[88]), "=f"(_tmem_load_0[89]), "=f"(_tmem_load_0[90]), "=f"(_tmem_load_0[91]), "=f"(_tmem_load_0[92]), "=f"(_tmem_load_0[93]), "=f"(_tmem_load_0[94]), "=f"(_tmem_load_0[95]), "=f"(_tmem_load_0[96]), "=f"(_tmem_load_0[97]), "=f"(_tmem_load_0[98]), "=f"(_tmem_load_0[99]), "=f"(_tmem_load_0[100]), "=f"(_tmem_load_0[101]), "=f"(_tmem_load_0[102]), "=f"(_tmem_load_0[103]), "=f"(_tmem_load_0[104]), "=f"(_tmem_load_0[105]), "=f"(_tmem_load_0[106]), "=f"(_tmem_load_0[107]), "=f"(_tmem_load_0[108]), "=f"(_tmem_load_0[109]), "=f"(_tmem_load_0[110]), "=f"(_tmem_load_0[111]), "=f"(_tmem_load_0[112]), "=f"(_tmem_load_0[113]), "=f"(_tmem_load_0[114]), "=f"(_tmem_load_0[115]), "=f"(_tmem_load_0[116]), "=f"(_tmem_load_0[117]), "=f"(_tmem_load_0[118]), "=f"(_tmem_load_0[119]), "=f"(_tmem_load_0[120]), "=f"(_tmem_load_0[121]), "=f"(_tmem_load_0[122]), "=f"(_tmem_load_0[123]), "=f"(_tmem_load_0[124]), "=f"(_tmem_load_0[125]), "=f"(_tmem_load_0[126]), "=f"(_tmem_load_0[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    #pragma unroll
+                    for (int kk = 0; kk < 128; kk += 4) {
+                        float csq_vals[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk) * 4));
+                        float d0 = _tmem_load_0[kk] - csq_vals[0];
+                        float d1 = _tmem_load_0[kk + 1] - csq_vals[1];
+                        float best_01 = d0;
+                        int idx_01 = off_k_1 + score_base + kk;
+                        if (d1 > best_01) {
+                            best_01 = d1;
+                            idx_01 = off_k_1 + score_base + kk + 1;
+                        }
+                        float d2 = _tmem_load_0[kk + 2] - csq_vals[2];
+                        float d3 = _tmem_load_0[kk + 3] - csq_vals[3];
+                        float best_23 = d2;
+                        int idx_23 = off_k_1 + score_base + kk + 2;
+                        if (d3 > best_23) {
+                            best_23 = d3;
+                            idx_23 = off_k_1 + score_base + kk + 3;
+                        }
+                        float best_group = best_01;
+                        int idx_group = idx_01;
+                        if (best_23 > best_group) {
+                            best_group = best_23;
+                            idx_group = idx_23;
+                        }
+                        if (best_group > best_score) {
+                            best_score = best_group;
+                            best_idx = idx_group;
+                        }
+                    }
+                    score_base = 128;
+                    float _tmem_load_1[128];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x128.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63]), "=f"(_tmem_load_1[64]), "=f"(_tmem_load_1[65]), "=f"(_tmem_load_1[66]), "=f"(_tmem_load_1[67]), "=f"(_tmem_load_1[68]), "=f"(_tmem_load_1[69]), "=f"(_tmem_load_1[70]), "=f"(_tmem_load_1[71]), "=f"(_tmem_load_1[72]), "=f"(_tmem_load_1[73]), "=f"(_tmem_load_1[74]), "=f"(_tmem_load_1[75]), "=f"(_tmem_load_1[76]), "=f"(_tmem_load_1[77]), "=f"(_tmem_load_1[78]), "=f"(_tmem_load_1[79]), "=f"(_tmem_load_1[80]), "=f"(_tmem_load_1[81]), "=f"(_tmem_load_1[82]), "=f"(_tmem_load_1[83]), "=f"(_tmem_load_1[84]), "=f"(_tmem_load_1[85]), "=f"(_tmem_load_1[86]), "=f"(_tmem_load_1[87]), "=f"(_tmem_load_1[88]), "=f"(_tmem_load_1[89]), "=f"(_tmem_load_1[90]), "=f"(_tmem_load_1[91]), "=f"(_tmem_load_1[92]), "=f"(_tmem_load_1[93]), "=f"(_tmem_load_1[94]), "=f"(_tmem_load_1[95]), "=f"(_tmem_load_1[96]), "=f"(_tmem_load_1[97]), "=f"(_tmem_load_1[98]), "=f"(_tmem_load_1[99]), "=f"(_tmem_load_1[100]), "=f"(_tmem_load_1[101]), "=f"(_tmem_load_1[102]), "=f"(_tmem_load_1[103]), "=f"(_tmem_load_1[104]), "=f"(_tmem_load_1[105]), "=f"(_tmem_load_1[106]), "=f"(_tmem_load_1[107]), "=f"(_tmem_load_1[108]), "=f"(_tmem_load_1[109]), "=f"(_tmem_load_1[110]), "=f"(_tmem_load_1[111]), "=f"(_tmem_load_1[112]), "=f"(_tmem_load_1[113]), "=f"(_tmem_load_1[114]), "=f"(_tmem_load_1[115]), "=f"(_tmem_load_1[116]), "=f"(_tmem_load_1[117]), "=f"(_tmem_load_1[118]), "=f"(_tmem_load_1[119]), "=f"(_tmem_load_1[120]), "=f"(_tmem_load_1[121]), "=f"(_tmem_load_1[122]), "=f"(_tmem_load_1[123]), "=f"(_tmem_load_1[124]), "=f"(_tmem_load_1[125]), "=f"(_tmem_load_1[126]), "=f"(_tmem_load_1[127])
+                        : "r"(taddr + (unsigned int)(warp % 4 * 32 << 16) + (unsigned int)score_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 128; kk_1 += 4) {
+                        float csq_vals_1[4];
+                        asm volatile("ld.shared.v4.b32 {%0,%1,%2,%3}, [%4];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[0])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 1])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 2])), "=r"(*reinterpret_cast<uint32_t*>(&csq_vals_1[(0) + 3]))
+                            : "r"(csq_smem_addr + (score_base + kk_1) * 4));
+                        float d0_1 = _tmem_load_1[kk_1] - csq_vals_1[0];
+                        float d1_1 = _tmem_load_1[kk_1 + 1] - csq_vals_1[1];
+                        float best_01_1 = d0_1;
+                        int idx_01_1 = off_k_1 + score_base + kk_1;
+                        if (d1_1 > best_01_1) {
+                            best_01_1 = d1_1;
+                            idx_01_1 = off_k_1 + score_base + kk_1 + 1;
+                        }
+                        float d2_1 = _tmem_load_1[kk_1 + 2] - csq_vals_1[2];
+                        float d3_1 = _tmem_load_1[kk_1 + 3] - csq_vals_1[3];
+                        float best_23_1 = d2_1;
+                        int idx_23_1 = off_k_1 + score_base + kk_1 + 2;
+                        if (d3_1 > best_23_1) {
+                            best_23_1 = d3_1;
+                            idx_23_1 = off_k_1 + score_base + kk_1 + 3;
+                        }
+                        float best_group_1 = best_01_1;
+                        int idx_group_1 = idx_01_1;
+                        if (best_23_1 > best_group_1) {
+                            best_group_1 = best_23_1;
+                            idx_group_1 = idx_23_1;
+                        }
+                        if (best_group_1 > best_score) {
+                            best_score = best_group_1;
+                            best_idx = idx_group_1;
+                        }
+                    }
+                }
+                if (global_n < N) {
+                    *((int*)(out + out_offset)) = best_idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0351.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0351.cu
new file mode 100644
index 00000000..fcc7623c
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0351.cu
@@ -0,0 +1,520 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 256
+#define TMEM_SCORE_TMEM_OFFSET 0
+#define NUM_MAIN_STAGES 1
+#define SMEM_SMEM_X_OFF 1024
+#define SMEM_SMEM_X_STAGE_BYTES 4096
+#define SMEM_SMEM_X_STRIDE 4096
+#define SMEM_SMEM_C_OFF 5120
+#define SMEM_SMEM_C_STAGE_BYTES 16384
+#define SMEM_SMEM_C_STRIDE 16384
+#define SMEM_SMEM_CSQ_OFF 21504
+#define SMEM_SMEM_CSQ_STAGE_BYTES 1024
+#define SMEM_SMEM_CSQ_STRIDE 1024
+#define SMEM_TOTAL 22528
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(192) void
+kernel_flash_kmeans_assign_d224_tmem_abi_repair_d17c_v4(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ x_sq, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* smem_x = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int smem_x_addr = smem + 1024;
+    __nv_bfloat16* smem_c = reinterpret_cast<__nv_bfloat16*>(smem_raw + 5120);
+    const int smem_c_addr = smem + 5120;
+    float* smem_csq = reinterpret_cast<float*>(smem_raw + 21504);
+    const int smem_csq_addr = smem + 21504;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // x_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_empty: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // score_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // score_empty: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 40, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (256 columns, 256 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 48);
+    if (warp == 0) {
+        int _tmem_hold = smem + 48;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(256) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define x_empty_addr (mbar_base + 8)
+    #define c_full_addr (mbar_base + 16)
+    #define c_empty_addr (mbar_base + 24)
+    #define score_full_addr (mbar_base + 32)
+    #define score_empty_addr (mbar_base + 40)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_score_tmem = taddr;
+
+    // ---- Role: compute ----
+    if (warp <= 3) {
+        { // compute_main
+            int num_tiles = B * num_n_tiles;
+            int compute_warp = warp;
+            int lane_pair = lane % 4;
+            int row_origin = compute_warp * 16;
+            int row_lane_base = row_origin + lane / 4;
+            int row0 = row_lane_base;
+            int row1 = row_lane_base + 8;
+            int compute_tid = compute_warp * 32 + lane;
+            unsigned int _phase_score_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx = bid; tile_idx < num_tiles; tile_idx += num_bids) {
+                int batch = tile_idx / (unsigned int)num_n_tiles;
+                int n_tile = tile_idx % (unsigned int)num_n_tiles;
+                int off_n = n_tile * 64;
+                int global_n0 = off_n + row0;
+                int global_n1 = off_n + row1;
+                int out_offset0 = batch * N + global_n0;
+                int out_offset1 = batch * N + global_n1;
+                int csq_smem_addr = smem_csq_addr;
+                float best0 = -3.4e+38f;
+                float best1 = -3.4e+38f;
+                int idx0 = 0;
+                int idx1 = 0;
+                #pragma unroll 1
+                for (int iter_k = 0; iter_k < K_tiles; iter_k++) {
+                    int off_k = iter_k * 256;
+                    if ((float)compute_tid < 64.0f) {
+                        int csq_base = compute_tid * 4;
+                        float _vec_load_0[4];
+                        {
+                            float4 _v4 = *reinterpret_cast<const float4*>(c_sq + batch * K + off_k + csq_base);
+                            _vec_load_0[0 + 0] = _v4.x;
+                            _vec_load_0[0 + 1] = _v4.y;
+                            _vec_load_0[0 + 2] = _v4.z;
+                            _vec_load_0[0 + 3] = _v4.w;
+                        }
+                        float csq_half[4];
+                        csq_half[0] = 0.5f * _vec_load_0[0];
+                        csq_half[1] = 0.5f * _vec_load_0[1];
+                        csq_half[2] = 0.5f * _vec_load_0[2];
+                        csq_half[3] = 0.5f * _vec_load_0[3];
+                        asm volatile("st.shared.v4.f32 [%0], {%1,%2,%3,%4};" :: "r"(csq_smem_addr + csq_base * 4), "f"(csq_half[0]), "f"(csq_half[1]), "f"(csq_half[2]), "f"(csq_half[3]) : "memory");
+                    }
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    mbarrier_wait(score_full_addr, _phase_score_full_0);
+                    _phase_score_full_0 ^= 1;
+                    #pragma unroll
+                    for (int score_base = 0; score_base < 256; score_base += 128) {
+                        float _tmem_load_0[64];
+                        asm volatile(
+                            "tcgen05.ld.sync.aligned.16x256b.x16.b32"
+                            " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                            : "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[0])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[1])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[2])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[3])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[4])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[5])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[6])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[7])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[8])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[9])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[10])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[11])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[12])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[13])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[14])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[15])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[16])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[17])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[18])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[19])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[20])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[21])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[22])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[23])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[24])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[25])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[26])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[27])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[28])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[29])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[30])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[31])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[32])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[33])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[34])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[35])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[36])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[37])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[38])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[39])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[40])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[41])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[42])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[43])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[44])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[45])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[46])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[47])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[48])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[49])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[50])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[51])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[52])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[53])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[54])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[55])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[56])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[57])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[58])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[59])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[60])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[61])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[62])), "=r"(*reinterpret_cast<uint32_t*>(&_tmem_load_0[63]))
+                            : "r"(taddr + (unsigned int)score_base)
+                            : "memory");
+                        asm volatile("tcgen05.wait::ld.sync.aligned;");
+                        #pragma unroll
+                        for (int rep = 0; rep < 16.0f; rep++) {
+                            int local_reg = rep * 4;
+                            int col_base = score_base + rep * 8 + lane_pair * 2;
+                            float csq0 = smem_csq[col_base];
+                            float csq1 = smem_csq[col_base + 1];
+                            float d0 = _tmem_load_0[local_reg] - csq0;
+                            if (d0 > best0) {
+                                best0 = d0;
+                                idx0 = off_k + col_base;
+                            }
+                            float d1 = _tmem_load_0[local_reg + 1] - csq1;
+                            if (d1 > best0) {
+                                best0 = d1;
+                                idx0 = off_k + col_base + 1;
+                            }
+                            float d2 = _tmem_load_0[local_reg + 2] - csq0;
+                            if (d2 > best1) {
+                                best1 = d2;
+                                idx1 = off_k + col_base;
+                            }
+                            float d3 = _tmem_load_0[local_reg + 3] - csq1;
+                            if (d3 > best1) {
+                                best1 = d3;
+                                idx1 = off_k + col_base + 1;
+                            }
+                        }
+                    }
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty_addr);
+                    }
+                }
+                float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+                float peer0 = _shfl_xor_0;
+                int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+                int peer0_idx = _shfl_xor_1;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+                peer0 = _shfl_xor_2;
+                int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+                peer0_idx = _shfl_xor_3;
+                if (peer0 > best0) {
+                    best0 = peer0;
+                    idx0 = peer0_idx;
+                }
+                float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+                float peer1 = _shfl_xor_4;
+                int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+                int peer1_idx = _shfl_xor_5;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+                peer1 = _shfl_xor_6;
+                int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+                peer1_idx = _shfl_xor_7;
+                if (peer1 > best1) {
+                    best1 = peer1;
+                    idx1 = peer1_idx;
+                }
+                if (lane_pair == 0) {
+                    if (global_n0 < N) {
+                        *((int*)(out + out_offset0)) = idx0;
+                    }
+                    if (global_n1 < N) {
+                        *((int*)(out + out_offset1)) = idx1;
+                    }
+                }
+            }
+        }
+    // ---- Role: load ----
+    } else if (warp == 4) {
+        { // load_main
+            int num_tiles_1 = B * num_n_tiles;
+            unsigned int _phase_x_empty_0 = 1;
+            unsigned int _phase_c_empty_0 = 1;
+            if (elect_sync()) {
+                #pragma unroll 1
+                for (unsigned int tile_idx_1 = bid; tile_idx_1 < num_tiles_1; tile_idx_1 += num_bids) {
+                    int batch_1 = tile_idx_1 / (unsigned int)num_n_tiles;
+                    int n_tile_1 = tile_idx_1 % (unsigned int)num_n_tiles;
+                    int off_n_1 = n_tile_1 * 64;
+                    int x_row = batch_1 * N + off_n_1;
+                    #pragma unroll 1
+                    for (int iter_k_1 = 0; iter_k_1 < K_tiles; iter_k_1++) {
+                        int off_k_1 = iter_k_1 * 256;
+                        int c_row = batch_1 * K + off_k_1;
+                        #pragma unroll 1
+                        for (int iter_d = 0; iter_d < 7; iter_d++) {
+                            int d_group = iter_d;
+                            mbarrier_wait(x_empty_addr, _phase_x_empty_0);
+                            _phase_x_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_x_addr, x_tmap, 0, x_row, d_group, x_full_addr);
+                            mbarrier_arrive_expect_tx(x_full_addr, 4096);
+                            mbarrier_wait(c_empty_addr, _phase_c_empty_0);
+                            _phase_c_empty_0 ^= 1;
+                            tma_3d_gmem2smem(smem_c_addr, c_tmap, 0, c_row, d_group, c_full_addr);
+                            mbarrier_arrive_expect_tx(c_full_addr, 16384);
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma ----
+    } else if (warp == 5) {
+        { // mma_main
+            int num_tiles_2 = B * num_n_tiles;
+            unsigned int _phase_score_empty_0 = 1;
+            unsigned int _phase_x_full_0 = 0;
+            unsigned int _phase_c_full_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_idx_2 = bid; tile_idx_2 < num_tiles_2; tile_idx_2 += num_bids) {
+                #pragma unroll 1
+                for (int iter_k_2 = 0; iter_k_2 < K_tiles; iter_k_2++) {
+                    mbarrier_wait(score_empty_addr, _phase_score_empty_0);
+                    _phase_score_empty_0 ^= 1;
+                    #pragma unroll 1
+                    for (int iter_d_1 = 0; iter_d_1 < 7; iter_d_1++) {
+                        mbarrier_wait(x_full_addr, _phase_x_full_0);
+                        _phase_x_full_0 ^= 1;
+                        mbarrier_wait(c_full_addr, _phase_c_full_0);
+                        _phase_c_full_0 ^= 1;
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int init_flag = ((iter_d_1 == 0) ? 1 : 0);
+                        int _mma_a_addr_0 = smem_x_addr;
+                        int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                        int _mma_b_addr_0 = smem_c_addr;
+                        int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                        asm volatile(
+                    "{\n\t"
+                    ".reg .pred leader, p0, p1;\n\t"
+                    ".reg .b32 adhi, bdhi, alo, blo, id;\n\t"
+                    ".reg .b64 da, db;\n\t"
+                    "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+                    "setp.ne.b32 p0, %3, 0;\n\t"
+                    "setp.ne.b32 p1, 1, 0;\n\t"
+                    ""
+                    "mov.b32 adhi, 0x80004020;\n\t"
+                    "mov.b32 bdhi, 0x80004020;\n\t"
+                    "mov.b32 id, 71304336;\n\t"
+                    "mov.b32 alo, %0;\n\t"
+                    "mov.b32 blo, %1;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p0;\n\t"
+                    "add.u32 alo, alo, 2;\n\t"
+                    "add.u32 blo, blo, 2;\n\t"
+                    "mov.b64 da, {alo, adhi};\n\t"
+                    "mov.b64 db, {blo, bdhi};\n\t"
+                    "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, id, p1;\n\t"
+                    "}\n"
+                    :: "r"(_mma_a_lo_0), "r"(_mma_b_lo_0), "r"(tmem_score_tmem), "r"(((init_flag) ? 0 : 1)));
+                        elect_commit(x_empty_addr);
+                        elect_commit(c_empty_addr);
+                    }
+                    elect_commit(score_full_addr);
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(256));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0352.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0352.cu
new file mode 100644
index 00000000..482ca687
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0352.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d160_pad192_pack_f9b2_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0353.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0353.cu
new file mode 100644
index 00000000..90ac8670
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0353.cu
@@ -0,0 +1,937 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_SX_OFF 1024
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SC0_OFF 15360
+#define SMEM_SC0_STAGE_BYTES 7168
+#define SMEM_SC0_STRIDE 7168
+#define SMEM_SC1_OFF 22528
+#define SMEM_SC1_STAGE_BYTES 7168
+#define SMEM_SC1_STRIDE 7168
+#define SMEM_TOTAL 29696
+#define THREADS 160
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(160) void
+kernel_flash_kmeans_assign_d112_k1024_owner_local_warp_mma_distinct_workfeed_c829_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int sx_addr = smem + 1024;
+    __nv_bfloat16* sc0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int sc0_addr = smem + 15360;
+    __nv_bfloat16* sc1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sc1_addr = smem + 22528;
+
+    // Mbarrier init (5 groups, 5 barriers)
+    // Mbarriers at smem_raw[0..40)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_full: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_full0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_empty0: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 16, 4, leader);
+        // c_full1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_empty1: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 32, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    __syncthreads();
+
+    const int mbar_base = smem;
+    #define x_full_addr (mbar_base + 0)
+    #define c_full0_addr (mbar_base + 8)
+    #define c_empty0_addr (mbar_base + 16)
+    #define c_full1_addr (mbar_base + 24)
+    #define c_empty1_addr (mbar_base + 32)
+
+    // ---- Role: load ----
+    if (warp == 0) {
+        { // load_main
+            int tile = bid;
+            int batch = tile / num_n_tiles;
+            int nt = tile % num_n_tiles;
+            int point_base = batch * N + nt * 64;
+            unsigned int _phase_c_empty0_0 = 1;
+            unsigned int _phase_c_empty1_0 = 1;
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_full_addr, 14336);
+                cp_async_bulk_gmem2smem(sx_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_full_addr);
+                #pragma unroll 1
+                for (unsigned int pair = 0; pair < 16; pair++) {
+                    int kbase0 = pair * 64;
+                    mbarrier_wait(c_empty0_addr, _phase_c_empty0_0);
+                    _phase_c_empty0_0 ^= 1;
+                    mbarrier_arrive_expect_tx(c_full0_addr, 7168);
+                    cp_async_bulk_gmem2smem(sc0_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + kbase0) * D) * (unsigned long long)2)), 7168, c_full0_addr);
+                    int kbase1 = kbase0 + 32;
+                    mbarrier_wait(c_empty1_addr, _phase_c_empty1_0);
+                    _phase_c_empty1_0 ^= 1;
+                    mbarrier_arrive_expect_tx(c_full1_addr, 7168);
+                    cp_async_bulk_gmem2smem(sc1_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + kbase1) * D) * (unsigned long long)2)), 7168, c_full1_addr);
+                }
+            }
+        }
+    // ---- Role: compute ----
+    } else if (warp >= 1 && warp <= 4) {
+        { // compute_main
+            int tile_1 = bid;
+            int batch_1 = tile_1 / num_n_tiles;
+            int nt_1 = tile_1 % num_n_tiles;
+            int warp_id_in_role = (warp - 1);
+            int row_base = warp_id_in_role * 16;
+            int lane_pair = lane % 4;
+            float best0 = -3.4e+38f;
+            float best1 = -3.4e+38f;
+            int idx0 = 0;
+            int idx1 = 0;
+            unsigned int _phase_x_full_0 = 0;
+            mbarrier_wait(x_full_addr, _phase_x_full_0);
+            _phase_x_full_0 ^= 1;
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int _phase_c_full0_0 = 0;
+            unsigned int _phase_c_full1_0 = 0;
+            #pragma unroll 1
+            for (unsigned int pair_1 = 0; pair_1 < 16; pair_1++) {
+                int kbase0_1 = pair_1 * 64;
+                mbarrier_wait(c_full0_addr, _phase_c_full0_0);
+                _phase_c_full0_0 ^= 1;
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                unsigned int a0[4];
+                unsigned int b00[2];
+                unsigned int b01[2];
+                unsigned int b02[2];
+                unsigned int b03[2];
+                float acc00[4];
+                float acc01[4];
+                float acc02[4];
+                float acc03[4];
+                unsigned int a0_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+                unsigned int b00_addr = (sc0_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b01_addr = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b02_addr = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b03_addr = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc00[0]), "=f"(acc00[1]), "=f"(acc00[2]), "=f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc01[0]), "=f"(acc01[1]), "=f"(acc01[2]), "=f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc02[0]), "=f"(acc02[1]), "=f"(acc02[2]), "=f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc03[0]), "=f"(acc03[1]), "=f"(acc03[2]), "=f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+                unsigned int b00_addr_1 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_2 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_3 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_4 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_0)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_1)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_2)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_3)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_4)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_5 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+                unsigned int b00_addr_6 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_7 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_8 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_9 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_5)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_6)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_7)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_8)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_9)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+                unsigned int b00_addr_11 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_12 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_13 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_14 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_10)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_11)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_12)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_13)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_14)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_15 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+                unsigned int b00_addr_16 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_17 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_18 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_19 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_15)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_16)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_17)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_18)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_19)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_20 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+                unsigned int b00_addr_21 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_22 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_23 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_24 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_20)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_21)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_22)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_23)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_24)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                unsigned int a0_addr_25 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+                unsigned int b00_addr_26 = (sc0_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b01_addr_27 = (sc0_addr + (unsigned int)((8 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b02_addr_28 = (sc0_addr + (unsigned int)((16 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b03_addr_29 = (sc0_addr + (unsigned int)((24 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a0[0]), "=r"(a0[1]), "=r"(a0[2]), "=r"(a0[3])
+                    : "r"(a0_addr_25)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b00[0]), "=r"(b00[1])
+                    : "r"(b00_addr_26)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b01[0]), "=r"(b01[1])
+                    : "r"(b01_addr_27)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b02[0]), "=r"(b02[1])
+                    : "r"(b02_addr_28)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b03[0]), "=r"(b03[1])
+                    : "r"(b03_addr_29)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc00[0]), "+f"(acc00[1]), "+f"(acc00[2]), "+f"(acc00[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b00[0]), "r"(b00[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc01[0]), "+f"(acc01[1]), "+f"(acc01[2]), "+f"(acc01[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b01[0]), "r"(b01[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc02[0]), "+f"(acc02[1]), "+f"(acc02[2]), "+f"(acc02[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b02[0]), "r"(b02[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc03[0]), "+f"(acc03[1]), "+f"(acc03[2]), "+f"(acc03[3])
+                    : "r"(a0[0]), "r"(a0[1]), "r"(a0[2]), "r"(a0[3]), "r"(b03[0]), "r"(b03[1]));
+                float vals0[8];
+                float vals1[8];
+                vals0[0] = acc00[0];
+                vals0[1] = acc00[1];
+                vals0[2] = acc01[0];
+                vals0[3] = acc01[1];
+                vals0[4] = acc02[0];
+                vals0[5] = acc02[1];
+                vals0[6] = acc03[0];
+                vals0[7] = acc03[1];
+                vals1[0] = acc00[2];
+                vals1[1] = acc00[3];
+                vals1[2] = acc01[2];
+                vals1[3] = acc01[3];
+                vals1[4] = acc02[2];
+                vals1[5] = acc02[3];
+                vals1[6] = acc03[2];
+                vals1[7] = acc03[3];
+                #pragma unroll
+                for (int vi0 = 0; vi0 < 8; vi0++) {
+                    int col0 = vi0 / 2 * 8 + lane_pair * 2 + vi0 % 2;
+                    float cand0 = vals0[vi0] - 0.5f * c_sq[batch_1 * K + kbase0_1 + col0];
+                    int cand_idx0 = kbase0_1 + col0;
+                    bool take0 = cand0 > best0;
+                    if (cand0 == best0) {
+                        if (cand_idx0 < idx0) {
+                            take0 = 1;
+                        }
+                    }
+                    if (take0) {
+                        best0 = cand0;
+                        idx0 = cand_idx0;
+                    }
+                    float cand1 = vals1[vi0] - 0.5f * c_sq[batch_1 * K + kbase0_1 + col0];
+                    int cand_idx1 = kbase0_1 + col0;
+                    bool take1 = cand1 > best1;
+                    if (cand1 == best1) {
+                        if (cand_idx1 < idx1) {
+                            take1 = 1;
+                        }
+                    }
+                    if (take1) {
+                        best1 = cand1;
+                        idx1 = cand_idx1;
+                    }
+                }
+                __syncwarp();
+                if (elect_sync()) {
+                    mbarrier_arrive(c_empty0_addr);
+                }
+                int kbase1_1 = kbase0_1 + 32;
+                mbarrier_wait(c_full1_addr, _phase_c_full1_0);
+                _phase_c_full1_0 ^= 1;
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                unsigned int a1[4];
+                unsigned int b10[2];
+                unsigned int b11[2];
+                unsigned int b12[2];
+                unsigned int b13[2];
+                float acc10[4];
+                float acc11[4];
+                float acc12[4];
+                float acc13[4];
+                unsigned int a1_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+                unsigned int b10_addr = (sc1_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b11_addr = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b12_addr = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                unsigned int b13_addr = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (lane / 8 & 1) * 8 * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc10[0]), "=f"(acc10[1]), "=f"(acc10[2]), "=f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc11[0]), "=f"(acc11[1]), "=f"(acc11[2]), "=f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc12[0]), "=f"(acc12[1]), "=f"(acc12[2]), "=f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                    : "=f"(acc13[0]), "=f"(acc13[1]), "=f"(acc13[2]), "=f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_30 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+                unsigned int b10_addr_31 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_32 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_33 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_34 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (16 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_30)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_31)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_32)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_33)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_34)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_35 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+                unsigned int b10_addr_36 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_37 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_38 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_39 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (32 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_35)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_36)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_37)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_38)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_39)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_40 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+                unsigned int b10_addr_41 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_42 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_43 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_44 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (48 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_40)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_41)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_42)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_43)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_44)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_45 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+                unsigned int b10_addr_46 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_47 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_48 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_49 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (64 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_45)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_46)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_47)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_48)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_49)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_50 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+                unsigned int b10_addr_51 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_52 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_53 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_54 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (80 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_50)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_51)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_52)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_53)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_54)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                unsigned int a1_addr_55 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+                unsigned int b10_addr_56 = (sc1_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b11_addr_57 = (sc1_addr + (unsigned int)((8 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b12_addr_58 = (sc1_addr + (unsigned int)((16 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                unsigned int b13_addr_59 = (sc1_addr + (unsigned int)((24 + lane % 8) * 224 + (96 + (lane / 8 & 1) * 8) * 2));
+                asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                    : "=r"(a1[0]), "=r"(a1[1]), "=r"(a1[2]), "=r"(a1[3])
+                    : "r"(a1_addr_55)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b10[0]), "=r"(b10[1])
+                    : "r"(b10_addr_56)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b11[0]), "=r"(b11[1])
+                    : "r"(b11_addr_57)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b12[0]), "=r"(b12[1])
+                    : "r"(b12_addr_58)
+                    : "memory");
+                asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                    : "=r"(b13[0]), "=r"(b13[1])
+                    : "r"(b13_addr_59)
+                    : "memory");
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc10[0]), "+f"(acc10[1]), "+f"(acc10[2]), "+f"(acc10[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b10[0]), "r"(b10[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc11[0]), "+f"(acc11[1]), "+f"(acc11[2]), "+f"(acc11[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b11[0]), "r"(b11[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc12[0]), "+f"(acc12[1]), "+f"(acc12[2]), "+f"(acc12[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b12[0]), "r"(b12[1]));
+                asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                    : "+f"(acc13[0]), "+f"(acc13[1]), "+f"(acc13[2]), "+f"(acc13[3])
+                    : "r"(a1[0]), "r"(a1[1]), "r"(a1[2]), "r"(a1[3]), "r"(b13[0]), "r"(b13[1]));
+                float vals10[8];
+                float vals11[8];
+                vals10[0] = acc10[0];
+                vals10[1] = acc10[1];
+                vals10[2] = acc11[0];
+                vals10[3] = acc11[1];
+                vals10[4] = acc12[0];
+                vals10[5] = acc12[1];
+                vals10[6] = acc13[0];
+                vals10[7] = acc13[1];
+                vals11[0] = acc10[2];
+                vals11[1] = acc10[3];
+                vals11[2] = acc11[2];
+                vals11[3] = acc11[3];
+                vals11[4] = acc12[2];
+                vals11[5] = acc12[3];
+                vals11[6] = acc13[2];
+                vals11[7] = acc13[3];
+                #pragma unroll
+                for (int vi1 = 0; vi1 < 8; vi1++) {
+                    int col1 = vi1 / 2 * 8 + lane_pair * 2 + vi1 % 2;
+                    float cand10 = vals10[vi1] - 0.5f * c_sq[batch_1 * K + kbase1_1 + col1];
+                    int cand_idx10 = kbase1_1 + col1;
+                    bool take10 = cand10 > best0;
+                    if (cand10 == best0) {
+                        if (cand_idx10 < idx0) {
+                            take10 = 1;
+                        }
+                    }
+                    if (take10) {
+                        best0 = cand10;
+                        idx0 = cand_idx10;
+                    }
+                    float cand11 = vals11[vi1] - 0.5f * c_sq[batch_1 * K + kbase1_1 + col1];
+                    int cand_idx11 = kbase1_1 + col1;
+                    bool take11 = cand11 > best1;
+                    if (cand11 == best1) {
+                        if (cand_idx11 < idx1) {
+                            take11 = 1;
+                        }
+                    }
+                    if (take11) {
+                        best1 = cand11;
+                        idx1 = cand_idx11;
+                    }
+                }
+                __syncwarp();
+                if (elect_sync()) {
+                    mbarrier_arrive(c_empty1_addr);
+                }
+            }
+            float _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best0, 1);
+            float peer0 = _shfl_xor_0;
+            int _shfl_xor_1 = __shfl_xor_sync(0xFFFFFFFF, idx0, 1);
+            int peer_idx0 = _shfl_xor_1;
+            if (peer0 > best0) {
+                best0 = peer0;
+                idx0 = peer_idx0;
+            }
+            if (peer0 == best0) {
+                if (peer_idx0 < idx0) {
+                    idx0 = peer_idx0;
+                }
+            }
+            float _shfl_xor_2 = __shfl_xor_sync(0xFFFFFFFF, best0, 2);
+            peer0 = _shfl_xor_2;
+            int _shfl_xor_3 = __shfl_xor_sync(0xFFFFFFFF, idx0, 2);
+            peer_idx0 = _shfl_xor_3;
+            if (peer0 > best0) {
+                best0 = peer0;
+                idx0 = peer_idx0;
+            }
+            if (peer0 == best0) {
+                if (peer_idx0 < idx0) {
+                    idx0 = peer_idx0;
+                }
+            }
+            float _shfl_xor_4 = __shfl_xor_sync(0xFFFFFFFF, best1, 1);
+            float peer1 = _shfl_xor_4;
+            int _shfl_xor_5 = __shfl_xor_sync(0xFFFFFFFF, idx1, 1);
+            int peer_idx1 = _shfl_xor_5;
+            if (peer1 > best1) {
+                best1 = peer1;
+                idx1 = peer_idx1;
+            }
+            if (peer1 == best1) {
+                if (peer_idx1 < idx1) {
+                    idx1 = peer_idx1;
+                }
+            }
+            float _shfl_xor_6 = __shfl_xor_sync(0xFFFFFFFF, best1, 2);
+            peer1 = _shfl_xor_6;
+            int _shfl_xor_7 = __shfl_xor_sync(0xFFFFFFFF, idx1, 2);
+            peer_idx1 = _shfl_xor_7;
+            if (peer1 > best1) {
+                best1 = peer1;
+                idx1 = peer_idx1;
+            }
+            if (peer1 == best1) {
+                if (peer_idx1 < idx1) {
+                    idx1 = peer_idx1;
+                }
+            }
+            if (lane_pair == 0) {
+                int row0 = row_base + lane / 4;
+                *((int*)(out + (batch_1 * N + nt_1 * 64 + row0))) = idx0;
+                *((int*)(out + (batch_1 * N + nt_1 * 64 + row0 + 8))) = idx1;
+            }
+        }
+    }
+
+    // Cleanup
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
new file mode 100644
index 00000000..fad9fa7f
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
@@ -0,0 +1,540 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_PEER_KEYS_OFF 42496
+#define SMEM_PEER_KEYS_STAGE_BYTES 512
+#define SMEM_PEER_KEYS_STRIDE 512
+#define SMEM_TOTAL 43008
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 2;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 2;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* peer_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int peer_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 6 barriers)
+    // Mbarriers at smem_raw[0..48)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // peer_keys_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 40, 1, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define peer_keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_peer_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3856035760 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3856035760 = *(uint16_t*)&_bval_3856035760;
+                uint32_t _addr_3856035760 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3856035760), "h"(_bits_3856035760) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 16;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3856021056 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3856021056), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (cta_rank == 1) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    uint32_t _mapa_0;
+                    asm volatile(
+                        "mapa.shared::cluster.u32 %0, %1, %2;"
+                        : "=r"(_mapa_0) : "r"(peer_keys_addr), "r"(0));
+                    uint32_t _mapa_1;
+                    asm volatile(
+                        "mapa.shared::cluster.u32 %0, %1, %2;"
+                        : "=r"(_mapa_1) : "r"(peer_keys_ready_addr), "r"(0));
+                    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                    asm volatile(
+                        "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                        :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                    asm volatile(
+                        "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                        " [%0], [%1], %2, [%3];"
+                        :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_1)
+                        : "memory");
+                }
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(peer_keys_ready_addr, _phase_peer_keys_ready_0);
+            _phase_peer_keys_ready_0 ^= 1;
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            int row_1 = tid;
+            if (row_1 < 64) {
+                unsigned long long local_key = local_keys[row_1];
+                unsigned long long peer_key = peer_keys[row_1];
+                unsigned long long best_key = ((peer_key > local_key) ? peer_key : local_key);
+                unsigned long long mask64_1 = 4294967295;
+                int idx = (int)(mask64_1 - (best_key & mask64_1));
+                *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0355.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0355.cu
new file mode 100644
index 00000000..b875687d
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0355.cu
@@ -0,0 +1,628 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+#define LOOM_INF CUDART_INF_F
+#define TMEM_NCOLS 128
+#define TMEM_SCORES0_OFFSET 0
+#define TMEM_SCORES1_OFFSET 64
+#define NUM_X_PIPE_STAGES 7
+#define SMEM_SX_OFF 1024
+#define SMEM_SX_STAGE_BYTES 4096
+#define SMEM_SX_STRIDE 4096
+#define SMEM_SC0_OFF 29696
+#define SMEM_SC0_STAGE_BYTES 2048
+#define SMEM_SC0_STRIDE 2048
+#define SMEM_SC1_OFF 31744
+#define SMEM_SC1_STAGE_BYTES 2048
+#define SMEM_SC1_STRIDE 2048
+#define SMEM_SLOT0_KEYS_OFF 33792
+#define SMEM_SLOT0_KEYS_STAGE_BYTES 1024
+#define SMEM_SLOT0_KEYS_STRIDE 1024
+#define SMEM_SLOT1_KEYS_OFF 34816
+#define SMEM_SLOT1_KEYS_STAGE_BYTES 1024
+#define SMEM_SLOT1_KEYS_STRIDE 1024
+#define SMEM_TOTAL 35840
+#define THREADS 416
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void tcgen05_mma_f16(
+    int taddr, uint64_t a_desc, uint64_t b_desc,
+    uint32_t i_desc, int enable_input_d) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, p;\n\t"
+        "}\n"
+        :: "r"(taddr), "l"(a_desc), "l"(b_desc),
+           "r"(i_desc), "r"(enable_input_d));
+}
+
+
+__device__ __forceinline__ uint64_t desc_encode(uint64_t x) {
+    return (x & 0x3FFFFULL) >> 4ULL;
+}
+
+
+__device__ __forceinline__ void mma_ss_step(
+    int a_lo, int b_lo, int taddr, uint32_t i_desc, int enable_d,
+    uint32_t a_dhi, uint32_t b_dhi) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader, p;\n\t"
+        ".reg .b32 adhi, bdhi;\n\t"
+        ".reg .b64 da, db;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "mov.b32 adhi, %5;\n\t"
+        "mov.b32 bdhi, %6;\n\t"
+        "mov.b64 da, {%0, adhi};\n\t"
+        "mov.b64 db, {%1, bdhi};\n\t"
+        "@leader tcgen05.mma.cta_group::1.kind::f16 [%2], da, db, %3, p;\n\t"
+        "}\n"
+        :: "r"(a_lo), "r"(b_lo), "r"(taddr), "r"(i_desc), "r"(enable_d), "r"(a_dhi), "r"(b_dhi));
+}
+
+
+__device__ __forceinline__ void elect_commit(int mbar_addr) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred leader;\n\t"
+        "elect.sync _|leader, 0xFFFFFFFF;\n\t"
+        "@leader tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];\n\t"
+        "}\n"
+        :: "r"(mbar_addr));
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ uint64_t make_smem_desc(int addr) {
+    const int SBO = 1024;
+    return desc_encode(addr)
+         | (desc_encode(SBO) << 32ULL)
+         | (1ULL << 46ULL)
+         | (2ULL << 61ULL);
+}
+
+
+__device__ __forceinline__ void tma_3d_gmem2smem(
+    int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.tensor.3d.shared::cta.global"
+        ".mbarrier::complete_tx::bytes"
+        " [%0], [%1, {%2, %3, %4}], [%5];"
+        :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z),
+           "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tcgen05_commit(int mbar_addr) {
+    asm volatile(
+        "tcgen05.commit.cta_group::1.mbarrier::arrive::one"
+        ".shared::cluster.b64 [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16(float* dst, int tmem_addr) {
+    asm volatile(
+        "tcgen05.ld.sync.aligned.32x32b.x16.b32"
+        " {%0, %1, %2, %3, %4, %5, %6, %7,"
+        "  %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"
+        : "=f"(dst[0]),  "=f"(dst[1]),  "=f"(dst[2]),  "=f"(dst[3]),
+          "=f"(dst[4]),  "=f"(dst[5]),  "=f"(dst[6]),  "=f"(dst[7]),
+          "=f"(dst[8]),  "=f"(dst[9]),  "=f"(dst[10]), "=f"(dst[11]),
+          "=f"(dst[12]), "=f"(dst[13]), "=f"(dst[14]), "=f"(dst[15])
+        : "r"(tmem_addr));
+}
+
+
+__device__ __forceinline__ void tmem_ld_x16_wait(float* dst, int addr) {
+    tmem_ld_x16(dst, addr);
+    asm volatile("tcgen05.wait::ld.sync.aligned;");
+}
+
+
+__device__ __forceinline__ uint32_t make_warp_uniform(uint32_t val) {
+    uint32_t result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1f, 0xffffffff;"
+        : "=r"(result) : "r"(val));
+    return result;
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(416) void
+kernel_flash_kmeans_assign_d112_shared_point_dual_issuer_tcgen05_6e1e_v1(const void* __restrict__ x_tmap, const void* __restrict__ c_tmap, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles, int K_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // Kernel setup ops
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int sx_addr = smem + 1024;
+    __nv_bfloat16* sc0 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 29696);
+    const int sc0_addr = smem + 29696;
+    __nv_bfloat16* sc1 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 31744);
+    const int sc1_addr = smem + 31744;
+    unsigned long long* slot0_keys = reinterpret_cast<unsigned long long*>(smem_raw + 33792);
+    const int slot0_keys_addr = smem + 33792;
+    unsigned long long* slot1_keys = reinterpret_cast<unsigned long long*>(smem_raw + 34816);
+    const int slot1_keys_addr = smem + 34816;
+
+    // Mbarrier init (14 groups, 20 barriers)
+    // Mbarriers at smem_raw[0..160)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // --- pipeline 'x_pipe' ---
+        // x_tma_full: 7 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        mbarrier_init_pred(smem + 8, 1, leader);
+        mbarrier_init_pred(smem + 16, 1, leader);
+        mbarrier_init_pred(smem + 24, 1, leader);
+        mbarrier_init_pred(smem + 32, 1, leader);
+        mbarrier_init_pred(smem + 40, 1, leader);
+        mbarrier_init_pred(smem + 48, 1, leader);
+        // x_ready0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 56, 1, leader);
+        // x_empty0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 64, 1, leader);
+        // x_ready1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 72, 1, leader);
+        // x_empty1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 80, 1, leader);
+        // c_full0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 88, 1, leader);
+        // c_empty0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 96, 1, leader);
+        // c_full1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 104, 1, leader);
+        // c_empty1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 112, 1, leader);
+        // score_full0: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 120, 1, leader);
+        // score_empty0: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 128, 4, leader);
+        // score_full1: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 136, 1, leader);
+        // score_empty1: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 144, 4, leader);
+        // slot1_keys_ready: 1 barriers, init_count=4
+        mbarrier_init_pred(smem + 152, 4, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    // TMEM alloc (128 columns, 128 used)
+    volatile int* tmem_addr_storage = (volatile int*)(smem_raw + 160);
+    if (warp == 0) {
+        int _tmem_hold = smem + 160;
+        asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(_tmem_hold), "r"(128) : "memory");
+    }
+
+    __syncthreads();
+    asm volatile("tcgen05.fence::after_thread_sync;");
+
+    const int mbar_base = smem;
+    #define x_tma_full_addr (mbar_base + 0)
+    #define x_ready0_addr (mbar_base + 56)
+    #define x_empty0_addr (mbar_base + 64)
+    #define x_ready1_addr (mbar_base + 72)
+    #define x_empty1_addr (mbar_base + 80)
+    #define c_full0_addr (mbar_base + 88)
+    #define c_empty0_addr (mbar_base + 96)
+    #define c_full1_addr (mbar_base + 104)
+    #define c_empty1_addr (mbar_base + 112)
+    #define score_full0_addr (mbar_base + 120)
+    #define score_empty0_addr (mbar_base + 128)
+    #define score_full1_addr (mbar_base + 136)
+    #define score_empty1_addr (mbar_base + 144)
+    #define slot1_keys_ready_addr (mbar_base + 152)
+    const int taddr = tmem_addr_storage[0];
+
+    // Kernel post-init ops
+    const int tmem_scores0 = taddr;
+    const int tmem_scores1 = taddr + 64;
+
+    // ---- Role: x_load ----
+    if (warp == 0) {
+        { // x_load_main
+            int total_tiles = B * num_n_tiles;
+            unsigned int _phase_x_empty0_0 = 1;
+            unsigned int _phase_x_empty1_0 = 1;
+            unsigned int _phase_x_tma_full = 0;
+            #pragma unroll 1
+            for (unsigned int tile = bid; tile < total_tiles; tile += num_bids) {
+                int point_row = tile / (unsigned int)num_n_tiles * (unsigned int)N + tile % (unsigned int)num_n_tiles * 128;
+                mbarrier_wait(x_empty0_addr, _phase_x_empty0_0);
+                _phase_x_empty0_0 ^= 1;
+                mbarrier_wait(x_empty1_addr, _phase_x_empty1_0);
+                _phase_x_empty1_0 ^= 1;
+                if (warp == 0) {
+                    if (elect_sync()) {
+                        #pragma unroll
+                        for (int ft = 0; ft < 7; ft++) {
+                            mbarrier_arrive_expect_tx(x_tma_full_addr + (ft) * 8, 4096);
+                            tma_3d_gmem2smem(sx_addr + (unsigned int)(ft * 4096), x_tmap, 0, point_row, ft, x_tma_full_addr + (ft) * 8);
+                        }
+                    }
+                }
+                #pragma unroll
+                for (int ft_1 = 0; ft_1 < 7; ft_1++) {
+                    mbarrier_wait(x_tma_full_addr + (ft_1) * 8, _phase_x_tma_full);
+                }
+                asm volatile("fence.proxy.async;");
+                if (warp == 0) {
+                    if (elect_sync()) {
+                        mbarrier_arrive(x_ready0_addr);
+                        mbarrier_arrive(x_ready1_addr);
+                    }
+                }
+            }
+        }
+    // ---- Role: c_load0 ----
+    } else if (warp == 1) {
+        { // c_load0_main
+            int total_tiles_1 = B * num_n_tiles;
+            int owner_tiles = K_tiles / 2;
+            unsigned int _phase_c_empty0_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_1 = bid; tile_1 < total_tiles_1; tile_1 += num_bids) {
+                int batch = tile_1 / (unsigned int)num_n_tiles;
+                if (warp == 1) {
+                    if (elect_sync()) {
+                        #pragma unroll 1
+                        for (int owner_kt = 0; owner_kt < owner_tiles; owner_kt++) {
+                            int kt = owner_kt * 2;
+                            int centroid_row = batch * K + kt * 64;
+                            #pragma unroll
+                            for (int ft_2 = 0; ft_2 < 7; ft_2++) {
+                                mbarrier_wait(c_empty0_addr, _phase_c_empty0_0);
+                                _phase_c_empty0_0 ^= 1;
+                                mbarrier_arrive_expect_tx(c_full0_addr, 2048);
+                                tma_3d_gmem2smem(sc0_addr, c_tmap, 0, centroid_row, ft_2, c_full0_addr);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: c_load1 ----
+    } else if (warp == 2) {
+        { // c_load1_main
+            int total_tiles_2 = B * num_n_tiles;
+            int owner_tiles_1 = K_tiles / 2;
+            unsigned int _phase_c_empty1_0 = 1;
+            #pragma unroll 1
+            for (unsigned int tile_2 = bid; tile_2 < total_tiles_2; tile_2 += num_bids) {
+                int batch_1 = tile_2 / (unsigned int)num_n_tiles;
+                if (warp == 2) {
+                    if (elect_sync()) {
+                        #pragma unroll 1
+                        for (int owner_kt_1 = 0; owner_kt_1 < owner_tiles_1; owner_kt_1++) {
+                            int kt_1 = owner_kt_1 * 2 + 1;
+                            int centroid_row_1 = batch_1 * K + kt_1 * 64;
+                            #pragma unroll
+                            for (int ft_3 = 0; ft_3 < 7; ft_3++) {
+                                mbarrier_wait(c_empty1_addr, _phase_c_empty1_0);
+                                _phase_c_empty1_0 ^= 1;
+                                mbarrier_arrive_expect_tx(c_full1_addr, 2048);
+                                tma_3d_gmem2smem(sc1_addr, c_tmap, 0, centroid_row_1, ft_3, c_full1_addr);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    // ---- Role: mma0 ----
+    } else if (warp == 3) {
+        { // mma0_main
+            int total_tiles_3 = B * num_n_tiles;
+            int owner_tiles_2 = K_tiles / 2;
+            unsigned int _phase_x_ready0_0 = 0;
+            unsigned int _phase_score_empty0_0 = 1;
+            unsigned int _phase_c_full0_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_3 = bid; tile_3 < total_tiles_3; tile_3 += num_bids) {
+                mbarrier_wait(x_ready0_addr, _phase_x_ready0_0);
+                _phase_x_ready0_0 ^= 1;
+                #pragma unroll 1
+                for (int owner_kt_2 = 0; owner_kt_2 < owner_tiles_2; owner_kt_2++) {
+                    mbarrier_wait(score_empty0_addr, _phase_score_empty0_0);
+                    _phase_score_empty0_0 ^= 1;
+                    mbarrier_wait(c_full0_addr, _phase_c_full0_0);
+                    _phase_c_full0_0 ^= 1;
+                    asm volatile("fence.proxy.async;");
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_0 = sx_addr;
+                    int _mma_a_lo_0 = make_warp_uniform((_mma_a_addr_0 >> 4) & 0x3FFF);
+                    int _mma_b_addr_0 = sc0_addr;
+                    int _mma_b_lo_0 = make_warp_uniform((_mma_b_addr_0 >> 4) & 0x3FFF);
+                    mma_ss_step(_mma_a_lo_0, _mma_b_lo_0, tmem_scores0, 135267472, 0, 0xC0004010U, 0xC0004010U);
+                    elect_commit(c_empty0_addr);
+                    #pragma unroll
+                    for (int ft_4 = 1; ft_4 < 7; ft_4++) {
+                        mbarrier_wait(c_full0_addr, _phase_c_full0_0);
+                        _phase_c_full0_0 ^= 1;
+                        asm volatile("fence.proxy.async;");
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int _mma_a_addr_1 = sx_addr + (unsigned int)(ft_4 * 4096);
+                        int _mma_a_lo_1 = make_warp_uniform((_mma_a_addr_1 >> 4) & 0x3FFF);
+                        int _mma_b_addr_1 = sc0_addr;
+                        int _mma_b_lo_1 = make_warp_uniform((_mma_b_addr_1 >> 4) & 0x3FFF);
+                        mma_ss_step(_mma_a_lo_1, _mma_b_lo_1, tmem_scores0, 135267472, 1, 0xC0004010U, 0xC0004010U);
+                        elect_commit(c_empty0_addr);
+                    }
+                    elect_commit(score_full0_addr);
+                }
+                elect_commit(x_empty0_addr);
+            }
+        }
+    // ---- Role: compute0 ----
+    } else if (warp >= 4 && warp <= 7) {
+        { // compute0_main
+            int total_tiles_4 = B * num_n_tiles;
+            int owner_tiles_3 = K_tiles / 2;
+            int warp_id_in_role = (warp - 4);
+            int row = warp_id_in_role * 32 + lane;
+            int row_base = warp_id_in_role * 32 << 16;
+            unsigned int _phase_score_full0_0 = 0;
+            unsigned int _phase_slot1_keys_ready_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_4 = bid; tile_4 < total_tiles_4; tile_4 += num_bids) {
+                int batch_2 = tile_4 / (unsigned int)num_n_tiles;
+                int nt = tile_4 % (unsigned int)num_n_tiles;
+                float best = -3.4e+38f;
+                int best_idx = 0;
+                #pragma unroll 1
+                for (int owner_kt_3 = 0; owner_kt_3 < owner_tiles_3; owner_kt_3++) {
+                    int kt_2 = owner_kt_3 * 2;
+                    int kb = kt_2 * 64;
+                    mbarrier_wait(score_full0_addr, _phase_score_full0_0);
+                    _phase_score_full0_0 ^= 1;
+                    float _tmem_load_0[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x64.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=f"(_tmem_load_0[0]), "=f"(_tmem_load_0[1]), "=f"(_tmem_load_0[2]), "=f"(_tmem_load_0[3]), "=f"(_tmem_load_0[4]), "=f"(_tmem_load_0[5]), "=f"(_tmem_load_0[6]), "=f"(_tmem_load_0[7]), "=f"(_tmem_load_0[8]), "=f"(_tmem_load_0[9]), "=f"(_tmem_load_0[10]), "=f"(_tmem_load_0[11]), "=f"(_tmem_load_0[12]), "=f"(_tmem_load_0[13]), "=f"(_tmem_load_0[14]), "=f"(_tmem_load_0[15]), "=f"(_tmem_load_0[16]), "=f"(_tmem_load_0[17]), "=f"(_tmem_load_0[18]), "=f"(_tmem_load_0[19]), "=f"(_tmem_load_0[20]), "=f"(_tmem_load_0[21]), "=f"(_tmem_load_0[22]), "=f"(_tmem_load_0[23]), "=f"(_tmem_load_0[24]), "=f"(_tmem_load_0[25]), "=f"(_tmem_load_0[26]), "=f"(_tmem_load_0[27]), "=f"(_tmem_load_0[28]), "=f"(_tmem_load_0[29]), "=f"(_tmem_load_0[30]), "=f"(_tmem_load_0[31]), "=f"(_tmem_load_0[32]), "=f"(_tmem_load_0[33]), "=f"(_tmem_load_0[34]), "=f"(_tmem_load_0[35]), "=f"(_tmem_load_0[36]), "=f"(_tmem_load_0[37]), "=f"(_tmem_load_0[38]), "=f"(_tmem_load_0[39]), "=f"(_tmem_load_0[40]), "=f"(_tmem_load_0[41]), "=f"(_tmem_load_0[42]), "=f"(_tmem_load_0[43]), "=f"(_tmem_load_0[44]), "=f"(_tmem_load_0[45]), "=f"(_tmem_load_0[46]), "=f"(_tmem_load_0[47]), "=f"(_tmem_load_0[48]), "=f"(_tmem_load_0[49]), "=f"(_tmem_load_0[50]), "=f"(_tmem_load_0[51]), "=f"(_tmem_load_0[52]), "=f"(_tmem_load_0[53]), "=f"(_tmem_load_0[54]), "=f"(_tmem_load_0[55]), "=f"(_tmem_load_0[56]), "=f"(_tmem_load_0[57]), "=f"(_tmem_load_0[58]), "=f"(_tmem_load_0[59]), "=f"(_tmem_load_0[60]), "=f"(_tmem_load_0[61]), "=f"(_tmem_load_0[62]), "=f"(_tmem_load_0[63])
+                        : "r"(taddr + (unsigned int)row_base)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 8, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty0_addr);
+                    }
+                    #pragma unroll
+                    for (int kk = 0; kk < 64; kk++) {
+                        float score = _tmem_load_0[kk] - 0.5f * c_sq[batch_2 * K + kb + kk];
+                        if (score > best) {
+                            best = score;
+                            best_idx = kb + kk;
+                        }
+                    }
+                }
+                uint32_t _amf_u_0 = __float_as_uint(best);
+                uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+                unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+                slot0_keys[row] = (unsigned long long)_amf_enc_0 << 32 | 4294967295 - (unsigned long long)best_idx;
+                asm volatile("barrier.sync 10, %0;" :: "r"(128));
+                mbarrier_wait(slot1_keys_ready_addr, _phase_slot1_keys_ready_0);
+                _phase_slot1_keys_ready_0 ^= 1;
+                unsigned long long peer_key = slot1_keys[row];
+                unsigned long long own_key = slot0_keys[row];
+                unsigned long long best_key = ((peer_key > own_key) ? peer_key : own_key);
+                int idx = (int)(4294967295 - (best_key & 4294967295));
+                *((int*)(out + (batch_2 * N + nt * 128 + row))) = idx;
+            }
+        }
+    // ---- Role: compute1 ----
+    } else if (warp >= 8 && warp <= 11) {
+        { // compute1_main
+            int total_tiles_5 = B * num_n_tiles;
+            int owner_tiles_4 = K_tiles / 2;
+            int warp_id_in_role_1 = (warp - 8);
+            int row_1 = warp_id_in_role_1 * 32 + lane;
+            int row_base_1 = warp_id_in_role_1 * 32 << 16;
+            unsigned int _phase_score_full1_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_5 = bid; tile_5 < total_tiles_5; tile_5 += num_bids) {
+                int batch_3 = tile_5 / (unsigned int)num_n_tiles;
+                float best_1 = -3.4e+38f;
+                int best_idx_1 = 64;
+                #pragma unroll 1
+                for (int owner_kt_4 = 0; owner_kt_4 < owner_tiles_4; owner_kt_4++) {
+                    int kt_3 = owner_kt_4 * 2 + 1;
+                    int kb_1 = kt_3 * 64;
+                    mbarrier_wait(score_full1_addr, _phase_score_full1_0);
+                    _phase_score_full1_0 ^= 1;
+                    float _tmem_load_1[64];
+                    asm volatile(
+                        "tcgen05.ld.sync.aligned.32x32b.x64.b32"
+                        " {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
+                        : "=f"(_tmem_load_1[0]), "=f"(_tmem_load_1[1]), "=f"(_tmem_load_1[2]), "=f"(_tmem_load_1[3]), "=f"(_tmem_load_1[4]), "=f"(_tmem_load_1[5]), "=f"(_tmem_load_1[6]), "=f"(_tmem_load_1[7]), "=f"(_tmem_load_1[8]), "=f"(_tmem_load_1[9]), "=f"(_tmem_load_1[10]), "=f"(_tmem_load_1[11]), "=f"(_tmem_load_1[12]), "=f"(_tmem_load_1[13]), "=f"(_tmem_load_1[14]), "=f"(_tmem_load_1[15]), "=f"(_tmem_load_1[16]), "=f"(_tmem_load_1[17]), "=f"(_tmem_load_1[18]), "=f"(_tmem_load_1[19]), "=f"(_tmem_load_1[20]), "=f"(_tmem_load_1[21]), "=f"(_tmem_load_1[22]), "=f"(_tmem_load_1[23]), "=f"(_tmem_load_1[24]), "=f"(_tmem_load_1[25]), "=f"(_tmem_load_1[26]), "=f"(_tmem_load_1[27]), "=f"(_tmem_load_1[28]), "=f"(_tmem_load_1[29]), "=f"(_tmem_load_1[30]), "=f"(_tmem_load_1[31]), "=f"(_tmem_load_1[32]), "=f"(_tmem_load_1[33]), "=f"(_tmem_load_1[34]), "=f"(_tmem_load_1[35]), "=f"(_tmem_load_1[36]), "=f"(_tmem_load_1[37]), "=f"(_tmem_load_1[38]), "=f"(_tmem_load_1[39]), "=f"(_tmem_load_1[40]), "=f"(_tmem_load_1[41]), "=f"(_tmem_load_1[42]), "=f"(_tmem_load_1[43]), "=f"(_tmem_load_1[44]), "=f"(_tmem_load_1[45]), "=f"(_tmem_load_1[46]), "=f"(_tmem_load_1[47]), "=f"(_tmem_load_1[48]), "=f"(_tmem_load_1[49]), "=f"(_tmem_load_1[50]), "=f"(_tmem_load_1[51]), "=f"(_tmem_load_1[52]), "=f"(_tmem_load_1[53]), "=f"(_tmem_load_1[54]), "=f"(_tmem_load_1[55]), "=f"(_tmem_load_1[56]), "=f"(_tmem_load_1[57]), "=f"(_tmem_load_1[58]), "=f"(_tmem_load_1[59]), "=f"(_tmem_load_1[60]), "=f"(_tmem_load_1[61]), "=f"(_tmem_load_1[62]), "=f"(_tmem_load_1[63])
+                        : "r"(taddr + (unsigned int)row_base_1 + 64)
+                        : "memory");
+                    asm volatile("tcgen05.wait::ld.sync.aligned;");
+                    asm volatile("barrier.sync 9, %0;" :: "r"(128));
+                    if (elect_sync()) {
+                        mbarrier_arrive(score_empty1_addr);
+                    }
+                    #pragma unroll
+                    for (int kk_1 = 0; kk_1 < 64; kk_1++) {
+                        float score_1 = _tmem_load_1[kk_1] - 0.5f * c_sq[batch_3 * K + kb_1 + kk_1];
+                        if (score_1 > best_1) {
+                            best_1 = score_1;
+                            best_idx_1 = kb_1 + kk_1;
+                        }
+                    }
+                }
+                uint32_t _amf_u_0 = __float_as_uint(best_1);
+                uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+                unsigned int _amf_enc_1 = _amf_u_0 ^ _amf_mask_0;
+                slot1_keys[row_1] = (unsigned long long)_amf_enc_1 << 32 | 4294967295 - (unsigned long long)best_idx_1;
+                asm volatile("barrier.sync 11, %0;" :: "r"(128));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                if (elect_sync()) {
+                    mbarrier_arrive(slot1_keys_ready_addr);
+                }
+            }
+        }
+    // ---- Role: mma1 ----
+    } else if (warp == 12) {
+        { // mma1_main
+            int total_tiles_6 = B * num_n_tiles;
+            int owner_tiles_5 = K_tiles / 2;
+            unsigned int _phase_x_ready1_0 = 0;
+            unsigned int _phase_score_empty1_0 = 1;
+            unsigned int _phase_c_full1_0 = 0;
+            #pragma unroll 1
+            for (unsigned int tile_6 = bid; tile_6 < total_tiles_6; tile_6 += num_bids) {
+                mbarrier_wait(x_ready1_addr, _phase_x_ready1_0);
+                _phase_x_ready1_0 ^= 1;
+                #pragma unroll 1
+                for (int owner_kt_5 = 0; owner_kt_5 < owner_tiles_5; owner_kt_5++) {
+                    mbarrier_wait(score_empty1_addr, _phase_score_empty1_0);
+                    _phase_score_empty1_0 ^= 1;
+                    mbarrier_wait(c_full1_addr, _phase_c_full1_0);
+                    _phase_c_full1_0 ^= 1;
+                    asm volatile("fence.proxy.async;");
+                    asm volatile("tcgen05.fence::after_thread_sync;");
+                    int _mma_a_addr_2 = sx_addr;
+                    int _mma_a_lo_2 = make_warp_uniform((_mma_a_addr_2 >> 4) & 0x3FFF);
+                    int _mma_b_addr_2 = sc1_addr;
+                    int _mma_b_lo_2 = make_warp_uniform((_mma_b_addr_2 >> 4) & 0x3FFF);
+                    mma_ss_step(_mma_a_lo_2, _mma_b_lo_2, tmem_scores1, 135267472, 0, 0xC0004010U, 0xC0004010U);
+                    elect_commit(c_empty1_addr);
+                    #pragma unroll
+                    for (int ft_5 = 1; ft_5 < 7; ft_5++) {
+                        mbarrier_wait(c_full1_addr, _phase_c_full1_0);
+                        _phase_c_full1_0 ^= 1;
+                        asm volatile("fence.proxy.async;");
+                        asm volatile("tcgen05.fence::after_thread_sync;");
+                        int _mma_a_addr_3 = sx_addr + (unsigned int)(ft_5 * 4096);
+                        int _mma_a_lo_3 = make_warp_uniform((_mma_a_addr_3 >> 4) & 0x3FFF);
+                        int _mma_b_addr_3 = sc1_addr;
+                        int _mma_b_lo_3 = make_warp_uniform((_mma_b_addr_3 >> 4) & 0x3FFF);
+                        mma_ss_step(_mma_a_lo_3, _mma_b_lo_3, tmem_scores1, 135267472, 1, 0xC0004010U, 0xC0004010U);
+                        elect_commit(c_empty1_addr);
+                    }
+                    elect_commit(score_full1_addr);
+                }
+                elect_commit(x_empty1_addr);
+            }
+        }
+    }
+
+    // Cleanup
+    __syncthreads(); // barrier before TMEM dealloc
+
+    if (warp == 0) {
+        asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(tmem_addr_storage[0]), "r"(128));
+        asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;");
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
new file mode 100644
index 00000000..c09a29a5
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
@@ -0,0 +1,562 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define SMEM_X_RAW_OFF 1024
+#define SMEM_X_RAW_STAGE_BYTES 14336
+#define SMEM_X_RAW_STRIDE 14336
+#define SMEM_C_DIRECT00_OFF 15360
+#define SMEM_C_DIRECT00_STAGE_BYTES 1792
+#define SMEM_C_DIRECT00_STRIDE 1792
+#define SMEM_C_DIRECT01_OFF 17152
+#define SMEM_C_DIRECT01_STAGE_BYTES 1792
+#define SMEM_C_DIRECT01_STRIDE 1792
+#define SMEM_C_DIRECT10_OFF 18944
+#define SMEM_C_DIRECT10_STAGE_BYTES 1792
+#define SMEM_C_DIRECT10_STRIDE 1792
+#define SMEM_C_DIRECT11_OFF 20736
+#define SMEM_C_DIRECT11_STAGE_BYTES 1792
+#define SMEM_C_DIRECT11_STRIDE 1792
+#define SMEM_SX_OFF 22528
+#define SMEM_SX_STAGE_BYTES 14336
+#define SMEM_SX_STRIDE 14336
+#define SMEM_SS_OFF 36864
+#define SMEM_SS_STAGE_BYTES 4096
+#define SMEM_SS_STRIDE 4096
+#define SMEM_GROUP_KEYS_OFF 40960
+#define SMEM_GROUP_KEYS_STAGE_BYTES 1024
+#define SMEM_GROUP_KEYS_STRIDE 1024
+#define SMEM_LOCAL_KEYS_OFF 41984
+#define SMEM_LOCAL_KEYS_STAGE_BYTES 512
+#define SMEM_LOCAL_KEYS_STRIDE 512
+#define SMEM_CLUSTER_KEYS_OFF 42496
+#define SMEM_CLUSTER_KEYS_STAGE_BYTES 4096
+#define SMEM_CLUSTER_KEYS_STRIDE 4096
+#define SMEM_TOTAL 46592
+#define THREADS 256
+
+#include <math_constants.h>
+
+__device__ __forceinline__ uint32_t elect_sync() {
+    uint32_t pred = 0;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred %%px;\n\t"
+        "elect.sync _|%%px, %1;\n\t"
+        "@%%px mov.s32 %0, 1;\n\t"
+        "}\n"
+        : "+r"(pred)
+        : "r"(0xFFFFFFFF));
+    return pred;
+}
+
+
+__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(mbar_addr), "r"(count));
+}
+
+
+__device__ __forceinline__ uint32_t mbarrier_try_wait(int mbar_addr, int phase) {
+    uint32_t token;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "mbarrier.try_wait.parity.shared::cta.b64"
+        " P1, [%1], %2;\n\t"
+        "selp.u32 %0, 1, 0, P1;\n\t"
+        "}\n"
+        : "=r"(token)
+        : "r"(mbar_addr), "r"(phase) : "memory");
+    return token;
+}
+
+__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
+    uint32_t ticks = 0x989680;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred P1;\n\t"
+        "LAB_WAIT:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64"
+        " P1, [%0], %1, %2;\n\t"
+        "@P1 bra.uni DONE;\n\t"
+        "bra.uni LAB_WAIT;\n\t"
+        "DONE:\n\t"
+        "}\n"
+        :: "r"(mbar_addr), "r"(phase), "r"(ticks) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_token(int mbar_addr, int phase, uint32_t token) {
+    if (token == 0) {
+        mbarrier_wait(mbar_addr, phase);
+    }
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive(int mbar_addr) {
+    asm volatile(
+        "mbarrier.arrive.release.cta.shared::cta.b64 _, [%0];"
+        :: "r"(mbar_addr) : "memory");
+}
+
+
+__device__ __forceinline__ void mbarrier_arrive_expect_tx(int mbar_addr, uint32_t bytes) {
+    asm volatile(
+        "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
+        :: "r"(mbar_addr), "r"(bytes) : "memory");
+}
+
+
+__device__ __forceinline__ uint32_t smem_addr(const void* ptr) {
+    uint32_t addr;
+    asm("{\n\t"
+        ".reg .u64 u64addr;\n\t"
+        "cvta.to.shared.u64 u64addr, %1;\n\t"
+        "cvt.u32.u64 %0, u64addr;\n\t"
+        "}\n" : "=r"(addr) : "l"(ptr));
+    return addr;
+}
+
+
+__device__ __forceinline__ uint32_t mapa_to_rank(uint32_t local_addr, uint32_t rank) {
+    uint32_t remote;
+    asm volatile("mapa.shared::cluster.u32 %0, %1, %2;"
+        : "=r"(remote) : "r"(local_addr), "r"(rank));
+    return remote;
+}
+
+
+__device__ __forceinline__ void mbarrier_init_pred(int mbar_addr, uint32_t count, uint32_t pred) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %2, 0;\n\t"
+        "@p mbarrier.init.shared::cta.b64 [%0], %1;\n\t"
+        "}\n" :: "r"(mbar_addr), "r"(count), "r"(pred));
+}
+
+
+__device__ __forceinline__ void fence_async_shared() {
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+}
+
+
+__device__ __forceinline__ void cp_async_bulk_gmem2smem(
+    unsigned smem_addr, const void* gmem_ptr, unsigned bytes, int mbar_addr) {
+    asm volatile(
+        "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes"
+        " [%0], [%1], %2, [%3];"
+        :: "r"(smem_addr), "l"(gmem_ptr), "r"(bytes), "r"(mbar_addr)
+        : "memory");
+}
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, float* __restrict__ c_sq, int* __restrict__ out, int B, int N, int D, int K, int num_n_tiles)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+    extern __shared__ __align__(1024) char smem_raw[];
+    int smem;
+    smem = (int)(unsigned long long)__cvta_generic_to_shared(smem_raw);
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+    const unsigned int clusters_x = gridDim.x / 8;
+    const unsigned int cluster_id = ((blockIdx.z * gridDim.y + blockIdx.y) * clusters_x) + blockIdx.x / 8;
+    const unsigned int num_clusters = clusters_x * gridDim.y * gridDim.z;
+
+    int cta_rank;
+    asm volatile("mov.b32 %0, %%cluster_ctarank;" : "=r"(cta_rank));
+
+    // Kernel setup ops
+    __nv_bfloat16* x_raw = reinterpret_cast<__nv_bfloat16*>(smem_raw + 1024);
+    const int x_raw_addr = smem + 1024;
+    __nv_bfloat16* c_direct00 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 15360);
+    const int c_direct00_addr = smem + 15360;
+    __nv_bfloat16* c_direct01 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 17152);
+    const int c_direct01_addr = smem + 17152;
+    __nv_bfloat16* c_direct10 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 18944);
+    const int c_direct10_addr = smem + 18944;
+    __nv_bfloat16* c_direct11 = reinterpret_cast<__nv_bfloat16*>(smem_raw + 20736);
+    const int c_direct11_addr = smem + 20736;
+    __nv_bfloat16* sx = reinterpret_cast<__nv_bfloat16*>(smem_raw + 22528);
+    const int sx_addr = smem + 22528;
+    float* ss = reinterpret_cast<float*>(smem_raw + 36864);
+    const int ss_addr = smem + 36864;
+    unsigned long long* group_keys = reinterpret_cast<unsigned long long*>(smem_raw + 40960);
+    const int group_keys_addr = smem + 40960;
+    unsigned long long* local_keys = reinterpret_cast<unsigned long long*>(smem_raw + 41984);
+    const int local_keys_addr = smem + 41984;
+    unsigned long long* cluster_keys = reinterpret_cast<unsigned long long*>(smem_raw + 42496);
+    const int cluster_keys_addr = smem + 42496;
+
+    // Mbarrier init (6 groups, 13 barriers)
+    // Mbarriers at smem_raw[0..104)
+
+    if (warp == 0) {
+        uint32_t leader = elect_sync();
+        // x_ready: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 0, 1, leader);
+        // c_ready00: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 8, 1, leader);
+        // c_ready01: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 16, 1, leader);
+        // c_ready10: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 24, 1, leader);
+        // c_ready11: 1 barriers, init_count=1
+        mbarrier_init_pred(smem + 32, 1, leader);
+        // keys_ready: 8 barriers, init_count=8
+        mbarrier_init_pred(smem + 40, 8, leader);
+        mbarrier_init_pred(smem + 48, 8, leader);
+        mbarrier_init_pred(smem + 56, 8, leader);
+        mbarrier_init_pred(smem + 64, 8, leader);
+        mbarrier_init_pred(smem + 72, 8, leader);
+        mbarrier_init_pred(smem + 80, 8, leader);
+        mbarrier_init_pred(smem + 88, 8, leader);
+        mbarrier_init_pred(smem + 96, 8, leader);
+        asm volatile("fence.mbarrier_init.release.cluster;");
+    }
+
+    __syncthreads();
+
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+
+    const int mbar_base = smem;
+    #define x_ready_addr (mbar_base + 0)
+    #define c_ready00_addr (mbar_base + 8)
+    #define c_ready01_addr (mbar_base + 16)
+    #define c_ready10_addr (mbar_base + 24)
+    #define c_ready11_addr (mbar_base + 32)
+    #define keys_ready_addr (mbar_base + 40)
+
+    // === Task calls (dependency order) ===
+    int total_tiles = B * num_n_tiles;
+    unsigned int _phase_x_ready_0 = 0;
+    unsigned int _phase_c_ready00_0 = 0;
+    unsigned int _phase_c_ready01_0 = 0;
+    unsigned int _phase_c_ready10_0 = 0;
+    unsigned int _phase_c_ready11_0 = 0;
+    unsigned int _phase_keys_ready_0 = 0;
+    #pragma unroll 1
+    for (unsigned int tile = cluster_id; tile < total_tiles; tile += num_clusters) {
+        int batch = tile / (unsigned int)num_n_tiles;
+        int nt = tile % (unsigned int)num_n_tiles;
+        int point_base = batch * N + nt * 64;
+        if (warp == 0) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(x_ready_addr, 14336);
+                cp_async_bulk_gmem2smem(x_raw_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(x) + ((unsigned long long)(point_base * D) * (unsigned long long)2)), 14336, x_ready_addr);
+            }
+        }
+        mbarrier_wait(x_ready_addr, _phase_x_ready_0);
+        _phase_x_ready_0 ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;");
+        #pragma unroll 1
+        for (unsigned int i = tid; i < 7168; i += 256) {
+            int row = i / 112;
+            int col = i % 112;
+            {
+                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
+                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+            }
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        int warp_id_in_role = (warp - 0);
+        int group = warp_id_in_role / 4;
+        int local_warp = warp_id_in_role % 4;
+        int local_row = lane % 16;
+        int row_base = local_warp * 16;
+        float best = -3.4e+38f;
+        int owner_k_tiles = K / 64;
+        int group_k_tiles = owner_k_tiles / 2;
+        int group_tile_begin = cta_rank * owner_k_tiles + group * group_k_tiles;
+        int best_idx = group_tile_begin * 8;
+        int first_kbase = group_tile_begin * 8;
+        if (group == 0) {
+            if (warp == 0) {
+                if (elect_sync()) {
+                    mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                    cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                }
+            }
+        } else if (warp == 4) {
+            if (elect_sync()) {
+                mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + first_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+            }
+        }
+        #pragma unroll 1
+        for (int group_kt = 0; group_kt < group_k_tiles; group_kt++) {
+            int current_stage = group_kt % 2;
+            int kt = group_tile_begin + group_kt;
+            int kbase = kt * 8;
+            bool has_next = group_k_tiles > group_kt + 1;
+            if (has_next) {
+                int next_stage = (group_kt + 1) % 2;
+                int next_kbase = (kt + 1) * 8;
+                if (group == 0) {
+                    if (next_stage == 0) {
+                        if (warp == 0) {
+                            if (elect_sync()) {
+                                mbarrier_arrive_expect_tx(c_ready00_addr, 1792);
+                                cp_async_bulk_gmem2smem(c_direct00_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready00_addr);
+                            }
+                        }
+                    } else if (warp == 0) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready01_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct01_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready01_addr);
+                        }
+                    }
+                } else if (next_stage == 0) {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready10_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct10_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready10_addr);
+                        }
+                    }
+                } else {
+                    if (warp == 4) {
+                        if (elect_sync()) {
+                            mbarrier_arrive_expect_tx(c_ready11_addr, 1792);
+                            cp_async_bulk_gmem2smem(c_direct11_addr, reinterpret_cast<const void*>(reinterpret_cast<const uint8_t*>(centroids) + ((unsigned long long)((batch * K + next_kbase) * D) * (unsigned long long)2)), 1792, c_ready11_addr);
+                        }
+                    }
+                }
+            }
+            if (group == 0) {
+                if (current_stage == 0) {
+                    mbarrier_wait(c_ready00_addr, _phase_c_ready00_0);
+                    _phase_c_ready00_0 ^= 1;
+                } else {
+                    mbarrier_wait(c_ready01_addr, _phase_c_ready01_0);
+                    _phase_c_ready01_0 ^= 1;
+                }
+            } else if (current_stage == 0) {
+                mbarrier_wait(c_ready10_addr, _phase_c_ready10_0);
+                _phase_c_ready10_0 ^= 1;
+            } else {
+                mbarrier_wait(c_ready11_addr, _phase_c_ready11_0);
+                _phase_c_ready11_0 ^= 1;
+            }
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            unsigned int a[4];
+            unsigned int b[2];
+            float acc[4];
+            unsigned int a_addr = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + lane / 16 * 16));
+            unsigned int b_addr = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (lane / 8 & 1) * 8 * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {0f00000000, 0f00000000, 0f00000000, 0f00000000};\n"
+                : "=f"(acc[0]), "=f"(acc[1]), "=f"(acc[2]), "=f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_0 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 32)));
+            unsigned int b_addr_1 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (16 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_0)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_1)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_2 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 64)));
+            unsigned int b_addr_3 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (32 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_2)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_3)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_4 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 96)));
+            unsigned int b_addr_5 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (48 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_4)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_5)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_6 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 128)));
+            unsigned int b_addr_7 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (64 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_6)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_7)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_8 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 160)));
+            unsigned int b_addr_9 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (80 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_8)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_9)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            unsigned int a_addr_10 = (sx_addr + (unsigned int)((row_base + lane % 16) * 224 + (lane / 16 * 16 + 192)));
+            unsigned int b_addr_11 = ((group == 0) ? ((current_stage == 0) ? (c_direct00_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct01_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))) : ((current_stage == 0) ? (c_direct10_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2)) : (c_direct11_addr + (unsigned int)(lane % 8 * 224 + (96 + (lane / 8 & 1) * 8) * 2))));
+            asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];\n"
+                : "=r"(a[0]), "=r"(a[1]), "=r"(a[2]), "=r"(a[3])
+                : "r"(a_addr_10)
+                : "memory");
+            asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];\n"
+                : "=r"(b[0]), "=r"(b[1])
+                : "r"(b_addr_11)
+                : "memory");
+            asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};\n"
+                : "+f"(acc[0]), "+f"(acc[1]), "+f"(acc[2]), "+f"(acc[3])
+                : "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]));
+            #pragma unroll
+            for (int rp = 0; rp < 2; rp++) {
+                #pragma unroll
+                for (int cp = 0; cp < 2; cp++) {
+                    int rr = lane / 4 + rp * 8;
+                    int cc = lane % 4 * 2 + cp;
+                    {
+                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                    }
+                }
+            }
+            __syncwarp();
+            if (lane < 16) {
+                #pragma unroll
+                for (int kk = 0; kk < 8; kk++) {
+                    float score = ss[(group * 64 + row_base + local_row) * 8 + kk] - 0.5f * c_sq[batch * K + kbase + kk];
+                    if (score > best) {
+                        best = score;
+                        best_idx = kbase + kk;
+                    }
+                }
+            }
+            if (group == 0) {
+                asm volatile("barrier.sync 1, %0;" :: "r"(128));
+            } else {
+                asm volatile("barrier.sync 2, %0;" :: "r"(128));
+            }
+        }
+        if (lane < 16) {
+            uint32_t _amf_u_0 = __float_as_uint(best);
+            uint32_t _amf_mask_0 = -int32_t(_amf_u_0 >> 31) | 0x80000000u;
+            unsigned int _amf_enc_0 = _amf_u_0 ^ _amf_mask_0;
+            unsigned long long shift64 = 32;
+            unsigned long long mask64 = 4294967295;
+            group_keys[group * 64 + row_base + local_row] = (unsigned long long)_amf_enc_0 << shift64 | mask64 - (unsigned long long)best_idx;
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (group == 0 && lane < 16) {
+            unsigned long long first_key = group_keys[row_base + local_row];
+            unsigned long long second_key = group_keys[64 + row_base + local_row];
+            local_keys[row_base + local_row] = ((second_key > first_key) ? second_key : first_key);
+        }
+        asm volatile("barrier.sync 3, %0;" :: "r"(256));
+        if (warp == 0) {
+            if (elect_sync()) {
+                uint32_t _mapa_0;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_0) : "r"(cluster_keys_addr + (unsigned int)(cta_rank * 512)), "r"(0));
+                asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+                uint32_t _mapa_1;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_1) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1;"
+                    :: "r"(_mapa_1), "r"((uint32_t)(512)) : "memory");
+                uint32_t _mapa_2;
+                asm volatile(
+                    "mapa.shared::cluster.u32 %0, %1, %2;"
+                    : "=r"(_mapa_2) : "r"(keys_ready_addr), "r"(0));
+                asm volatile(
+                    "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes"
+                    " [%0], [%1], %2, [%3];"
+                    :: "r"(_mapa_0), "r"(local_keys_addr), "r"((uint32_t)(512)), "r"(_mapa_2)
+                    : "memory");
+            }
+        }
+        if (cta_rank == 0) {
+            mbarrier_wait(keys_ready_addr, _phase_keys_ready_0);
+            _phase_keys_ready_0 ^= 1;
+            asm volatile("tcgen05.fence::after_thread_sync;");
+            int row_1 = tid / 2;
+            int lane_pair = tid % 2;
+            if (row_1 < 64) {
+                unsigned long long best_key = 0;
+                #pragma unroll
+                for (int peer = lane_pair; peer < 8; peer += 2) {
+                    unsigned long long key = cluster_keys[peer * 64 + row_1];
+                    if (key > best_key) {
+                        best_key = key;
+                    }
+                }
+                unsigned long long _shfl_xor_0 = __shfl_xor_sync(0xFFFFFFFF, best_key, 1);
+                unsigned long long peer_key = _shfl_xor_0;
+                if (peer_key > best_key) {
+                    best_key = peer_key;
+                }
+                if (lane_pair == 0) {
+                    unsigned long long mask64_1 = 4294967295;
+                    int idx = (int)(mask64_1 - (best_key & mask64_1));
+                    *((int*)(out + (batch * N + nt * 64 + row_1))) = idx;
+                }
+            }
+        }
+    }
+
+    // Cleanup
+    asm volatile("barrier.cluster.arrive.release.aligned;");
+    asm volatile("barrier.cluster.wait.acquire.aligned;");
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0357.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0357.cu
new file mode 100644
index 00000000..ea986bdf
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0357.cu
@@ -0,0 +1,138 @@
+typedef unsigned char      uint8_t;
+typedef unsigned short     uint16_t;
+typedef unsigned int       uint32_t;
+typedef unsigned long long uint64_t;
+typedef signed int         int32_t;
+typedef short int          int16_t;
+
+#include <cuda_bf16.h>
+
+__device__ __forceinline__ int make_warp_uniform(int x) {
+    int result;
+    asm volatile("shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;"
+                 : "=r"(result) : "r"(x));
+    return result;
+}
+
+#define LOOM_INF CUDART_INF_F
+#define NUM_MAIN_STAGES 1
+#define THREADS 256
+
+#include <math_constants.h>
+
+extern "C" {
+
+__global__ __launch_bounds__(256) void
+kernel_flash_kmeans_assign_cleanroom_tcgen05_d160_pack_padded_b23d_v1(__nv_bfloat16* __restrict__ x, __nv_bfloat16* __restrict__ centroids, __nv_bfloat16* __restrict__ x_pad, __nv_bfloat16* __restrict__ c_pad, int B, int N, int D, int K, int total_x_pad, int total_c_pad)
+{
+    const int tid = threadIdx.x;
+    const int warp = make_warp_uniform(tid / 32);
+    const int lane = tid % 32;
+
+
+    const int bid = blockIdx.x;
+    const int num_bids = gridDim.x;
+
+    // === Task calls (dependency order) ===
+    int grid_stride = num_bids * 256;
+    int start = bid * 256 + tid;
+    int total_x_vecs = total_x_pad / 8;
+    int total_c_vecs = total_c_pad / 8;
+    #pragma unroll 1
+    for (unsigned int vec_idx = start; vec_idx < total_x_vecs; vec_idx += grid_stride) {
+        int d_pad = vec_idx % 24 * 8;
+        int row = vec_idx / 24;
+        int dst_base = vec_idx * 8;
+        if (d_pad < D) {
+            float _vec_load_0[8];
+            {
+                const uint4* _vptr_0 = reinterpret_cast<const uint4*>(x + (row * D + d_pad) + 0);
+                uint4 _vld_0[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_0[_blk] = _vptr_0[_blk];
+                    __nv_bfloat16* _velems_0 = reinterpret_cast<__nv_bfloat16*>(&_vld_0[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_0[0 + _blk * 8 + _j] = __bfloat162float(_velems_0[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_0[0 + 0], _vec_load_0[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_0[0 + 2], _vec_load_0[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_0[0 + 4], _vec_load_0[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_0[0 + 6], _vec_load_0[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros[8];
+            zeros[0] = 0.0f;
+            zeros[1] = 0.0f;
+            zeros[2] = 0.0f;
+            zeros[3] = 0.0f;
+            zeros[4] = 0.0f;
+            zeros[5] = 0.0f;
+            zeros[6] = 0.0f;
+            zeros[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros[0 + 0], zeros[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros[0 + 2], zeros[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros[0 + 4], zeros[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros[0 + 6], zeros[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(x_pad + dst_base))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+    #pragma unroll 1
+    for (unsigned int vec_idx_1 = start; vec_idx_1 < total_c_vecs; vec_idx_1 += grid_stride) {
+        int d_pad_1 = vec_idx_1 % 24 * 8;
+        int row_1 = vec_idx_1 / 24;
+        int dst_base_1 = vec_idx_1 * 8;
+        if (d_pad_1 < D) {
+            float _vec_load_1[8];
+            {
+                const uint4* _vptr_1 = reinterpret_cast<const uint4*>(centroids + (row_1 * D + d_pad_1) + 0);
+                uint4 _vld_1[1];
+                #pragma unroll
+                for (int _blk = 0; _blk < 1; _blk++) {
+                    _vld_1[_blk] = _vptr_1[_blk];
+                    __nv_bfloat16* _velems_1 = reinterpret_cast<__nv_bfloat16*>(&_vld_1[_blk]);
+                    #pragma unroll
+                    for (int _j = 0; _j < 8; _j++)
+                        _vec_load_1[0 + _blk * 8 + _j] = __bfloat162float(_velems_1[_j]);
+                }
+            }
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(_vec_load_1[0 + 0], _vec_load_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(_vec_load_1[0 + 2], _vec_load_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(_vec_load_1[0 + 4], _vec_load_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(_vec_load_1[0 + 6], _vec_load_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        } else {
+            float zeros_1[8];
+            zeros_1[0] = 0.0f;
+            zeros_1[1] = 0.0f;
+            zeros_1[2] = 0.0f;
+            zeros_1[3] = 0.0f;
+            zeros_1[4] = 0.0f;
+            zeros_1[5] = 0.0f;
+            zeros_1[6] = 0.0f;
+            zeros_1[7] = 0.0f;
+            {
+                __nv_bfloat162 _pk[4];
+                _pk[0] = __floats2bfloat162_rn(zeros_1[0 + 0], zeros_1[0 + 1]);
+                _pk[1] = __floats2bfloat162_rn(zeros_1[0 + 2], zeros_1[0 + 3]);
+                _pk[2] = __floats2bfloat162_rn(zeros_1[0 + 4], zeros_1[0 + 5]);
+                _pk[3] = __floats2bfloat162_rn(zeros_1[0 + 6], zeros_1[0 + 7]);
+                *reinterpret_cast<uint4*>(&((__nv_bfloat16*)(c_pad + dst_base_1))[0]) = *reinterpret_cast<uint4*>(&_pk[0]);
+            }
+        }
+    }
+}
+
+} // extern "C"
+
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
new file mode 100644
index 00000000..f93bb51c
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
@@ -0,0 +1,1012 @@
+from __future__ import annotations
+
+import math
+from collections import OrderedDict
+from contextlib import contextmanager
+from dataclasses import dataclass, field
+from threading import Condition, Event, RLock
+from typing import Any
+
+from ._dispatch import flash_kmeans_assign_dispatcher as _dispatcher
+from ._runtime import detect_gpu_arch, launch_context, runtime_activity_snapshot
+
+SEMANTIC_ENTRYPOINT = "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval"
+
+
+@dataclass(frozen=True)
+class PreparedFlashKMeansAssign:
+    """Exact tensors, workspace, output, and direct launch plan for KMeans."""
+
+    inputs: dict[str, Any]
+    launch_plan: Any
+    stream: Any = None
+    timeout_ms: float | None = None
+
+    @property
+    def out(self) -> Any:
+        return self.inputs["out"]
+
+    @property
+    def selected_route(self) -> str:
+        return self.launch_plan.selected_route
+
+
+@dataclass
+class _RuntimeSlot:
+    inputs: dict[str, Any]
+    launch_plan: Any
+    norm_plan: Any = None
+    internal_x_sq: bool = False
+    internal_c_sq: bool = False
+    norm_compute_fields: tuple[str, ...] = ()
+    record_each_call_fields: tuple[str, ...] = ("x", "centroids")
+    norm_rebind_program: tuple[tuple[str, Any], ...] = ()
+    lock: RLock = field(default_factory=RLock, repr=False)
+
+
+@dataclass
+class _PendingPreparation:
+    event: Event = field(default_factory=Event, repr=False)
+    error: BaseException | None = field(default=None, repr=False)
+
+
+def _normalize_device_index(torch: Any, device: Any) -> int:
+    if device is None:
+        return int(torch.cuda.current_device())
+    if isinstance(device, bool):
+        raise TypeError("device must identify a CUDA device")
+    if isinstance(device, int):
+        if device < 0:
+            raise ValueError("CUDA device index must be non-negative")
+        return int(device)
+    device_type = getattr(device, "type", None)
+    device_index = getattr(device, "index", None)
+    if device_type is None:
+        device_ctor = getattr(torch, "device", None)
+        if device_ctor is None:
+            raise TypeError("device must identify a CUDA device")
+        normalized = device_ctor(device)
+        device_type = getattr(normalized, "type", None)
+        device_index = getattr(normalized, "index", None)
+    if device_type != "cuda":
+        raise ValueError(f"Flash-KMeans runtime requires a CUDA device, got {device_type!r}")
+    resolved_index = int(torch.cuda.current_device() if device_index is None else device_index)
+    if resolved_index < 0:
+        raise ValueError("CUDA device index must be non-negative")
+    return resolved_index
+
+
+def _validate_timeout(timeout_ms: float | None) -> float | None:
+    if timeout_ms is None:
+        return None
+    if isinstance(timeout_ms, bool) or not isinstance(timeout_ms, int | float):
+        raise TypeError("timeout_ms must be a positive finite number or None")
+    value = float(timeout_ms)
+    if not math.isfinite(value) or value <= 0:
+        raise ValueError("timeout_ms must be a positive finite number")
+    return value
+
+
+def _resolve_stream(torch: Any, device_index: int, stream: Any) -> Any:
+    resolved_stream = torch.cuda.current_stream(device_index) if stream is None else stream
+    stream_device = getattr(resolved_stream, "device", None)
+    stream_device_index = getattr(stream_device, "index", stream_device)
+    if stream_device_index is not None and int(stream_device_index) != int(device_index):
+        raise ValueError(
+            f"Flash-KMeans stream device {stream_device_index} does not match input device {device_index}"
+        )
+    return resolved_stream
+
+
+def _same_cuda_stream(left: Any, right: Any) -> bool:
+    return left is right or int(left.cuda_stream) == int(right.cuda_stream)
+
+
+@contextmanager
+def _device_stream_context(
+    torch: Any,
+    device_index: int,
+    stream: Any,
+    *,
+    context_is_active: bool,
+):
+    """Resolve one stream and enter it only when the caller has not already done so."""
+
+    if context_is_active:
+        if stream is None:
+            raise RuntimeError("an active Flash-KMeans CUDA context requires an explicit stream")
+        yield stream
+        return
+    with torch.cuda.device(device_index):
+        resolved_stream = _resolve_stream(torch, device_index, stream)
+        with torch.cuda.stream(resolved_stream):
+            yield resolved_stream
+
+
+def _pointer_alias_topology(*tensors: Any) -> tuple[int, ...]:
+    """Canonical pointer-equivalence classes independent of concrete addresses."""
+
+    classes: dict[int, int] = {}
+    topology: list[int] = []
+    for tensor in tensors:
+        if tensor is None:
+            topology.append(-1)
+            continue
+        pointer = int(tensor.data_ptr())
+        if pointer not in classes:
+            classes[pointer] = len(classes)
+        topology.append(classes[pointer])
+    return tuple(topology)
+
+
+class FlashKMeansAssignRuntime:
+    """Long-lived KMeans assignment runtime with per-shape, per-stream plans.
+
+    ``compute`` accepts new tensors and new shapes.  The first call for one
+    shape/stream resolves and captures the exact route; later calls only
+    refresh data-derived norms, rebind caller tensor pointers, and enqueue the
+    already captured launch sequence.  Workspace is never shared across CUDA
+    streams.
+    """
+
+    def __init__(
+        self,
+        *,
+        device: Any = None,
+        arch: str | None = None,
+        timeout_ms: float | None = None,
+        max_cached_shapes: int | None = None,
+        compile: str = "lazy",
+    ) -> None:
+        import torch
+
+        if compile != "lazy":
+            raise ValueError("compile must be 'lazy'; use warmup() to eagerly prepare known shapes")
+        if max_cached_shapes is not None:
+            if isinstance(max_cached_shapes, bool) or not isinstance(max_cached_shapes, int):
+                raise TypeError("max_cached_shapes must be a positive integer or None")
+            if max_cached_shapes <= 0:
+                raise ValueError("max_cached_shapes must be positive")
+        self.device_index = _normalize_device_index(torch, device)
+        with torch.cuda.device(self.device_index):
+            detected_arch = str(detect_gpu_arch())
+        self.arch = detected_arch if arch is None else str(arch)
+        if self.arch != detected_arch:
+            raise ValueError(
+                f"Flash-KMeans runtime arch must match its device: requested {self.arch}, detected {detected_arch}"
+            )
+        self.timeout_ms = _validate_timeout(timeout_ms)
+        self.max_cached_shapes = max_cached_shapes
+        self._torch = torch
+        self._slots: OrderedDict[tuple[Any, ...], _RuntimeSlot] = OrderedDict()
+        self._preparing: dict[tuple[Any, ...], _PendingPreparation] = {}
+        self._cache_lock = RLock()
+        self._lifecycle = Condition(RLock())
+        self._active_computes = 0
+        self._clearing = False
+        self._hits = 0
+        self._misses = 0
+
+    @contextmanager
+    def _compute_lifecycle(self):
+        """Admit concurrent compute calls while making clear() an exclusive barrier."""
+
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            self._active_computes += 1
+        try:
+            yield
+        finally:
+            with self._lifecycle:
+                self._active_computes -= 1
+                if self._active_computes == 0:
+                    self._lifecycle.notify_all()
+
+    def cache_info(self) -> dict[str, int | None]:
+        with self._cache_lock:
+            return {
+                "size": len(self._slots),
+                "hits": self._hits,
+                "misses": self._misses,
+                "max_cached_shapes": self.max_cached_shapes,
+            }
+
+    def _cache_key(
+        self,
+        inputs: dict[str, Any],
+        stream_handle: int,
+        *,
+        caller_supplied_out: bool = True,
+    ) -> tuple[Any, ...]:
+        alias_topology: tuple[int, ...]
+        if not caller_supplied_out and inputs["x_sq"] is None and inputs["c_sq"] is None:
+            x_pointer = int(inputs["x"].data_ptr())
+            centroids_pointer = int(inputs["centroids"].data_ptr())
+            if x_pointer and centroids_pointer:
+                # The internally allocated output cannot alias either live
+                # input. Preserve the canonical class numbering for both
+                # possible x/centroid relationships without reading it.
+                alias_topology = (
+                    0,
+                    0 if x_pointer == centroids_pointer else 1,
+                    -1,
+                    -1,
+                    1 if x_pointer == centroids_pointer else 2,
+                )
+            else:
+                alias_topology = _pointer_alias_topology(
+                    inputs["x"],
+                    inputs["centroids"],
+                    inputs["x_sq"],
+                    inputs["c_sq"],
+                    inputs["out"],
+                )
+        else:
+            alias_topology = _pointer_alias_topology(
+                inputs["x"],
+                inputs["centroids"],
+                inputs["x_sq"],
+                inputs["c_sq"],
+                inputs["out"],
+            )
+        return (
+            self.device_index,
+            self.arch,
+            int(inputs["B"]),
+            int(inputs["N"]),
+            int(inputs["D"]),
+            int(inputs["K"]),
+            str(inputs["dtype"]),
+            alias_topology,
+            int(stream_handle),
+        )
+
+    def clear(self, *, synchronize: bool = True) -> None:
+        """Exclusively release slots after admitted host calls finish.
+
+        The default waits for device completion. With ``synchronize=False``,
+        recorded-stream ownership keeps tensor storage allocator-safe, but the
+        caller remains responsible for observing asynchronous completion.
+        """
+        import torch
+
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            try:
+                self._clearing = True
+                while self._active_computes:
+                    self._lifecycle.wait()
+                if synchronize:
+                    with torch.cuda.device(self.device_index):
+                        torch.cuda.synchronize()
+                with self._cache_lock:
+                    self._slots.clear()
+                    self._hits = 0
+                    self._misses = 0
+            finally:
+                self._clearing = False
+                self._lifecycle.notify_all()
+
+    def warmup(self, *args: Any, synchronize: bool = True, **kwargs: Any):
+        result = self.compute(*args, **kwargs)
+        if synchronize:
+            import torch
+
+            with torch.cuda.device(self.device_index):
+                torch.cuda.synchronize()
+        return result
+
+    def compute(
+        self,
+        x: Any,
+        centroids: Any,
+        *,
+        out: Any | None = None,
+        x_sq: Any | None = None,
+        c_sq: Any | None = None,
+        stream: Any = None,
+        timeout_ms: float | None = None,
+        return_info: bool = False,
+    ):
+        with self._compute_lifecycle():
+            torch = self._torch
+            if int(torch.cuda.current_device()) == self.device_index:
+                if stream is None:
+                    resolved_stream = torch.cuda.current_stream(self.device_index)
+                    return self._compute(
+                        x,
+                        centroids,
+                        out=out,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        stream=resolved_stream,
+                        timeout_ms=timeout_ms,
+                        return_info=return_info,
+                    )
+                resolved_stream = _resolve_stream(torch, self.device_index, stream)
+                current_stream = torch.cuda.current_stream(self.device_index)
+                if _same_cuda_stream(resolved_stream, current_stream):
+                    return self._compute(
+                        x,
+                        centroids,
+                        out=out,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        stream=resolved_stream,
+                        timeout_ms=timeout_ms,
+                        return_info=return_info,
+                    )
+                with torch.cuda.stream(resolved_stream):
+                    return self._compute(
+                        x,
+                        centroids,
+                        out=out,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        stream=resolved_stream,
+                        timeout_ms=timeout_ms,
+                        return_info=return_info,
+                    )
+            with torch.cuda.device(self.device_index):
+                resolved_stream = _resolve_stream(torch, self.device_index, stream)
+                current_stream = torch.cuda.current_stream(self.device_index)
+                if _same_cuda_stream(resolved_stream, current_stream):
+                    return self._compute(
+                        x,
+                        centroids,
+                        out=out,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        stream=resolved_stream,
+                        timeout_ms=timeout_ms,
+                        return_info=return_info,
+                    )
+                with torch.cuda.stream(resolved_stream):
+                    return self._compute(
+                        x,
+                        centroids,
+                        out=out,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        stream=resolved_stream,
+                        timeout_ms=timeout_ms,
+                        return_info=return_info,
+                    )
+
+    def _compute(
+        self,
+        x: Any,
+        centroids: Any,
+        *,
+        out: Any | None,
+        x_sq: Any | None,
+        c_sq: Any | None,
+        stream: Any,
+        timeout_ms: float | None,
+        return_info: bool,
+    ):
+        caller_supplied_out = out is not None
+        effective_timeout_ms = self.timeout_ms if timeout_ms is None else _validate_timeout(timeout_ms)
+        inputs, resolved_stream, resolved_arch = _prepare_inputs(
+            x,
+            centroids,
+            out=out,
+            x_sq=x_sq,
+            c_sq=c_sq,
+            device_index=self.device_index,
+            arch=self.arch,
+            stream=stream,
+            arch_is_validated=True,
+            timeout_ms=effective_timeout_ms,
+            defer_missing_norms=True,
+            _context_is_active=True,
+            _torch=self._torch,
+        )
+        stream_handle = int(resolved_stream.cuda_stream)
+        key = self._cache_key(
+            inputs,
+            stream_handle,
+            caller_supplied_out=caller_supplied_out,
+        )
+        activity_before = runtime_activity_snapshot() if return_info else None
+        slot, cache_hit, owns_slot_lock = self._get_or_create_slot(
+            key,
+            inputs,
+            resolved_stream=resolved_stream,
+            resolved_arch=resolved_arch,
+            _context_is_active=True,
+        )
+        activity_after = runtime_activity_snapshot() if return_info else None
+        if not owns_slot_lock:
+            slot.lock.acquire()
+        norm_mode = (
+            "fused_bf16_pair_row_norm:" + ",".join(slot.norm_compute_fields)
+            if slot.norm_compute_fields
+            else "route_elided_internal_norms"
+            if slot.internal_x_sq or slot.internal_c_sq
+            else "explicit_precomputed"
+        )
+        try:
+            if cache_hit:
+                if slot.launch_plan.stream_handle != stream_handle:
+                    raise RuntimeError("cached Flash-KMeans slot changed its prepared stream")
+                for name in ("x", "centroids", "out"):
+                    slot.inputs[name] = inputs[name]
+                if not slot.internal_x_sq:
+                    slot.inputs["x_sq"] = inputs["x_sq"]
+                if not slot.internal_c_sq:
+                    slot.inputs["c_sq"] = inputs["c_sq"]
+                slot.inputs["_norm_mode"] = norm_mode
+            # Protect every new caller-owned tensor before non-retaining
+            # rebind. Slot-owned norms and a default output are allocated
+            # on this permanently bound stream, so they do not need
+            # repeated allocator ownership calls.
+            _record_stream_inputs(
+                resolved_stream,
+                slot.inputs,
+                slot.record_each_call_fields,
+            )
+            if caller_supplied_out:
+                _record_stream(resolved_stream, slot.inputs["out"])
+            if cache_hit:
+                # Slot lookup already proved the public alias topology and
+                # stream identity. Rebind only the scrubbed pointer carriers
+                # needed by this fixed-stream launch sequence.
+                slot.launch_plan.direct_launcher._rebind_stream_bound_scrubbed_inputs(
+                    slot.inputs,
+                    stream=resolved_stream,
+                )
+            if slot.norm_plan is not None:
+                try:
+                    if cache_hit:
+                        _rebind_stream_bound_norm_inputs(slot)
+                    else:
+                        slot.norm_plan.rebind(
+                            slot.inputs["x"],
+                            slot.inputs["centroids"],
+                            slot.inputs["x_sq"],
+                            slot.inputs["c_sq"],
+                            stream=resolved_stream,
+                        )
+                    slot.norm_plan.launch(
+                        stream=resolved_stream,
+                        timeout_ms=effective_timeout_ms,
+                    )
+                finally:
+                    if not cache_hit:
+                        _prepare_stream_bound_norm_rebind(slot)
+            slot.launch_plan._launch_stream_bound_recorded(
+                timeout_ms=effective_timeout_ms,
+            )
+            output = slot.inputs["out"]
+        finally:
+            try:
+                if not cache_hit:
+                    slot.launch_plan.direct_launcher.release_bound_inputs()
+            finally:
+                for name in ("x", "centroids", "out"):
+                    slot.inputs[name] = None
+                if not slot.internal_x_sq:
+                    slot.inputs["x_sq"] = None
+                if not slot.internal_c_sq:
+                    slot.inputs["c_sq"] = None
+                slot.lock.release()
+
+        if not return_info:
+            return output
+        cold_activity = {
+            "source_read_occurred": bool(activity_after["source_reads"] > activity_before["source_reads"]),
+            "nvrtc_compile_occurred": bool(
+                activity_after["nvrtc_compiles"] > activity_before["nvrtc_compiles"]
+            ),
+            "module_load_occurred": bool(activity_after["module_loads"] > activity_before["module_loads"]),
+            "scratch_allocation_occurred": not cache_hit,
+        }
+        return output, {
+            "semantic_entrypoint": SEMANTIC_ENTRYPOINT,
+            "selected_route": slot.launch_plan.selected_route,
+            "launch_entrypoint": slot.launch_plan.launch_entrypoint,
+            "exact_launch_plan": True,
+            "runtime_cache_hit": cache_hit,
+            "assignment_launch_count": slot.launch_plan.launch_count,
+            "norm_launch_count": int(slot.norm_plan is not None),
+            "norm_compute_fields": list(slot.norm_compute_fields),
+            "runtime_launch_count": slot.launch_plan.launch_count + int(slot.norm_plan is not None),
+            "norm_mode": norm_mode,
+            "arch": slot.launch_plan.arch,
+            "device_index": slot.launch_plan.device_index,
+            "stream_handle": slot.launch_plan.stream_handle,
+            "cold_first_call_activity": cold_activity,
+        }
+
+    def _get_or_create_slot(
+        self,
+        key: tuple[Any, ...],
+        inputs: dict[str, Any],
+        *,
+        resolved_stream: Any,
+        resolved_arch: str,
+        _context_is_active: bool = False,
+    ) -> tuple[_RuntimeSlot, bool, bool]:
+        """Return a slot; a newly published slot is returned with its lock held."""
+
+        import torch
+
+        while True:
+            with self._cache_lock:
+                slot = self._slots.get(key)
+                if slot is not None:
+                    self._hits += 1
+                    return slot, True, False
+                pending = self._preparing.get(key)
+                if pending is None:
+                    if (
+                        self.max_cached_shapes is not None
+                        and len(self._slots) + len(self._preparing) >= self.max_cached_shapes
+                    ):
+                        raise RuntimeError(
+                            "FlashKMeansAssignRuntime cache is full; call clear() only after in-flight work completes"
+                        )
+                    pending = _PendingPreparation()
+                    self._preparing[key] = pending
+                    break
+            pending.event.wait()
+            if pending.error is not None:
+                raise RuntimeError("KMeans slot preparation failed in another thread") from pending.error
+
+        slot: _RuntimeSlot | None = None
+        try:
+            with _device_stream_context(
+                torch,
+                self.device_index,
+                resolved_stream,
+                context_is_active=_context_is_active,
+            ):
+                internal_x_sq = inputs["x_sq"] is None
+                internal_c_sq = inputs["c_sq"] is None
+                if internal_x_sq:
+                    inputs["x_sq"] = torch.empty(
+                        (int(inputs["B"]), int(inputs["N"])),
+                        dtype=torch.float32,
+                        device=inputs["x"].device,
+                    )
+                if internal_c_sq:
+                    inputs["c_sq"] = torch.empty(
+                        (int(inputs["B"]), int(inputs["K"])),
+                        dtype=torch.float32,
+                        device=inputs["x"].device,
+                    )
+                launch_plan = _dispatcher.prepare_launch_plan(
+                    inputs,
+                    arch=resolved_arch,
+                    stream=resolved_stream,
+                    timeout_ms=None,
+                )
+                # This slot is permanently bound to resolved_stream. Record
+                # route-private scratch and descriptor storage once while the
+                # plan owns its original caller tensors; subsequent computes
+                # separately record every new public tensor before rebinding.
+                launch_plan.direct_launcher.record_stream(resolved_stream)
+                bound_input_keys = set(launch_plan.direct_launcher.bound_input_keys)
+                compute_x_sq = internal_x_sq and "x_sq" in bound_input_keys
+                compute_c_sq = internal_c_sq and "c_sq" in bound_input_keys
+                norm_plan = None
+                if compute_x_sq or compute_c_sq:
+                    from ._row_norm import prepare_bf16_pair_row_norm
+
+                    norm_plan = prepare_bf16_pair_row_norm(
+                        inputs["x"],
+                        inputs["centroids"],
+                        inputs["x_sq"],
+                        inputs["c_sq"],
+                        compute_x=compute_x_sq,
+                        compute_c=compute_c_sq,
+                        arch=resolved_arch,
+                        stream=resolved_stream,
+                    )
+                norm_compute_fields = tuple(
+                    name for name, enabled in (("x_sq", compute_x_sq), ("c_sq", compute_c_sq)) if enabled
+                )
+            slot = _RuntimeSlot(
+                inputs=inputs,
+                launch_plan=launch_plan,
+                norm_plan=norm_plan,
+                internal_x_sq=internal_x_sq,
+                internal_c_sq=internal_c_sq,
+                norm_compute_fields=norm_compute_fields,
+                record_each_call_fields=(
+                    "x",
+                    "centroids",
+                    *(("x_sq",) if not internal_x_sq else ()),
+                    *(("c_sq",) if not internal_c_sq else ()),
+                ),
+            )
+            slot.lock.acquire()
+        except BaseException as error:
+            if slot is not None:
+                try:
+                    slot.lock.release()
+                except RuntimeError:
+                    pass
+            with self._cache_lock:
+                self._preparing.pop(key, None)
+                pending.error = error
+                pending.event.set()
+            raise
+        publication_committed = False
+        try:
+            with self._cache_lock:
+                old_misses = self._misses
+                try:
+                    self._slots[key] = slot
+                    self._misses = old_misses + 1
+                    self._preparing.pop(key, None)
+                    pending.event.set()
+                    publication_committed = True
+                except BaseException as error:
+                    if self._slots.get(key) is slot:
+                        self._slots.pop(key, None)
+                    self._misses = old_misses
+                    if self._preparing.get(key) is pending:
+                        self._preparing.pop(key, None)
+                    pending.error = error
+                    pending.event.set()
+                    raise
+        except BaseException as error:
+            if not publication_committed:
+                with self._cache_lock:
+                    if self._slots.get(key) is slot:
+                        self._slots.pop(key, None)
+                        self._misses -= 1
+                    if self._preparing.get(key) is pending:
+                        self._preparing.pop(key, None)
+                    if pending.error is None:
+                        pending.error = error
+                    pending.event.set()
+            slot.lock.release()
+            raise
+        return slot, False, True
+
+
+def init(
+    *,
+    device: Any = None,
+    arch: str | None = None,
+    timeout_ms: float | None = None,
+    max_cached_shapes: int | None = None,
+    compile: str = "lazy",
+) -> FlashKMeansAssignRuntime:
+    """Create one reusable runtime; shape-specific plans remain lazy."""
+
+    return FlashKMeansAssignRuntime(
+        device=device,
+        arch=arch,
+        timeout_ms=timeout_ms,
+        max_cached_shapes=max_cached_shapes,
+        compile=compile,
+    )
+
+
+def _require_aux_tensor(
+    tensor: Any,
+    *,
+    name: str,
+    shape: tuple[int, ...],
+    dtype: Any,
+    device: Any,
+) -> None:
+    if tuple(tensor.shape) != shape or tensor.dtype is not dtype:
+        raise ValueError(f"{name} must have dtype {dtype} and shape {shape}")
+    if tensor.device != device or not tensor.is_contiguous():
+        raise ValueError(f"{name} must be contiguous and on {device}")
+
+
+def _record_stream(stream: Any, *tensors: Any) -> None:
+    seen: set[int] = set()
+    for tensor in tensors:
+        identity = id(tensor)
+        if identity in seen:
+            continue
+        seen.add(identity)
+        record_stream = getattr(tensor, "record_stream", None)
+        if callable(record_stream):
+            record_stream(stream)
+
+
+def _record_stream_inputs(
+    stream: Any,
+    inputs: dict[str, Any],
+    fields: tuple[str, ...],
+) -> None:
+    seen: set[int] = set()
+    for name in fields:
+        tensor = inputs[name]
+        identity = id(tensor)
+        if identity in seen:
+            continue
+        seen.add(identity)
+        record_stream = getattr(tensor, "record_stream", None)
+        if callable(record_stream):
+            record_stream(stream)
+
+
+def _rebind_stream_bound_norm_inputs(slot: _RuntimeSlot) -> None:
+    """Update one validated slot's prepared norm pointer carriers in place."""
+
+    if not slot.norm_rebind_program:
+        raise RuntimeError("cached KMeans norm launch has no fixed-stream rebind program")
+    pointer_updates = tuple(
+        (carrier, int(slot.inputs[name].data_ptr()))
+        for name, carrier in slot.norm_rebind_program
+    )
+    for carrier, pointer in pointer_updates:
+        carrier.value = pointer
+
+
+def _prepare_stream_bound_norm_rebind(slot: _RuntimeSlot) -> None:
+    """Scrub cold norm callers and retain only the slot's dynamic carriers."""
+
+    all_bindings = ((0, "x"), (1, "centroids"), (2, "x_sq"), (3, "c_sq"))
+    full_program = slot.norm_plan.launch_plan._scrub_stream_bound_pointer_keepalives(
+        all_bindings
+    )
+    dynamic_names = {
+        "x",
+        "centroids",
+        *(("x_sq",) if not slot.internal_x_sq else ()),
+        *(("c_sq",) if not slot.internal_c_sq else ()),
+    }
+    slot.norm_rebind_program = tuple(
+        (name, carrier) for name, carrier in full_program if name in dynamic_names
+    )
+
+
+def _prepare_inputs(
+    x: Any,
+    centroids: Any,
+    *,
+    out: Any | None,
+    x_sq: Any | None,
+    c_sq: Any | None,
+    device_index: int | None,
+    arch: str | None,
+    stream: Any,
+    arch_is_validated: bool = False,
+    timeout_ms: float | None = None,
+    defer_missing_norms: bool = False,
+    _context_is_active: bool = False,
+    _torch: Any = None,
+) -> tuple[dict[str, Any], Any, str]:
+    if _torch is None:
+        import torch
+    else:
+        torch = _torch
+
+    if not all(isinstance(item, torch.Tensor) and item.is_cuda for item in (x, centroids)):
+        raise TypeError("x and centroids must be CUDA torch.Tensor objects")
+    if x.dtype is not torch.bfloat16 or centroids.dtype is not torch.bfloat16:
+        raise TypeError("x and centroids dtype must be bfloat16")
+    if x.ndim != 3 or centroids.ndim != 3 or not x.is_contiguous() or not centroids.is_contiguous():
+        raise ValueError("x and centroids must be contiguous [B, rows, D] tensors")
+    bsz, n_points, dim = map(int, x.shape)
+    c_bsz, n_clusters, c_dim = map(int, centroids.shape)
+    if (bsz, dim) != (c_bsz, c_dim) or x.device != centroids.device:
+        raise ValueError("x and centroids batch/feature dimensions and device must match")
+    input_device_index = x.device.index
+    if input_device_index is None:
+        input_device_index = torch.cuda.current_device()
+    input_device_index = int(input_device_index)
+    if device_index is not None and input_device_index != int(device_index):
+        raise ValueError(
+            f"Flash-KMeans runtime targets CUDA device {device_index}, got input device {input_device_index}"
+        )
+    with _device_stream_context(
+        torch,
+        input_device_index,
+        stream,
+        context_is_active=_context_is_active,
+    ) as resolved_stream:
+        if arch_is_validated:
+            if arch is None:
+                raise RuntimeError("validated Flash-KMeans runtime must provide its active arch")
+            resolved_arch = str(arch)
+        else:
+            detected_arch = str(detect_gpu_arch())
+            resolved_arch = detected_arch if arch is None else str(arch)
+            if resolved_arch != detected_arch:
+                raise ValueError(
+                    "Flash-KMeans launch arch must match the active device: "
+                    f"requested {resolved_arch}, detected {detected_arch}"
+                )
+        caller_supplied_out = out is not None
+        if not caller_supplied_out:
+            out = torch.empty((bsz, n_points), dtype=torch.int32, device=x.device)
+        else:
+            _require_aux_tensor(
+                out,
+                name="out",
+                shape=(bsz, n_points),
+                dtype=torch.int32,
+                device=x.device,
+            )
+        compute_x_sq = x_sq is None
+        compute_c_sq = c_sq is None
+        if not defer_missing_norms:
+            if compute_x_sq:
+                x_sq = torch.empty((bsz, n_points), dtype=torch.float32, device=x.device)
+            if compute_c_sq:
+                c_sq = torch.empty((bsz, n_clusters), dtype=torch.float32, device=x.device)
+        if x_sq is not None:
+            _require_aux_tensor(
+                x_sq,
+                name="x_sq",
+                shape=(bsz, n_points),
+                dtype=torch.float32,
+                device=x.device,
+            )
+        if c_sq is not None:
+            _require_aux_tensor(
+                c_sq,
+                name="c_sq",
+                shape=(bsz, n_clusters),
+                dtype=torch.float32,
+                device=x.device,
+            )
+        if (compute_x_sq or compute_c_sq) and not defer_missing_norms:
+            # This single custom launch converts BF16, squares, and reduces
+            # both row sets without PyTorch conversion/reduction temporaries.
+            from ._row_norm import launch_bf16_pair_row_norm
+
+            _record_stream(resolved_stream, x, centroids, x_sq, c_sq, out)
+            launch_bf16_pair_row_norm(
+                x,
+                centroids,
+                x_sq,
+                c_sq,
+                compute_x=compute_x_sq,
+                compute_c=compute_c_sq,
+                stream=resolved_stream,
+                arch=resolved_arch,
+                timeout_ms=timeout_ms,
+            )
+        norm_mode = (
+            "fused_bf16_pair_row_norm"
+            if compute_x_sq and compute_c_sq
+            else "mixed_fused_bf16_pair_row_norm"
+            if compute_x_sq or compute_c_sq
+            else "explicit_precomputed"
+        )
+        inputs = {
+            "B": bsz,
+            "N": n_points,
+            "D": dim,
+            "K": n_clusters,
+            "dtype": "bfloat16",
+            "x": x,
+            "centroids": centroids,
+            "x_sq": x_sq,
+            "c_sq": c_sq,
+            "out": out,
+            "_norm_mode": norm_mode,
+        }
+    return inputs, resolved_stream, resolved_arch
+
+
+def prepare_flash_kmeans_assign(
+    x: Any,
+    centroids: Any,
+    *,
+    out: Any | None = None,
+    x_sq: Any | None = None,
+    c_sq: Any | None = None,
+    arch: str | None = None,
+    stream: Any = None,
+    timeout_ms: float | None = None,
+) -> PreparedFlashKMeansAssign:
+    """Validate and prepare an allocation-free direct launch for exact tensors."""
+
+    timeout_ms = _validate_timeout(timeout_ms)
+
+    inputs, resolved_stream, resolved_arch = _prepare_inputs(
+        x,
+        centroids,
+        out=out,
+        x_sq=x_sq,
+        c_sq=c_sq,
+        device_index=None,
+        arch=arch,
+        stream=stream,
+        timeout_ms=timeout_ms,
+    )
+    import torch
+
+    input_device_index = inputs["x"].device.index
+    device_index = int(torch.cuda.current_device() if input_device_index is None else input_device_index)
+    with torch.cuda.device(device_index), torch.cuda.stream(resolved_stream):
+        launch_plan = _dispatcher.prepare_launch_plan(
+            inputs,
+            arch=resolved_arch,
+            stream=resolved_stream,
+            timeout_ms=timeout_ms,
+        )
+    return PreparedFlashKMeansAssign(
+        inputs=inputs,
+        launch_plan=launch_plan,
+        stream=resolved_stream,
+        timeout_ms=timeout_ms,
+    )
+
+
+def flash_kmeans_assign_prepared(
+    prepared: PreparedFlashKMeansAssign,
+    *,
+    stream: Any = None,
+    timeout_ms: float | None = None,
+    return_info: bool = False,
+):
+    """Submit a prepared plan without route selection, allocation, or packing."""
+
+    if not isinstance(prepared, PreparedFlashKMeansAssign):
+        raise TypeError("prepared must be returned by prepare_flash_kmeans_assign")
+    effective_timeout_ms = prepared.timeout_ms if timeout_ms is None else _validate_timeout(timeout_ms)
+    resolved_stream = prepared.stream if stream is None else stream
+    _record_stream(
+        resolved_stream,
+        *(prepared.inputs[name] for name in ("x", "centroids", "x_sq", "c_sq", "out")),
+    )
+    result = _dispatcher.launch_prepared(
+        prepared.launch_plan,
+        stream=resolved_stream,
+        timeout_ms=effective_timeout_ms,
+        public_inputs_already_recorded=True,
+    )
+    produced = result.get("cluster_ids", prepared.out) if isinstance(result, dict) else prepared.out
+    if produced is not prepared.out:
+        prepared.out.copy_(produced)
+    if not return_info:
+        return prepared.out
+    info = {
+        "semantic_entrypoint": SEMANTIC_ENTRYPOINT,
+        "selected_route": prepared.selected_route,
+        "launch_entrypoint": prepared.launch_plan.launch_entrypoint,
+        "exact_launch_plan": True,
+        "prepared_launch_count": prepared.launch_plan.launch_count,
+        "arch": prepared.launch_plan.arch,
+        "device_index": prepared.launch_plan.device_index,
+        "stream_handle": prepared.launch_plan.stream_handle,
+    }
+    return prepared.out, info
+
+
+def flash_kmeans_assign(
+    x: Any,
+    centroids: Any,
+    *,
+    out: Any | None = None,
+    x_sq: Any | None = None,
+    c_sq: Any | None = None,
+    arch: str | None = None,
+    stream: Any = None,
+    timeout_ms: float | None = None,
+    return_info: bool = False,
+):
+    """Assign points to centroids through a cold prepared/direct launch."""
+    timeout_ms = _validate_timeout(timeout_ms)
+    with launch_context(arch=arch, stream=stream, timeout_ms=timeout_ms):
+        prepared = prepare_flash_kmeans_assign(
+            x,
+            centroids,
+            out=out,
+            x_sq=x_sq,
+            c_sq=c_sq,
+            arch=arch,
+            stream=stream,
+            timeout_ms=timeout_ms,
+        )
+        return flash_kmeans_assign_prepared(
+            prepared,
+            stream=prepared.stream,
+            return_info=return_info,
+        )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/kernels.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/kernels.py
new file mode 100644
index 00000000..32b33d0f
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/kernels.py
@@ -0,0 +1,9150 @@
+from __future__ import annotations
+
+import json
+from dataclasses import dataclass
+from importlib import resources
+from typing import TYPE_CHECKING, Any
+
+if TYPE_CHECKING:
+    from ._runtime import CUDAKernel
+
+
+@dataclass(frozen=True)
+class KernelSpec:
+    name: str
+    symbol: str
+    source: str
+    threads: int
+    shared_mem_bytes: int
+    cluster_dims: tuple[int, int, int]
+    launch_mode: str
+    parameters: tuple[dict[str, str], ...]
+    specializations: dict[str, int | str]
+    compile_options: tuple[str, ...]
+
+    @staticmethod
+    def from_manifest(entry: dict[str, Any]) -> "KernelSpec":
+        return KernelSpec(
+            name=entry["name"],
+            symbol=entry["symbol"],
+            source=entry["source"],
+            threads=int(entry["threads"]),
+            shared_mem_bytes=int(entry["shared_mem_bytes"]),
+            cluster_dims=tuple(int(v) for v in entry["cluster_dims"]),
+            launch_mode=entry["launch_mode"],
+            parameters=tuple(entry["parameters"]),
+            specializations=dict(entry.get("specializations", {})),
+            compile_options=tuple(str(option) for option in entry.get("compile_options", ())),
+        )
+
+
+class ExportedKernel:
+    def __init__(self, spec: KernelSpec):
+        self.spec = spec
+        self._compiled: dict[tuple[str, tuple[str, ...], int, int], "CUDAKernel"] = {}
+        self._arg_types = tuple(parameter["ctype"] for parameter in spec.parameters)
+        self._default_block = (spec.threads, 1, 1)
+        self._default_shared_mem = spec.shared_mem_bytes
+        self._source_cache: str | None = None
+        self._source_digest: str | None = None
+
+    @property
+    def parameters(self) -> tuple[dict[str, str], ...]:
+        return self.spec.parameters
+
+    @property
+    def arg_types(self) -> tuple[str, ...]:
+        return self._arg_types
+
+    def source_text(self) -> str:
+        if self._source_cache is None:
+            from ._runtime import record_source_read
+
+            package = __package__ or __name__.rpartition(".")[0]
+            self._source_cache = resources.files(package).joinpath(self.spec.source).read_text(encoding="utf-8")
+            record_source_read()
+        return self._source_cache
+
+    def compile(self, *, arch: str | None = None, options: list[str] | None = None) -> "CUDAKernel":
+        effective_options = tuple(dict.fromkeys((*self.spec.compile_options, *(options or ()))))
+        from ._runtime import (
+            compilation_cache_generation,
+            current_cuda_device_index,
+            load_cached_kernel,
+            resolve_gpu_arch,
+        )
+
+        resolved_arch = resolve_gpu_arch(arch)
+        device_index = current_cuda_device_index()
+        generation = compilation_cache_generation()
+        key = (resolved_arch, effective_options, device_index, generation)
+        kernel = self._compiled.get(key)
+        if kernel is None or kernel.closed:
+            source = self.source_text()
+            if self._source_digest is None:
+                import hashlib
+
+                self._source_digest = hashlib.sha256(source.encode("utf-8")).hexdigest()
+            kernel = load_cached_kernel(
+                source,
+                source_digest=self._source_digest,
+                func_name=self.spec.symbol,
+                arch=resolved_arch,
+                device_index=device_index,
+                name=f"{self.spec.name}.cu",
+                options=effective_options,
+            )
+            self._compiled[key] = kernel
+        return kernel
+
+    def launch(
+        self,
+        *args,
+        grid: tuple[int, int, int],
+        block: tuple[int, int, int] | None = None,
+        shared_mem: int | None = None,
+        stream=None,
+        timeout_ms: float | None = None,
+        arch: str | None = None,
+        options: list[str] | None = None,
+    ) -> None:
+        from ._runtime import resolve_launch_defaults
+
+        arch, stream, timeout_ms = resolve_launch_defaults(
+            arch=arch,
+            stream=stream,
+            timeout_ms=timeout_ms,
+        )
+        prepared = self.prepare_launch(
+            *args,
+            grid=grid,
+            block=block,
+            shared_mem=shared_mem,
+            stream=stream,
+            arch=arch,
+            options=options,
+        )
+        prepared.launch(timeout_ms=timeout_ms)
+
+    def prepare_launch(
+        self,
+        *args,
+        grid: tuple[int, int, int],
+        block: tuple[int, int, int] | None = None,
+        shared_mem: int | None = None,
+        stream=None,
+        arch: str | None = None,
+        options: list[str] | None = None,
+    ):
+        # Compile and fully marshal one launch without submitting GPU work.
+
+        if len(args) != len(self.spec.parameters):
+            expected = ", ".join(p["name"] for p in self.spec.parameters)
+            raise TypeError(f"{self.spec.name} expects {len(self.spec.parameters)} args ({expected}), got {len(args)}")
+        from ._runtime import launch_stream_context, resolve_launch_defaults
+
+        arch, stream, _ = resolve_launch_defaults(
+            arch=arch,
+            stream=stream,
+            timeout_ms=None,
+        )
+        if block is None:
+            block = self._default_block
+        if shared_mem is None:
+            shared_mem = self._default_shared_mem
+        with launch_stream_context(stream):
+            kernel = self.compile(arch=arch, options=options)
+            if self.spec.launch_mode == "cluster":
+                return kernel.prepare_launch_cluster(
+                    grid=grid,
+                    block=block,
+                    args=args,
+                    arg_types=self._arg_types,
+                    cluster_dims=self.spec.cluster_dims,
+                    shared_mem=shared_mem,
+                    stream=stream,
+                )
+            if self.spec.launch_mode == "cooperative":
+                return kernel.prepare_launch_cooperative(
+                    grid=grid,
+                    block=block,
+                    args=args,
+                    arg_types=self._arg_types,
+                    shared_mem=shared_mem,
+                    stream=stream,
+                )
+            return kernel.prepare_launch(
+                grid=grid,
+                block=block,
+                args=args,
+                arg_types=self._arg_types,
+                shared_mem=shared_mem,
+                stream=stream,
+            )
+
+
+def _load_manifest() -> dict[str, Any]:
+    package = __package__ or __name__.rpartition(".")[0]
+    return json.loads(resources.files(package).joinpath("manifest.json").read_text(encoding="utf-8"))
+
+
+_MANIFEST = _load_manifest()
+KERNELS = {entry["name"]: ExportedKernel(KernelSpec.from_manifest(entry)) for entry in _MANIFEST["kernels"]}
+
+
+def get_kernel(name: str) -> ExportedKernel:
+    try:
+        return KERNELS[name]
+    except KeyError as exc:
+        available = ", ".join(sorted(KERNELS))
+        raise KeyError(f"Unknown exported kernel {name!r}. Available: {available}") from exc
+
+
+dispatch_kernel_0000 = get_kernel('dispatch_kernel_0000')
+
+
+def launch_dispatch_kernel_0000(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0000.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0001 = get_kernel('dispatch_kernel_0001')
+
+
+def launch_dispatch_kernel_0001(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0001.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0002 = get_kernel('dispatch_kernel_0002')
+
+
+def launch_dispatch_kernel_0002(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0002.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0003 = get_kernel('dispatch_kernel_0003')
+
+
+def launch_dispatch_kernel_0003(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0003.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0004 = get_kernel('dispatch_kernel_0004')
+
+
+def launch_dispatch_kernel_0004(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0004.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0005 = get_kernel('dispatch_kernel_0005')
+
+
+def launch_dispatch_kernel_0005(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0005.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0006 = get_kernel('dispatch_kernel_0006')
+
+
+def launch_dispatch_kernel_0006(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0006.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0007 = get_kernel('dispatch_kernel_0007')
+
+
+def launch_dispatch_kernel_0007(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0007.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0008 = get_kernel('dispatch_kernel_0008')
+
+
+def launch_dispatch_kernel_0008(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0008.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0009 = get_kernel('dispatch_kernel_0009')
+
+
+def launch_dispatch_kernel_0009(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0009.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0010 = get_kernel('dispatch_kernel_0010')
+
+
+def launch_dispatch_kernel_0010(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0010.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0011 = get_kernel('dispatch_kernel_0011')
+
+
+def launch_dispatch_kernel_0011(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0011.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0012 = get_kernel('dispatch_kernel_0012')
+
+
+def launch_dispatch_kernel_0012(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0012.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0013 = get_kernel('dispatch_kernel_0013')
+
+
+def launch_dispatch_kernel_0013(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0013.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0014 = get_kernel('dispatch_kernel_0014')
+
+
+def launch_dispatch_kernel_0014(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0014.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0015 = get_kernel('dispatch_kernel_0015')
+
+
+def launch_dispatch_kernel_0015(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0015.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0016 = get_kernel('dispatch_kernel_0016')
+
+
+def launch_dispatch_kernel_0016(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0016.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0017 = get_kernel('dispatch_kernel_0017')
+
+
+def launch_dispatch_kernel_0017(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0017.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0018 = get_kernel('dispatch_kernel_0018')
+
+
+def launch_dispatch_kernel_0018(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0018.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0019 = get_kernel('dispatch_kernel_0019')
+
+
+def launch_dispatch_kernel_0019(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0019.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0020 = get_kernel('dispatch_kernel_0020')
+
+
+def launch_dispatch_kernel_0020(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0020.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0021 = get_kernel('dispatch_kernel_0021')
+
+
+def launch_dispatch_kernel_0021(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0021.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0022 = get_kernel('dispatch_kernel_0022')
+
+
+def launch_dispatch_kernel_0022(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0022.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0023 = get_kernel('dispatch_kernel_0023')
+
+
+def launch_dispatch_kernel_0023(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0023.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0024 = get_kernel('dispatch_kernel_0024')
+
+
+def launch_dispatch_kernel_0024(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0024.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0025 = get_kernel('dispatch_kernel_0025')
+
+
+def launch_dispatch_kernel_0025(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0025.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0026 = get_kernel('dispatch_kernel_0026')
+
+
+def launch_dispatch_kernel_0026(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0026.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0027 = get_kernel('dispatch_kernel_0027')
+
+
+def launch_dispatch_kernel_0027(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0027.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0028 = get_kernel('dispatch_kernel_0028')
+
+
+def launch_dispatch_kernel_0028(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0028.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0029 = get_kernel('dispatch_kernel_0029')
+
+
+def launch_dispatch_kernel_0029(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0029.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0030 = get_kernel('dispatch_kernel_0030')
+
+
+def launch_dispatch_kernel_0030(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0030.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0031 = get_kernel('dispatch_kernel_0031')
+
+
+def launch_dispatch_kernel_0031(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0031.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0032 = get_kernel('dispatch_kernel_0032')
+
+
+def launch_dispatch_kernel_0032(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0032.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0033 = get_kernel('dispatch_kernel_0033')
+
+
+def launch_dispatch_kernel_0033(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0033.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0034 = get_kernel('dispatch_kernel_0034')
+
+
+def launch_dispatch_kernel_0034(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0034.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0035 = get_kernel('dispatch_kernel_0035')
+
+
+def launch_dispatch_kernel_0035(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0035.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0036 = get_kernel('dispatch_kernel_0036')
+
+
+def launch_dispatch_kernel_0036(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0036.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0037 = get_kernel('dispatch_kernel_0037')
+
+
+def launch_dispatch_kernel_0037(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0037.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0038 = get_kernel('dispatch_kernel_0038')
+
+
+def launch_dispatch_kernel_0038(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0038.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0039 = get_kernel('dispatch_kernel_0039')
+
+
+def launch_dispatch_kernel_0039(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0039.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0040 = get_kernel('dispatch_kernel_0040')
+
+
+def launch_dispatch_kernel_0040(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0040.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0041 = get_kernel('dispatch_kernel_0041')
+
+
+def launch_dispatch_kernel_0041(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0041.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0042 = get_kernel('dispatch_kernel_0042')
+
+
+def launch_dispatch_kernel_0042(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0042.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0043 = get_kernel('dispatch_kernel_0043')
+
+
+def launch_dispatch_kernel_0043(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0043.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0044 = get_kernel('dispatch_kernel_0044')
+
+
+def launch_dispatch_kernel_0044(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0044.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0045 = get_kernel('dispatch_kernel_0045')
+
+
+def launch_dispatch_kernel_0045(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0045.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0046 = get_kernel('dispatch_kernel_0046')
+
+
+def launch_dispatch_kernel_0046(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0046.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0047 = get_kernel('dispatch_kernel_0047')
+
+
+def launch_dispatch_kernel_0047(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0047.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0048 = get_kernel('dispatch_kernel_0048')
+
+
+def launch_dispatch_kernel_0048(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0048.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0049 = get_kernel('dispatch_kernel_0049')
+
+
+def launch_dispatch_kernel_0049(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0049.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0050 = get_kernel('dispatch_kernel_0050')
+
+
+def launch_dispatch_kernel_0050(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0050.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0051 = get_kernel('dispatch_kernel_0051')
+
+
+def launch_dispatch_kernel_0051(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0051.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0052 = get_kernel('dispatch_kernel_0052')
+
+
+def launch_dispatch_kernel_0052(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0052.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0053 = get_kernel('dispatch_kernel_0053')
+
+
+def launch_dispatch_kernel_0053(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0053.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0054 = get_kernel('dispatch_kernel_0054')
+
+
+def launch_dispatch_kernel_0054(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0054.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0055 = get_kernel('dispatch_kernel_0055')
+
+
+def launch_dispatch_kernel_0055(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0055.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0056 = get_kernel('dispatch_kernel_0056')
+
+
+def launch_dispatch_kernel_0056(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0056.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0057 = get_kernel('dispatch_kernel_0057')
+
+
+def launch_dispatch_kernel_0057(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0057.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0058 = get_kernel('dispatch_kernel_0058')
+
+
+def launch_dispatch_kernel_0058(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0058.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0059 = get_kernel('dispatch_kernel_0059')
+
+
+def launch_dispatch_kernel_0059(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0059.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0060 = get_kernel('dispatch_kernel_0060')
+
+
+def launch_dispatch_kernel_0060(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0060.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0061 = get_kernel('dispatch_kernel_0061')
+
+
+def launch_dispatch_kernel_0061(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0061.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0062 = get_kernel('dispatch_kernel_0062')
+
+
+def launch_dispatch_kernel_0062(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0062.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0063 = get_kernel('dispatch_kernel_0063')
+
+
+def launch_dispatch_kernel_0063(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0063.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0064 = get_kernel('dispatch_kernel_0064')
+
+
+def launch_dispatch_kernel_0064(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0064.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0065 = get_kernel('dispatch_kernel_0065')
+
+
+def launch_dispatch_kernel_0065(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0065.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0066 = get_kernel('dispatch_kernel_0066')
+
+
+def launch_dispatch_kernel_0066(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0066.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0067 = get_kernel('dispatch_kernel_0067')
+
+
+def launch_dispatch_kernel_0067(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0067.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0068 = get_kernel('dispatch_kernel_0068')
+
+
+def launch_dispatch_kernel_0068(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0068.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0069 = get_kernel('dispatch_kernel_0069')
+
+
+def launch_dispatch_kernel_0069(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0069.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0070 = get_kernel('dispatch_kernel_0070')
+
+
+def launch_dispatch_kernel_0070(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0070.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0071 = get_kernel('dispatch_kernel_0071')
+
+
+def launch_dispatch_kernel_0071(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0071.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0072 = get_kernel('dispatch_kernel_0072')
+
+
+def launch_dispatch_kernel_0072(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0072.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0073 = get_kernel('dispatch_kernel_0073')
+
+
+def launch_dispatch_kernel_0073(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0073.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0074 = get_kernel('dispatch_kernel_0074')
+
+
+def launch_dispatch_kernel_0074(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0074.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0075 = get_kernel('dispatch_kernel_0075')
+
+
+def launch_dispatch_kernel_0075(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0075.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0076 = get_kernel('dispatch_kernel_0076')
+
+
+def launch_dispatch_kernel_0076(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0076.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0077 = get_kernel('dispatch_kernel_0077')
+
+
+def launch_dispatch_kernel_0077(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0077.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0078 = get_kernel('dispatch_kernel_0078')
+
+
+def launch_dispatch_kernel_0078(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0078.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0079 = get_kernel('dispatch_kernel_0079')
+
+
+def launch_dispatch_kernel_0079(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0079.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0080 = get_kernel('dispatch_kernel_0080')
+
+
+def launch_dispatch_kernel_0080(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0080.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0081 = get_kernel('dispatch_kernel_0081')
+
+
+def launch_dispatch_kernel_0081(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0081.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0082 = get_kernel('dispatch_kernel_0082')
+
+
+def launch_dispatch_kernel_0082(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0082.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0083 = get_kernel('dispatch_kernel_0083')
+
+
+def launch_dispatch_kernel_0083(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0083.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0084 = get_kernel('dispatch_kernel_0084')
+
+
+def launch_dispatch_kernel_0084(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0084.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0085 = get_kernel('dispatch_kernel_0085')
+
+
+def launch_dispatch_kernel_0085(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0085.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0086 = get_kernel('dispatch_kernel_0086')
+
+
+def launch_dispatch_kernel_0086(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0086.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0087 = get_kernel('dispatch_kernel_0087')
+
+
+def launch_dispatch_kernel_0087(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0087.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0088 = get_kernel('dispatch_kernel_0088')
+
+
+def launch_dispatch_kernel_0088(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0088.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0089 = get_kernel('dispatch_kernel_0089')
+
+
+def launch_dispatch_kernel_0089(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0089.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0090 = get_kernel('dispatch_kernel_0090')
+
+
+def launch_dispatch_kernel_0090(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0090.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0091 = get_kernel('dispatch_kernel_0091')
+
+
+def launch_dispatch_kernel_0091(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0091.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0092 = get_kernel('dispatch_kernel_0092')
+
+
+def launch_dispatch_kernel_0092(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0092.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0093 = get_kernel('dispatch_kernel_0093')
+
+
+def launch_dispatch_kernel_0093(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0093.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0094 = get_kernel('dispatch_kernel_0094')
+
+
+def launch_dispatch_kernel_0094(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0094.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0095 = get_kernel('dispatch_kernel_0095')
+
+
+def launch_dispatch_kernel_0095(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0095.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0096 = get_kernel('dispatch_kernel_0096')
+
+
+def launch_dispatch_kernel_0096(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0096.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0097 = get_kernel('dispatch_kernel_0097')
+
+
+def launch_dispatch_kernel_0097(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0097.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0098 = get_kernel('dispatch_kernel_0098')
+
+
+def launch_dispatch_kernel_0098(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0098.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0099 = get_kernel('dispatch_kernel_0099')
+
+
+def launch_dispatch_kernel_0099(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0099.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0100 = get_kernel('dispatch_kernel_0100')
+
+
+def launch_dispatch_kernel_0100(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0100.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0101 = get_kernel('dispatch_kernel_0101')
+
+
+def launch_dispatch_kernel_0101(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0101.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0102 = get_kernel('dispatch_kernel_0102')
+
+
+def launch_dispatch_kernel_0102(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0102.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0103 = get_kernel('dispatch_kernel_0103')
+
+
+def launch_dispatch_kernel_0103(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0103.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0104 = get_kernel('dispatch_kernel_0104')
+
+
+def launch_dispatch_kernel_0104(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0104.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0105 = get_kernel('dispatch_kernel_0105')
+
+
+def launch_dispatch_kernel_0105(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0105.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0106 = get_kernel('dispatch_kernel_0106')
+
+
+def launch_dispatch_kernel_0106(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0106.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0107 = get_kernel('dispatch_kernel_0107')
+
+
+def launch_dispatch_kernel_0107(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0107.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0108 = get_kernel('dispatch_kernel_0108')
+
+
+def launch_dispatch_kernel_0108(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0108.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0109 = get_kernel('dispatch_kernel_0109')
+
+
+def launch_dispatch_kernel_0109(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0109.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0110 = get_kernel('dispatch_kernel_0110')
+
+
+def launch_dispatch_kernel_0110(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0110.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0111 = get_kernel('dispatch_kernel_0111')
+
+
+def launch_dispatch_kernel_0111(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0111.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0112 = get_kernel('dispatch_kernel_0112')
+
+
+def launch_dispatch_kernel_0112(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0112.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0113 = get_kernel('dispatch_kernel_0113')
+
+
+def launch_dispatch_kernel_0113(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0113.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0114 = get_kernel('dispatch_kernel_0114')
+
+
+def launch_dispatch_kernel_0114(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0114.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0115 = get_kernel('dispatch_kernel_0115')
+
+
+def launch_dispatch_kernel_0115(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0115.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0116 = get_kernel('dispatch_kernel_0116')
+
+
+def launch_dispatch_kernel_0116(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0116.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0117 = get_kernel('dispatch_kernel_0117')
+
+
+def launch_dispatch_kernel_0117(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0117.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0118 = get_kernel('dispatch_kernel_0118')
+
+
+def launch_dispatch_kernel_0118(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0118.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0119 = get_kernel('dispatch_kernel_0119')
+
+
+def launch_dispatch_kernel_0119(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0119.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0120 = get_kernel('dispatch_kernel_0120')
+
+
+def launch_dispatch_kernel_0120(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0120.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0121 = get_kernel('dispatch_kernel_0121')
+
+
+def launch_dispatch_kernel_0121(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0121.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0122 = get_kernel('dispatch_kernel_0122')
+
+
+def launch_dispatch_kernel_0122(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0122.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0123 = get_kernel('dispatch_kernel_0123')
+
+
+def launch_dispatch_kernel_0123(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0123.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0124 = get_kernel('dispatch_kernel_0124')
+
+
+def launch_dispatch_kernel_0124(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0124.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0125 = get_kernel('dispatch_kernel_0125')
+
+
+def launch_dispatch_kernel_0125(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0125.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0126 = get_kernel('dispatch_kernel_0126')
+
+
+def launch_dispatch_kernel_0126(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0126.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0127 = get_kernel('dispatch_kernel_0127')
+
+
+def launch_dispatch_kernel_0127(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0127.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0128 = get_kernel('dispatch_kernel_0128')
+
+
+def launch_dispatch_kernel_0128(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0128.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0129 = get_kernel('dispatch_kernel_0129')
+
+
+def launch_dispatch_kernel_0129(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0129.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0130 = get_kernel('dispatch_kernel_0130')
+
+
+def launch_dispatch_kernel_0130(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0130.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0131 = get_kernel('dispatch_kernel_0131')
+
+
+def launch_dispatch_kernel_0131(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0131.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0132 = get_kernel('dispatch_kernel_0132')
+
+
+def launch_dispatch_kernel_0132(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0132.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0133 = get_kernel('dispatch_kernel_0133')
+
+
+def launch_dispatch_kernel_0133(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0133.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0134 = get_kernel('dispatch_kernel_0134')
+
+
+def launch_dispatch_kernel_0134(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0134.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0135 = get_kernel('dispatch_kernel_0135')
+
+
+def launch_dispatch_kernel_0135(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0135.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0136 = get_kernel('dispatch_kernel_0136')
+
+
+def launch_dispatch_kernel_0136(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0136.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0137 = get_kernel('dispatch_kernel_0137')
+
+
+def launch_dispatch_kernel_0137(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0137.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0138 = get_kernel('dispatch_kernel_0138')
+
+
+def launch_dispatch_kernel_0138(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0138.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0139 = get_kernel('dispatch_kernel_0139')
+
+
+def launch_dispatch_kernel_0139(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0139.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0140 = get_kernel('dispatch_kernel_0140')
+
+
+def launch_dispatch_kernel_0140(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0140.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0141 = get_kernel('dispatch_kernel_0141')
+
+
+def launch_dispatch_kernel_0141(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0141.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0142 = get_kernel('dispatch_kernel_0142')
+
+
+def launch_dispatch_kernel_0142(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0142.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0143 = get_kernel('dispatch_kernel_0143')
+
+
+def launch_dispatch_kernel_0143(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0143.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0144 = get_kernel('dispatch_kernel_0144')
+
+
+def launch_dispatch_kernel_0144(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0144.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0145 = get_kernel('dispatch_kernel_0145')
+
+
+def launch_dispatch_kernel_0145(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0145.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0146 = get_kernel('dispatch_kernel_0146')
+
+
+def launch_dispatch_kernel_0146(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0146.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0147 = get_kernel('dispatch_kernel_0147')
+
+
+def launch_dispatch_kernel_0147(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0147.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0148 = get_kernel('dispatch_kernel_0148')
+
+
+def launch_dispatch_kernel_0148(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0148.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0149 = get_kernel('dispatch_kernel_0149')
+
+
+def launch_dispatch_kernel_0149(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0149.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0150 = get_kernel('dispatch_kernel_0150')
+
+
+def launch_dispatch_kernel_0150(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0150.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0151 = get_kernel('dispatch_kernel_0151')
+
+
+def launch_dispatch_kernel_0151(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0151.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0152 = get_kernel('dispatch_kernel_0152')
+
+
+def launch_dispatch_kernel_0152(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0152.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0153 = get_kernel('dispatch_kernel_0153')
+
+
+def launch_dispatch_kernel_0153(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0153.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0154 = get_kernel('dispatch_kernel_0154')
+
+
+def launch_dispatch_kernel_0154(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0154.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0155 = get_kernel('dispatch_kernel_0155')
+
+
+def launch_dispatch_kernel_0155(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0155.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0156 = get_kernel('dispatch_kernel_0156')
+
+
+def launch_dispatch_kernel_0156(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0156.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0157 = get_kernel('dispatch_kernel_0157')
+
+
+def launch_dispatch_kernel_0157(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0157.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0158 = get_kernel('dispatch_kernel_0158')
+
+
+def launch_dispatch_kernel_0158(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0158.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0159 = get_kernel('dispatch_kernel_0159')
+
+
+def launch_dispatch_kernel_0159(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0159.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0160 = get_kernel('dispatch_kernel_0160')
+
+
+def launch_dispatch_kernel_0160(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0160.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0161 = get_kernel('dispatch_kernel_0161')
+
+
+def launch_dispatch_kernel_0161(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0161.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0162 = get_kernel('dispatch_kernel_0162')
+
+
+def launch_dispatch_kernel_0162(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0162.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0163 = get_kernel('dispatch_kernel_0163')
+
+
+def launch_dispatch_kernel_0163(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0163.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0164 = get_kernel('dispatch_kernel_0164')
+
+
+def launch_dispatch_kernel_0164(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0164.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0165 = get_kernel('dispatch_kernel_0165')
+
+
+def launch_dispatch_kernel_0165(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0165.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0166 = get_kernel('dispatch_kernel_0166')
+
+
+def launch_dispatch_kernel_0166(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0166.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0167 = get_kernel('dispatch_kernel_0167')
+
+
+def launch_dispatch_kernel_0167(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0167.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0168 = get_kernel('dispatch_kernel_0168')
+
+
+def launch_dispatch_kernel_0168(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0168.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0169 = get_kernel('dispatch_kernel_0169')
+
+
+def launch_dispatch_kernel_0169(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0169.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0170 = get_kernel('dispatch_kernel_0170')
+
+
+def launch_dispatch_kernel_0170(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0170.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0171 = get_kernel('dispatch_kernel_0171')
+
+
+def launch_dispatch_kernel_0171(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0171.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0172 = get_kernel('dispatch_kernel_0172')
+
+
+def launch_dispatch_kernel_0172(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0172.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0173 = get_kernel('dispatch_kernel_0173')
+
+
+def launch_dispatch_kernel_0173(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0173.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0174 = get_kernel('dispatch_kernel_0174')
+
+
+def launch_dispatch_kernel_0174(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0174.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0175 = get_kernel('dispatch_kernel_0175')
+
+
+def launch_dispatch_kernel_0175(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0175.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0176 = get_kernel('dispatch_kernel_0176')
+
+
+def launch_dispatch_kernel_0176(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0176.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0177 = get_kernel('dispatch_kernel_0177')
+
+
+def launch_dispatch_kernel_0177(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0177.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0178 = get_kernel('dispatch_kernel_0178')
+
+
+def launch_dispatch_kernel_0178(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0178.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0179 = get_kernel('dispatch_kernel_0179')
+
+
+def launch_dispatch_kernel_0179(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0179.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0180 = get_kernel('dispatch_kernel_0180')
+
+
+def launch_dispatch_kernel_0180(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0180.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0181 = get_kernel('dispatch_kernel_0181')
+
+
+def launch_dispatch_kernel_0181(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0181.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0182 = get_kernel('dispatch_kernel_0182')
+
+
+def launch_dispatch_kernel_0182(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0182.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0183 = get_kernel('dispatch_kernel_0183')
+
+
+def launch_dispatch_kernel_0183(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0183.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0184 = get_kernel('dispatch_kernel_0184')
+
+
+def launch_dispatch_kernel_0184(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0184.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0185 = get_kernel('dispatch_kernel_0185')
+
+
+def launch_dispatch_kernel_0185(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0185.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0186 = get_kernel('dispatch_kernel_0186')
+
+
+def launch_dispatch_kernel_0186(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0186.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0187 = get_kernel('dispatch_kernel_0187')
+
+
+def launch_dispatch_kernel_0187(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0187.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0188 = get_kernel('dispatch_kernel_0188')
+
+
+def launch_dispatch_kernel_0188(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0188.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0189 = get_kernel('dispatch_kernel_0189')
+
+
+def launch_dispatch_kernel_0189(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0189.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0190 = get_kernel('dispatch_kernel_0190')
+
+
+def launch_dispatch_kernel_0190(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0190.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0191 = get_kernel('dispatch_kernel_0191')
+
+
+def launch_dispatch_kernel_0191(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0191.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0192 = get_kernel('dispatch_kernel_0192')
+
+
+def launch_dispatch_kernel_0192(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0192.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0193 = get_kernel('dispatch_kernel_0193')
+
+
+def launch_dispatch_kernel_0193(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0193.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0194 = get_kernel('dispatch_kernel_0194')
+
+
+def launch_dispatch_kernel_0194(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0194.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0195 = get_kernel('dispatch_kernel_0195')
+
+
+def launch_dispatch_kernel_0195(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0195.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0196 = get_kernel('dispatch_kernel_0196')
+
+
+def launch_dispatch_kernel_0196(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0196.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0197 = get_kernel('dispatch_kernel_0197')
+
+
+def launch_dispatch_kernel_0197(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0197.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0198 = get_kernel('dispatch_kernel_0198')
+
+
+def launch_dispatch_kernel_0198(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0198.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0199 = get_kernel('dispatch_kernel_0199')
+
+
+def launch_dispatch_kernel_0199(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0199.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0200 = get_kernel('dispatch_kernel_0200')
+
+
+def launch_dispatch_kernel_0200(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0200.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0201 = get_kernel('dispatch_kernel_0201')
+
+
+def launch_dispatch_kernel_0201(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0201.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0202 = get_kernel('dispatch_kernel_0202')
+
+
+def launch_dispatch_kernel_0202(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0202.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0203 = get_kernel('dispatch_kernel_0203')
+
+
+def launch_dispatch_kernel_0203(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0203.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0204 = get_kernel('dispatch_kernel_0204')
+
+
+def launch_dispatch_kernel_0204(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0204.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0205 = get_kernel('dispatch_kernel_0205')
+
+
+def launch_dispatch_kernel_0205(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0205.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0206 = get_kernel('dispatch_kernel_0206')
+
+
+def launch_dispatch_kernel_0206(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0206.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0207 = get_kernel('dispatch_kernel_0207')
+
+
+def launch_dispatch_kernel_0207(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0207.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0208 = get_kernel('dispatch_kernel_0208')
+
+
+def launch_dispatch_kernel_0208(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0208.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0209 = get_kernel('dispatch_kernel_0209')
+
+
+def launch_dispatch_kernel_0209(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0209.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0210 = get_kernel('dispatch_kernel_0210')
+
+
+def launch_dispatch_kernel_0210(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0210.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0211 = get_kernel('dispatch_kernel_0211')
+
+
+def launch_dispatch_kernel_0211(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0211.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0212 = get_kernel('dispatch_kernel_0212')
+
+
+def launch_dispatch_kernel_0212(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0212.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0213 = get_kernel('dispatch_kernel_0213')
+
+
+def launch_dispatch_kernel_0213(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0213.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0214 = get_kernel('dispatch_kernel_0214')
+
+
+def launch_dispatch_kernel_0214(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0214.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0215 = get_kernel('dispatch_kernel_0215')
+
+
+def launch_dispatch_kernel_0215(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0215.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0216 = get_kernel('dispatch_kernel_0216')
+
+
+def launch_dispatch_kernel_0216(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0216.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0217 = get_kernel('dispatch_kernel_0217')
+
+
+def launch_dispatch_kernel_0217(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0217.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0218 = get_kernel('dispatch_kernel_0218')
+
+
+def launch_dispatch_kernel_0218(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0218.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0219 = get_kernel('dispatch_kernel_0219')
+
+
+def launch_dispatch_kernel_0219(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0219.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0220 = get_kernel('dispatch_kernel_0220')
+
+
+def launch_dispatch_kernel_0220(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0220.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0221 = get_kernel('dispatch_kernel_0221')
+
+
+def launch_dispatch_kernel_0221(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0221.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0222 = get_kernel('dispatch_kernel_0222')
+
+
+def launch_dispatch_kernel_0222(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0222.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0223 = get_kernel('dispatch_kernel_0223')
+
+
+def launch_dispatch_kernel_0223(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0223.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0224 = get_kernel('dispatch_kernel_0224')
+
+
+def launch_dispatch_kernel_0224(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0224.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0225 = get_kernel('dispatch_kernel_0225')
+
+
+def launch_dispatch_kernel_0225(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0225.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0226 = get_kernel('dispatch_kernel_0226')
+
+
+def launch_dispatch_kernel_0226(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0226.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0227 = get_kernel('dispatch_kernel_0227')
+
+
+def launch_dispatch_kernel_0227(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0227.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0228 = get_kernel('dispatch_kernel_0228')
+
+
+def launch_dispatch_kernel_0228(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0228.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0229 = get_kernel('dispatch_kernel_0229')
+
+
+def launch_dispatch_kernel_0229(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0229.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0230 = get_kernel('dispatch_kernel_0230')
+
+
+def launch_dispatch_kernel_0230(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0230.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0231 = get_kernel('dispatch_kernel_0231')
+
+
+def launch_dispatch_kernel_0231(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0231.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0232 = get_kernel('dispatch_kernel_0232')
+
+
+def launch_dispatch_kernel_0232(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0232.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0233 = get_kernel('dispatch_kernel_0233')
+
+
+def launch_dispatch_kernel_0233(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0233.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0234 = get_kernel('dispatch_kernel_0234')
+
+
+def launch_dispatch_kernel_0234(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0234.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0235 = get_kernel('dispatch_kernel_0235')
+
+
+def launch_dispatch_kernel_0235(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0235.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0236 = get_kernel('dispatch_kernel_0236')
+
+
+def launch_dispatch_kernel_0236(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0236.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0237 = get_kernel('dispatch_kernel_0237')
+
+
+def launch_dispatch_kernel_0237(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0237.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0238 = get_kernel('dispatch_kernel_0238')
+
+
+def launch_dispatch_kernel_0238(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0238.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0239 = get_kernel('dispatch_kernel_0239')
+
+
+def launch_dispatch_kernel_0239(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0239.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0240 = get_kernel('dispatch_kernel_0240')
+
+
+def launch_dispatch_kernel_0240(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0240.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0241 = get_kernel('dispatch_kernel_0241')
+
+
+def launch_dispatch_kernel_0241(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0241.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0242 = get_kernel('dispatch_kernel_0242')
+
+
+def launch_dispatch_kernel_0242(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0242.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0243 = get_kernel('dispatch_kernel_0243')
+
+
+def launch_dispatch_kernel_0243(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0243.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0244 = get_kernel('dispatch_kernel_0244')
+
+
+def launch_dispatch_kernel_0244(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0244.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0245 = get_kernel('dispatch_kernel_0245')
+
+
+def launch_dispatch_kernel_0245(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0245.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0246 = get_kernel('dispatch_kernel_0246')
+
+
+def launch_dispatch_kernel_0246(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0246.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0247 = get_kernel('dispatch_kernel_0247')
+
+
+def launch_dispatch_kernel_0247(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0247.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0248 = get_kernel('dispatch_kernel_0248')
+
+
+def launch_dispatch_kernel_0248(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0248.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0249 = get_kernel('dispatch_kernel_0249')
+
+
+def launch_dispatch_kernel_0249(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0249.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0250 = get_kernel('dispatch_kernel_0250')
+
+
+def launch_dispatch_kernel_0250(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0250.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0251 = get_kernel('dispatch_kernel_0251')
+
+
+def launch_dispatch_kernel_0251(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0251.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0252 = get_kernel('dispatch_kernel_0252')
+
+
+def launch_dispatch_kernel_0252(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0252.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0253 = get_kernel('dispatch_kernel_0253')
+
+
+def launch_dispatch_kernel_0253(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0253.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0254 = get_kernel('dispatch_kernel_0254')
+
+
+def launch_dispatch_kernel_0254(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0254.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0255 = get_kernel('dispatch_kernel_0255')
+
+
+def launch_dispatch_kernel_0255(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0255.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0256 = get_kernel('dispatch_kernel_0256')
+
+
+def launch_dispatch_kernel_0256(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0256.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0257 = get_kernel('dispatch_kernel_0257')
+
+
+def launch_dispatch_kernel_0257(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0257.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0258 = get_kernel('dispatch_kernel_0258')
+
+
+def launch_dispatch_kernel_0258(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0258.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0259 = get_kernel('dispatch_kernel_0259')
+
+
+def launch_dispatch_kernel_0259(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0259.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0260 = get_kernel('dispatch_kernel_0260')
+
+
+def launch_dispatch_kernel_0260(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0260.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0261 = get_kernel('dispatch_kernel_0261')
+
+
+def launch_dispatch_kernel_0261(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0261.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0262 = get_kernel('dispatch_kernel_0262')
+
+
+def launch_dispatch_kernel_0262(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0262.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0263 = get_kernel('dispatch_kernel_0263')
+
+
+def launch_dispatch_kernel_0263(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0263.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0264 = get_kernel('dispatch_kernel_0264')
+
+
+def launch_dispatch_kernel_0264(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0264.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0265 = get_kernel('dispatch_kernel_0265')
+
+
+def launch_dispatch_kernel_0265(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0265.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0266 = get_kernel('dispatch_kernel_0266')
+
+
+def launch_dispatch_kernel_0266(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0266.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0267 = get_kernel('dispatch_kernel_0267')
+
+
+def launch_dispatch_kernel_0267(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0267.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0268 = get_kernel('dispatch_kernel_0268')
+
+
+def launch_dispatch_kernel_0268(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0268.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0269 = get_kernel('dispatch_kernel_0269')
+
+
+def launch_dispatch_kernel_0269(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0269.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0270 = get_kernel('dispatch_kernel_0270')
+
+
+def launch_dispatch_kernel_0270(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0270.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0271 = get_kernel('dispatch_kernel_0271')
+
+
+def launch_dispatch_kernel_0271(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0271.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0272 = get_kernel('dispatch_kernel_0272')
+
+
+def launch_dispatch_kernel_0272(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0272.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0273 = get_kernel('dispatch_kernel_0273')
+
+
+def launch_dispatch_kernel_0273(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0273.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0274 = get_kernel('dispatch_kernel_0274')
+
+
+def launch_dispatch_kernel_0274(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0274.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0275 = get_kernel('dispatch_kernel_0275')
+
+
+def launch_dispatch_kernel_0275(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0275.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0276 = get_kernel('dispatch_kernel_0276')
+
+
+def launch_dispatch_kernel_0276(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0276.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0277 = get_kernel('dispatch_kernel_0277')
+
+
+def launch_dispatch_kernel_0277(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0277.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0278 = get_kernel('dispatch_kernel_0278')
+
+
+def launch_dispatch_kernel_0278(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0278.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0279 = get_kernel('dispatch_kernel_0279')
+
+
+def launch_dispatch_kernel_0279(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0279.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0280 = get_kernel('dispatch_kernel_0280')
+
+
+def launch_dispatch_kernel_0280(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0280.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0281 = get_kernel('dispatch_kernel_0281')
+
+
+def launch_dispatch_kernel_0281(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0281.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0282 = get_kernel('dispatch_kernel_0282')
+
+
+def launch_dispatch_kernel_0282(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0282.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0283 = get_kernel('dispatch_kernel_0283')
+
+
+def launch_dispatch_kernel_0283(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0283.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0284 = get_kernel('dispatch_kernel_0284')
+
+
+def launch_dispatch_kernel_0284(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0284.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0285 = get_kernel('dispatch_kernel_0285')
+
+
+def launch_dispatch_kernel_0285(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0285.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0286 = get_kernel('dispatch_kernel_0286')
+
+
+def launch_dispatch_kernel_0286(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0286.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0287 = get_kernel('dispatch_kernel_0287')
+
+
+def launch_dispatch_kernel_0287(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0287.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0288 = get_kernel('dispatch_kernel_0288')
+
+
+def launch_dispatch_kernel_0288(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0288.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0289 = get_kernel('dispatch_kernel_0289')
+
+
+def launch_dispatch_kernel_0289(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0289.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0290 = get_kernel('dispatch_kernel_0290')
+
+
+def launch_dispatch_kernel_0290(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0290.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0291 = get_kernel('dispatch_kernel_0291')
+
+
+def launch_dispatch_kernel_0291(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0291.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0292 = get_kernel('dispatch_kernel_0292')
+
+
+def launch_dispatch_kernel_0292(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0292.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0293 = get_kernel('dispatch_kernel_0293')
+
+
+def launch_dispatch_kernel_0293(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0293.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0294 = get_kernel('dispatch_kernel_0294')
+
+
+def launch_dispatch_kernel_0294(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0294.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0295 = get_kernel('dispatch_kernel_0295')
+
+
+def launch_dispatch_kernel_0295(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0295.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0296 = get_kernel('dispatch_kernel_0296')
+
+
+def launch_dispatch_kernel_0296(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0296.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0297 = get_kernel('dispatch_kernel_0297')
+
+
+def launch_dispatch_kernel_0297(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0297.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0298 = get_kernel('dispatch_kernel_0298')
+
+
+def launch_dispatch_kernel_0298(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0298.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0299 = get_kernel('dispatch_kernel_0299')
+
+
+def launch_dispatch_kernel_0299(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0299.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0300 = get_kernel('dispatch_kernel_0300')
+
+
+def launch_dispatch_kernel_0300(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0300.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0301 = get_kernel('dispatch_kernel_0301')
+
+
+def launch_dispatch_kernel_0301(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0301.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0302 = get_kernel('dispatch_kernel_0302')
+
+
+def launch_dispatch_kernel_0302(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0302.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0303 = get_kernel('dispatch_kernel_0303')
+
+
+def launch_dispatch_kernel_0303(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0303.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0304 = get_kernel('dispatch_kernel_0304')
+
+
+def launch_dispatch_kernel_0304(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0304.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0305 = get_kernel('dispatch_kernel_0305')
+
+
+def launch_dispatch_kernel_0305(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0305.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0306 = get_kernel('dispatch_kernel_0306')
+
+
+def launch_dispatch_kernel_0306(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0306.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0307 = get_kernel('dispatch_kernel_0307')
+
+
+def launch_dispatch_kernel_0307(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0307.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0308 = get_kernel('dispatch_kernel_0308')
+
+
+def launch_dispatch_kernel_0308(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0308.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0309 = get_kernel('dispatch_kernel_0309')
+
+
+def launch_dispatch_kernel_0309(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0309.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0310 = get_kernel('dispatch_kernel_0310')
+
+
+def launch_dispatch_kernel_0310(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0310.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0311 = get_kernel('dispatch_kernel_0311')
+
+
+def launch_dispatch_kernel_0311(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0311.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0312 = get_kernel('dispatch_kernel_0312')
+
+
+def launch_dispatch_kernel_0312(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0312.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0313 = get_kernel('dispatch_kernel_0313')
+
+
+def launch_dispatch_kernel_0313(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0313.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0314 = get_kernel('dispatch_kernel_0314')
+
+
+def launch_dispatch_kernel_0314(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0314.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0315 = get_kernel('dispatch_kernel_0315')
+
+
+def launch_dispatch_kernel_0315(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0315.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0316 = get_kernel('dispatch_kernel_0316')
+
+
+def launch_dispatch_kernel_0316(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0316.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0317 = get_kernel('dispatch_kernel_0317')
+
+
+def launch_dispatch_kernel_0317(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0317.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0318 = get_kernel('dispatch_kernel_0318')
+
+
+def launch_dispatch_kernel_0318(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0318.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0319 = get_kernel('dispatch_kernel_0319')
+
+
+def launch_dispatch_kernel_0319(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0319.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0320 = get_kernel('dispatch_kernel_0320')
+
+
+def launch_dispatch_kernel_0320(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0320.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0321 = get_kernel('dispatch_kernel_0321')
+
+
+def launch_dispatch_kernel_0321(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0321.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0322 = get_kernel('dispatch_kernel_0322')
+
+
+def launch_dispatch_kernel_0322(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0322.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0323 = get_kernel('dispatch_kernel_0323')
+
+
+def launch_dispatch_kernel_0323(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0323.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0324 = get_kernel('dispatch_kernel_0324')
+
+
+def launch_dispatch_kernel_0324(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0324.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0325 = get_kernel('dispatch_kernel_0325')
+
+
+def launch_dispatch_kernel_0325(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0325.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0326 = get_kernel('dispatch_kernel_0326')
+
+
+def launch_dispatch_kernel_0326(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0326.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0327 = get_kernel('dispatch_kernel_0327')
+
+
+def launch_dispatch_kernel_0327(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0327.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0328 = get_kernel('dispatch_kernel_0328')
+
+
+def launch_dispatch_kernel_0328(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0328.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0329 = get_kernel('dispatch_kernel_0329')
+
+
+def launch_dispatch_kernel_0329(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0329.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0330 = get_kernel('dispatch_kernel_0330')
+
+
+def launch_dispatch_kernel_0330(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0330.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0331 = get_kernel('dispatch_kernel_0331')
+
+
+def launch_dispatch_kernel_0331(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0331.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0332 = get_kernel('dispatch_kernel_0332')
+
+
+def launch_dispatch_kernel_0332(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0332.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0333 = get_kernel('dispatch_kernel_0333')
+
+
+def launch_dispatch_kernel_0333(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0333.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0334 = get_kernel('dispatch_kernel_0334')
+
+
+def launch_dispatch_kernel_0334(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0334.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0335 = get_kernel('dispatch_kernel_0335')
+
+
+def launch_dispatch_kernel_0335(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0335.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0336 = get_kernel('dispatch_kernel_0336')
+
+
+def launch_dispatch_kernel_0336(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0336.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0337 = get_kernel('dispatch_kernel_0337')
+
+
+def launch_dispatch_kernel_0337(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0337.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0338 = get_kernel('dispatch_kernel_0338')
+
+
+def launch_dispatch_kernel_0338(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0338.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0339 = get_kernel('dispatch_kernel_0339')
+
+
+def launch_dispatch_kernel_0339(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0339.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0340 = get_kernel('dispatch_kernel_0340')
+
+
+def launch_dispatch_kernel_0340(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0340.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0341 = get_kernel('dispatch_kernel_0341')
+
+
+def launch_dispatch_kernel_0341(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0341.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0342 = get_kernel('dispatch_kernel_0342')
+
+
+def launch_dispatch_kernel_0342(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0342.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0343 = get_kernel('dispatch_kernel_0343')
+
+
+def launch_dispatch_kernel_0343(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0343.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0344 = get_kernel('dispatch_kernel_0344')
+
+
+def launch_dispatch_kernel_0344(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0344.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0345 = get_kernel('dispatch_kernel_0345')
+
+
+def launch_dispatch_kernel_0345(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0345.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0346 = get_kernel('dispatch_kernel_0346')
+
+
+def launch_dispatch_kernel_0346(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0346.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0347 = get_kernel('dispatch_kernel_0347')
+
+
+def launch_dispatch_kernel_0347(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0347.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0348 = get_kernel('dispatch_kernel_0348')
+
+
+def launch_dispatch_kernel_0348(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0348.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0349 = get_kernel('dispatch_kernel_0349')
+
+
+def launch_dispatch_kernel_0349(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0349.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0350 = get_kernel('dispatch_kernel_0350')
+
+
+def launch_dispatch_kernel_0350(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0350.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0351 = get_kernel('dispatch_kernel_0351')
+
+
+def launch_dispatch_kernel_0351(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0351.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0352 = get_kernel('dispatch_kernel_0352')
+
+
+def launch_dispatch_kernel_0352(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0352.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0353 = get_kernel('dispatch_kernel_0353')
+
+
+def launch_dispatch_kernel_0353(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0353.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0354 = get_kernel('dispatch_kernel_0354')
+
+
+def launch_dispatch_kernel_0354(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0354.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0355 = get_kernel('dispatch_kernel_0355')
+
+
+def launch_dispatch_kernel_0355(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0355.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0356 = get_kernel('dispatch_kernel_0356')
+
+
+def launch_dispatch_kernel_0356(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0356.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
+
+
+dispatch_kernel_0357 = get_kernel('dispatch_kernel_0357')
+
+
+def launch_dispatch_kernel_0357(
+    *args,
+    grid: tuple[int, int, int],
+    block: tuple[int, int, int] | None = None,
+    shared_mem: int | None = None,
+    stream=None,
+    timeout_ms: float | None = None,
+    arch: str | None = None,
+    options: list[str] | None = None,
+):
+    return dispatch_kernel_0357.launch(
+        *args,
+        grid=grid,
+        block=block,
+        shared_mem=shared_mem,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        arch=arch,
+        options=options,
+    )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json b/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
new file mode 100644
index 00000000..8983105e
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
@@ -0,0 +1,28144 @@
+{
+  "export_plan": {
+    "entrypoints": {
+      "correctness_test": "tests/test_correctness.py",
+      "performance_benchmark": "benchmarks/benchmark.py",
+      "python_interface": "src/flashlib_cake_kmeans/interface.py"
+    },
+    "file": "plan.json",
+    "kernel_count": 358,
+    "metadata": {
+      "baseline": "same-invocation pinned 07cf Triton baseline measured with CUPTI",
+      "inventory": "complete production dispatcher ledger",
+      "launch_resolution": "init-once device runtime with lazy per-shape/per-stream pointer-rebindable direct sequences",
+      "registry_correctness_shapes": 124,
+      "registry_performance_shapes": 124,
+      "runtime_coverage_shapes": 104,
+      "workload": "kmeans_assignment"
+    },
+    "name": "flashlib-kmeans-production",
+    "package_exports": {
+      "FlashKMeansAssignRuntime": ".interface:FlashKMeansAssignRuntime",
+      "PreparedFlashKMeansAssign": ".interface:PreparedFlashKMeansAssign",
+      "flash_kmeans_assign": ".interface:flash_kmeans_assign",
+      "flash_kmeans_assign_prepared": ".interface:flash_kmeans_assign_prepared",
+      "init": ".interface:init",
+      "prepare_flash_kmeans_assign": ".interface:prepare_flash_kmeans_assign"
+    },
+    "sha256": "21acf8461227184f0debdf147a5e70a37c52ce2e3b051178b8e906a5316621a2",
+    "tvm_ffi_exports": {
+      "flash_kmeans_assign": ".interface:flash_kmeans_assign"
+    },
+    "validation": {
+      "benchmark_registry_baseline": {
+        "official": {
+          "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+          "baseline_entrypoint": "benchmarks.flash_kmeans_triton_h200_raw_adapter:TritonH20007cfRawAdapter.compute",
+          "baseline_name": "triton_h200_07cf_raw_adapter_v1",
+          "baseline_timing_backend_field": "baseline_07cf_adapter_timing_backend",
+          "baseline_timing_boundary": "raw_inputs_default_output_shared_fused_pair_norm_plus_pinned_07cf_assign_synchronized_e2e",
+          "candidate_entrypoint": "flashlib_cake_kmeans.interface:FlashKMeansAssignRuntime.compute",
+          "candidate_timing_backend_field": "candidate_public_raw_timing_backend",
+          "candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
+          "role": "publication",
+          "speedup_denominator_metric": "candidate_public_raw_synchronized_e2e_ms",
+          "speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
+          "speedup_numerator_metric": "baseline_07cf_adapter_synchronized_e2e_ms",
+          "timing_backend": "cupti"
+        },
+        "parity": {
+          "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
+          "baseline_entrypoint": "benchmarks.flash_kmeans_triton_h200:euclid_assign_triton_h200",
+          "baseline_name": "triton_h200_07cf_precomputed",
+          "baseline_timing_backend_field": "baseline_07cf_precomputed_timing_backend",
+          "baseline_timing_boundary": "precomputed_norms_preallocated_output_pinned_07cf_assignment_gpu_span",
+          "candidate_entrypoint": "flashlib_cake_kmeans.interface:flash_kmeans_assign_prepared",
+          "candidate_timing_backend_field": "candidate_precomputed_timing_backend",
+          "candidate_timing_boundary": "precomputed_norms_preallocated_output_prepared_assignment_gpu_span",
+          "role": "diagnostic_only",
+          "speedup_denominator_metric": "candidate_precomputed_gpu_span_ms",
+          "speedup_metric": "precomputed_gpu_speedup_vs_07cf",
+          "speedup_numerator_metric": "baseline_07cf_precomputed_gpu_span_ms",
+          "timing_backend": "cupti"
+        },
+        "registry_candidate_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
+        "shared_preprocess": {
+          "implementation_entrypoint": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
+          "result_source_sha256_field": "preprocess_source_sha256",
+          "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104"
+        }
+      },
+      "benchmark_registry_baseline_key": "triton_h200_07cf_dual_lane_v1",
+      "benchmark_registry_baseline_sha256": "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c",
+      "benchmark_registry_candidate_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
+      "benchmark_registry_key": "flash_kmeans_assign_dispatch_full_contract",
+      "benchmark_registry_shape_labels_sha256": "172741a45af34837224b4005e0b6ba45637a07c7a4cabc88ed85ec95670e6290",
+      "benchmark_registry_shape_ledger_sha256": "172741a45af34837224b4005e0b6ba45637a07c7a4cabc88ed85ec95670e6290",
+      "correctness_shape_count": 124,
+      "expected_routes": [
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_1d49_d128_forced_fallback_b5_n7296_k512_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_1d49_d224_highn_overlap_b5_n5632_k768_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_1d49_d288_low_n_heldout_b3_n1152_k2048_d288"
+        },
+        {
+          "selected_route": "d352_exactd_splitk_c95c_v2",
+          "shape": "adjacent_1d49_d352_request_highk_b2_n1024_k8192_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_1d49_d416_random_b4_n3840_k512_d416"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_1d49_d480_smallk_boundary_b2_n2816_k256_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_1d49_d48_lowk_boundary_b4_n3968_k256_d48"
+        },
+        {
+          "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+          "shape": "adjacent_3328_d112_highk_low_n_b2_n512_k8192_d112"
+        },
+        {
+          "selected_route": "paired_large_v15",
+          "shape": "adjacent_3328_d128_exact_guard_k_neighbor_b8_n8192_k512_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_3328_d224_tail_div_b3_n3840_k512_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_3328_d288_guard_overlap_b4_n8192_k256_d288"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_3328_d352_random_legal_b3_n2048_k768_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_3328_d416_highk_low_n_b1_n384_k8192_d416"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_3328_d480_min_boundary_b1_n128_k256_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_3328_d48_small_boundary_b1_n256_k256_d48"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_5600_d112_odd_tile_tail_b5_n2176_k512_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_5600_d128_fallback_neighbor_b8_n8320_k256_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_5600_d224_k512_overlap_b3_n3072_k512_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_5600_d288_mid_highk_b2_n1024_k2048_d288"
+        },
+        {
+          "selected_route": "d352_exactd_splitk_c95c_v2",
+          "shape": "adjacent_5600_d352_splitk_edge_b2_n768_k4096_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_5600_d416_smallk_boundary_b4_n2048_k256_d416"
+        },
+        {
+          "selected_route": "d480_splitk_k1024_eac2_v1",
+          "shape": "adjacent_5600_d480_random_b1_n1536_k1024_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_5600_d48_low_n_boundary_b3_n1536_k256_d48"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d112_tail_b5_n2944_k512_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_68cf_d128_forced_fallback_b7_n6016_k512_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d224_overlap_b3_n5120_k1024_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_68cf_d288_boundary_b2_n1920_k512_d288"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d352_tail_b3_n2816_k768_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d416_overlap_b2_n2304_k1024_d416"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d480_boundary_b4_n1664_k512_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_68cf_d48_boundary_b4_n2304_k512_d48"
+        },
+        {
+          "selected_route": "d112_f826_c829_full_bucket_weave_evolve_flash_kmeans_assign_a262_v1",
+          "shape": "adjacent_8f09_d112_small_highk_b1_n384_k4096_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_8f09_d128_fallback_neighbor_b4_n4480_k512_d128"
+        },
+        {
+          "selected_route": "d224_tmem_abi_repair_d17c_v4",
+          "shape": "adjacent_8f09_d224_low_n_boundary_b4_n1536_k256_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_8f09_d288_k768_overlap_b1_n2560_k768_d288"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_8f09_d352_smallk_large_n_b4_n4096_k256_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_8f09_d416_midk_tail_b3_n3456_k768_d416"
+        },
+        {
+          "selected_route": "d480_splitk_k1024_eac2_v1",
+          "shape": "adjacent_8f09_d480_highk_low_n_b2_n640_k4096_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_8f09_d48_medium_tail_b2_n1792_k512_d48"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_9ca0_d112_tail_div_b3_n3840_k768_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_9ca0_d128_exact_guard_neighbor_b8_n8064_k256_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_9ca0_d224_guard_overlap_b2_n4096_k256_d224"
+        },
+        {
+          "selected_route": "d288_parent_splitk_hybrid_20260629_v1",
+          "shape": "adjacent_9ca0_d288_highk_low_n_b1_n384_k4096_d288"
+        },
+        {
+          "selected_route": "d352_exactd_splitk_c95c_v2",
+          "shape": "adjacent_9ca0_d352_splitk_boundary_b1_n512_k8192_d352"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_9ca0_d416_splitk_min_b1_n1024_k4096_d416"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_9ca0_d480_splitd_large_n_b2_n4096_k512_d480"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_9ca0_d48_guard_boundary_b6_n12288_k512_d48"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
+          "shape": "adjacent_a2f8_d112_lowk_tail_b4_n3456_k256_d112"
+        },
+        {
+          "selected_route": "aligned_weave_v10_fallback",
+          "shape": "adjacent_a2f8_d128_odd_fallback_b6_n8576_k512_d128"
+        },
+        {
+          "selected_route": "gap_pad_to_supported_seed_v1",
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+        "post_d895_d176_b1_n512_k8192_d176",
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+      "flashlib_cake_kmeans.launch_dispatch_kernel_0192",
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+      "flashlib_cake_kmeans.launch_dispatch_kernel_0194",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0195",
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+      "flashlib_cake_kmeans.launch_dispatch_kernel_0203",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0204",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0205",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0206",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0207",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0208",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0209",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0210",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0211",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0212",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0213",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0214",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0215",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0216",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0217",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0218",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0219",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0220",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0221",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0222",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0223",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0224",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0225",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0226",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0227",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0228",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0229",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0230",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0231",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0232",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0233",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0234",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0235",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0236",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0237",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0238",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0239",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0240",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0241",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0242",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0243",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0244",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0245",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0246",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0247",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0248",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0249",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0250",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0251",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0252",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0253",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0254",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0255",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0256",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0257",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0258",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0259",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0260",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0261",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0262",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0263",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0264",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0265",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0266",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0267",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0268",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0269",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0270",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0271",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0272",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0273",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0274",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0275",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0276",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0277",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0278",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0279",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0280",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0281",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0282",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0283",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0284",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0285",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0286",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0287",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0288",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0289",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0290",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0291",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0292",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0293",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0294",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0295",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0296",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0297",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0298",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0299",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0300",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0301",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0302",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0303",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0304",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0305",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0306",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0307",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0308",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0309",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0310",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0311",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0312",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0313",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0314",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0315",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0316",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0317",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0318",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0319",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0320",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0321",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0322",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0323",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0324",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0325",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0326",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0327",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0328",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0329",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0330",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0331",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0332",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0333",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0334",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0335",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0336",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0337",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0338",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0339",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0340",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0341",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0342",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0343",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0344",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0345",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0346",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0347",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0348",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0349",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0350",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0351",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0352",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0353",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0354",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0355",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0356",
+      "flashlib_cake_kmeans.launch_dispatch_kernel_0357"
+    ],
+    "tensor_interop": "dlpack-zero-copy"
+  }
+}
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/tvm_ffi.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/tvm_ffi.py
new file mode 100644
index 00000000..8a639de1
--- /dev/null
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/tvm_ffi.py
@@ -0,0 +1,179 @@
+"""Optional Apache TVM FFI adapters for the exported kernel package."""
+
+from __future__ import annotations
+
+import contextlib
+import importlib
+import json
+from pathlib import Path
+from typing import Any
+
+from .kernels import get_kernel
+
+
+_PACKAGE = 'flashlib_cake_kmeans'
+_KERNEL_ALIASES = ['dispatch_kernel_0000', 'dispatch_kernel_0001', 'dispatch_kernel_0002', 'dispatch_kernel_0003', 'dispatch_kernel_0004', 'dispatch_kernel_0005', 'dispatch_kernel_0006', 'dispatch_kernel_0007', 'dispatch_kernel_0008', 'dispatch_kernel_0009', 'dispatch_kernel_0010', 'dispatch_kernel_0011', 'dispatch_kernel_0012', 'dispatch_kernel_0013', 'dispatch_kernel_0014', 'dispatch_kernel_0015', 'dispatch_kernel_0016', 'dispatch_kernel_0017', 'dispatch_kernel_0018', 'dispatch_kernel_0019', 'dispatch_kernel_0020', 'dispatch_kernel_0021', 'dispatch_kernel_0022', 'dispatch_kernel_0023', 'dispatch_kernel_0024', 'dispatch_kernel_0025', 'dispatch_kernel_0026', 'dispatch_kernel_0027', 'dispatch_kernel_0028', 'dispatch_kernel_0029', 'dispatch_kernel_0030', 'dispatch_kernel_0031', 'dispatch_kernel_0032', 'dispatch_kernel_0033', 'dispatch_kernel_0034', 'dispatch_kernel_0035', 'dispatch_kernel_0036', 'dispatch_kernel_0037', 'dispatch_kernel_0038', 'dispatch_kernel_0039', 'dispatch_kernel_0040', 'dispatch_kernel_0041', 'dispatch_kernel_0042', 'dispatch_kernel_0043', 'dispatch_kernel_0044', 'dispatch_kernel_0045', 'dispatch_kernel_0046', 'dispatch_kernel_0047', 'dispatch_kernel_0048', 'dispatch_kernel_0049', 'dispatch_kernel_0050', 'dispatch_kernel_0051', 'dispatch_kernel_0052', 'dispatch_kernel_0053', 'dispatch_kernel_0054', 'dispatch_kernel_0055', 'dispatch_kernel_0056', 'dispatch_kernel_0057', 'dispatch_kernel_0058', 'dispatch_kernel_0059', 'dispatch_kernel_0060', 'dispatch_kernel_0061', 'dispatch_kernel_0062', 'dispatch_kernel_0063', 'dispatch_kernel_0064', 'dispatch_kernel_0065', 'dispatch_kernel_0066', 'dispatch_kernel_0067', 'dispatch_kernel_0068', 'dispatch_kernel_0069', 'dispatch_kernel_0070', 'dispatch_kernel_0071', 'dispatch_kernel_0072', 'dispatch_kernel_0073', 'dispatch_kernel_0074', 'dispatch_kernel_0075', 'dispatch_kernel_0076', 'dispatch_kernel_0077', 'dispatch_kernel_0078', 'dispatch_kernel_0079', 'dispatch_kernel_0080', 'dispatch_kernel_0081', 'dispatch_kernel_0082', 'dispatch_kernel_0083', 'dispatch_kernel_0084', 'dispatch_kernel_0085', 'dispatch_kernel_0086', 'dispatch_kernel_0087', 'dispatch_kernel_0088', 'dispatch_kernel_0089', 'dispatch_kernel_0090', 'dispatch_kernel_0091', 'dispatch_kernel_0092', 'dispatch_kernel_0093', 'dispatch_kernel_0094', 'dispatch_kernel_0095', 'dispatch_kernel_0096', 'dispatch_kernel_0097', 'dispatch_kernel_0098', 'dispatch_kernel_0099', 'dispatch_kernel_0100', 'dispatch_kernel_0101', 'dispatch_kernel_0102', 'dispatch_kernel_0103', 'dispatch_kernel_0104', 'dispatch_kernel_0105', 'dispatch_kernel_0106', 'dispatch_kernel_0107', 'dispatch_kernel_0108', 'dispatch_kernel_0109', 'dispatch_kernel_0110', 'dispatch_kernel_0111', 'dispatch_kernel_0112', 'dispatch_kernel_0113', 'dispatch_kernel_0114', 'dispatch_kernel_0115', 'dispatch_kernel_0116', 'dispatch_kernel_0117', 'dispatch_kernel_0118', 'dispatch_kernel_0119', 'dispatch_kernel_0120', 'dispatch_kernel_0121', 'dispatch_kernel_0122', 'dispatch_kernel_0123', 'dispatch_kernel_0124', 'dispatch_kernel_0125', 'dispatch_kernel_0126', 'dispatch_kernel_0127', 'dispatch_kernel_0128', 'dispatch_kernel_0129', 'dispatch_kernel_0130', 'dispatch_kernel_0131', 'dispatch_kernel_0132', 'dispatch_kernel_0133', 'dispatch_kernel_0134', 'dispatch_kernel_0135', 'dispatch_kernel_0136', 'dispatch_kernel_0137', 'dispatch_kernel_0138', 'dispatch_kernel_0139', 'dispatch_kernel_0140', 'dispatch_kernel_0141', 'dispatch_kernel_0142', 'dispatch_kernel_0143', 'dispatch_kernel_0144', 'dispatch_kernel_0145', 'dispatch_kernel_0146', 'dispatch_kernel_0147', 'dispatch_kernel_0148', 'dispatch_kernel_0149', 'dispatch_kernel_0150', 'dispatch_kernel_0151', 'dispatch_kernel_0152', 'dispatch_kernel_0153', 'dispatch_kernel_0154', 'dispatch_kernel_0155', 'dispatch_kernel_0156', 'dispatch_kernel_0157', 'dispatch_kernel_0158', 'dispatch_kernel_0159', 'dispatch_kernel_0160', 'dispatch_kernel_0161', 'dispatch_kernel_0162', 'dispatch_kernel_0163', 'dispatch_kernel_0164', 'dispatch_kernel_0165', 'dispatch_kernel_0166', 'dispatch_kernel_0167', 'dispatch_kernel_0168', 'dispatch_kernel_0169', 'dispatch_kernel_0170', 'dispatch_kernel_0171', 'dispatch_kernel_0172', 'dispatch_kernel_0173', 'dispatch_kernel_0174', 'dispatch_kernel_0175', 'dispatch_kernel_0176', 'dispatch_kernel_0177', 'dispatch_kernel_0178', 'dispatch_kernel_0179', 'dispatch_kernel_0180', 'dispatch_kernel_0181', 'dispatch_kernel_0182', 'dispatch_kernel_0183', 'dispatch_kernel_0184', 'dispatch_kernel_0185', 'dispatch_kernel_0186', 'dispatch_kernel_0187', 'dispatch_kernel_0188', 'dispatch_kernel_0189', 'dispatch_kernel_0190', 'dispatch_kernel_0191', 'dispatch_kernel_0192', 'dispatch_kernel_0193', 'dispatch_kernel_0194', 'dispatch_kernel_0195', 'dispatch_kernel_0196', 'dispatch_kernel_0197', 'dispatch_kernel_0198', 'dispatch_kernel_0199', 'dispatch_kernel_0200', 'dispatch_kernel_0201', 'dispatch_kernel_0202', 'dispatch_kernel_0203', 'dispatch_kernel_0204', 'dispatch_kernel_0205', 'dispatch_kernel_0206', 'dispatch_kernel_0207', 'dispatch_kernel_0208', 'dispatch_kernel_0209', 'dispatch_kernel_0210', 'dispatch_kernel_0211', 'dispatch_kernel_0212', 'dispatch_kernel_0213', 'dispatch_kernel_0214', 'dispatch_kernel_0215', 'dispatch_kernel_0216', 'dispatch_kernel_0217', 'dispatch_kernel_0218', 'dispatch_kernel_0219', 'dispatch_kernel_0220', 'dispatch_kernel_0221', 'dispatch_kernel_0222', 'dispatch_kernel_0223', 'dispatch_kernel_0224', 'dispatch_kernel_0225', 'dispatch_kernel_0226', 'dispatch_kernel_0227', 'dispatch_kernel_0228', 'dispatch_kernel_0229', 'dispatch_kernel_0230', 'dispatch_kernel_0231', 'dispatch_kernel_0232', 'dispatch_kernel_0233', 'dispatch_kernel_0234', 'dispatch_kernel_0235', 'dispatch_kernel_0236', 'dispatch_kernel_0237', 'dispatch_kernel_0238', 'dispatch_kernel_0239', 'dispatch_kernel_0240', 'dispatch_kernel_0241', 'dispatch_kernel_0242', 'dispatch_kernel_0243', 'dispatch_kernel_0244', 'dispatch_kernel_0245', 'dispatch_kernel_0246', 'dispatch_kernel_0247', 'dispatch_kernel_0248', 'dispatch_kernel_0249', 'dispatch_kernel_0250', 'dispatch_kernel_0251', 'dispatch_kernel_0252', 'dispatch_kernel_0253', 'dispatch_kernel_0254', 'dispatch_kernel_0255', 'dispatch_kernel_0256', 'dispatch_kernel_0257', 'dispatch_kernel_0258', 'dispatch_kernel_0259', 'dispatch_kernel_0260', 'dispatch_kernel_0261', 'dispatch_kernel_0262', 'dispatch_kernel_0263', 'dispatch_kernel_0264', 'dispatch_kernel_0265', 'dispatch_kernel_0266', 'dispatch_kernel_0267', 'dispatch_kernel_0268', 'dispatch_kernel_0269', 'dispatch_kernel_0270', 'dispatch_kernel_0271', 'dispatch_kernel_0272', 'dispatch_kernel_0273', 'dispatch_kernel_0274', 'dispatch_kernel_0275', 'dispatch_kernel_0276', 'dispatch_kernel_0277', 'dispatch_kernel_0278', 'dispatch_kernel_0279', 'dispatch_kernel_0280', 'dispatch_kernel_0281', 'dispatch_kernel_0282', 'dispatch_kernel_0283', 'dispatch_kernel_0284', 'dispatch_kernel_0285', 'dispatch_kernel_0286', 'dispatch_kernel_0287', 'dispatch_kernel_0288', 'dispatch_kernel_0289', 'dispatch_kernel_0290', 'dispatch_kernel_0291', 'dispatch_kernel_0292', 'dispatch_kernel_0293', 'dispatch_kernel_0294', 'dispatch_kernel_0295', 'dispatch_kernel_0296', 'dispatch_kernel_0297', 'dispatch_kernel_0298', 'dispatch_kernel_0299', 'dispatch_kernel_0300', 'dispatch_kernel_0301', 'dispatch_kernel_0302', 'dispatch_kernel_0303', 'dispatch_kernel_0304', 'dispatch_kernel_0305', 'dispatch_kernel_0306', 'dispatch_kernel_0307', 'dispatch_kernel_0308', 'dispatch_kernel_0309', 'dispatch_kernel_0310', 'dispatch_kernel_0311', 'dispatch_kernel_0312', 'dispatch_kernel_0313', 'dispatch_kernel_0314', 'dispatch_kernel_0315', 'dispatch_kernel_0316', 'dispatch_kernel_0317', 'dispatch_kernel_0318', 'dispatch_kernel_0319', 'dispatch_kernel_0320', 'dispatch_kernel_0321', 'dispatch_kernel_0322', 'dispatch_kernel_0323', 'dispatch_kernel_0324', 'dispatch_kernel_0325', 'dispatch_kernel_0326', 'dispatch_kernel_0327', 'dispatch_kernel_0328', 'dispatch_kernel_0329', 'dispatch_kernel_0330', 'dispatch_kernel_0331', 'dispatch_kernel_0332', 'dispatch_kernel_0333', 'dispatch_kernel_0334', 'dispatch_kernel_0335', 'dispatch_kernel_0336', 'dispatch_kernel_0337', 'dispatch_kernel_0338', 'dispatch_kernel_0339', 'dispatch_kernel_0340', 'dispatch_kernel_0341', 'dispatch_kernel_0342', 'dispatch_kernel_0343', 'dispatch_kernel_0344', 'dispatch_kernel_0345', 'dispatch_kernel_0346', 'dispatch_kernel_0347', 'dispatch_kernel_0348', 'dispatch_kernel_0349', 'dispatch_kernel_0350', 'dispatch_kernel_0351', 'dispatch_kernel_0352', 'dispatch_kernel_0353', 'dispatch_kernel_0354', 'dispatch_kernel_0355', 'dispatch_kernel_0356', 'dispatch_kernel_0357']
+_REGISTERED: dict[str, tuple[str, ...]] = {}
+
+
+class _RawCUDAStream:
+    def __init__(self, handle: int):
+        self.cuda_stream = int(handle)
+
+
+def _manifest() -> dict[str, Any]:
+    return json.loads(Path(__file__).with_name("manifest.json").read_text(encoding="utf-8"))
+
+
+def _planned_public_exports() -> dict[str, str] | None:
+    export_plan = _manifest().get("export_plan", {})
+    if "tvm_ffi_exports" in export_plan:
+        return dict(export_plan["tvm_ffi_exports"])
+    if "package_exports" in export_plan:
+        return dict(export_plan["package_exports"])
+    return None
+
+
+def _public_export_names() -> tuple[str, ...]:
+    planned = _planned_public_exports()
+    if planned is not None:
+        return tuple(planned)
+    package = importlib.import_module(__package__)
+    excluded = {
+        "KERNELS",
+        "ExportedKernel",
+        "get_kernel",
+        "register_tvm_ffi",
+        "tvm_ffi_function_names",
+        *(_KERNEL_ALIASES),
+        *(f"launch_{name}" for name in _KERNEL_ALIASES),
+    }
+    return tuple(
+        name
+        for name in getattr(package, "__all__", ())
+        if name not in excluded and callable(getattr(package, name, None))
+    )
+
+
+def tvm_ffi_function_names(namespace: str | None = None) -> tuple[str, ...]:
+    """Return the deterministic TVM FFI global names this package registers."""
+
+    prefix = namespace or _PACKAGE
+    public_names = [f"{prefix}.{name}" for name in _public_export_names()]
+    kernel_names = [f"{prefix}.launch_{name}" for name in _KERNEL_ALIASES]
+    return tuple(public_names + kernel_names)
+
+
+def _tensor_stream(arg: Any, tvm_ffi: Any) -> tuple[int, int] | None:
+    if not isinstance(arg, tvm_ffi.Tensor):
+        return None
+    device = arg.device
+    device_type = getattr(device, "type", None) or str(device).split(":", 1)[0]
+    if str(device_type) != "cuda":
+        return None
+    device_id = int(getattr(device, "index", 0))
+    return device_id, int(tvm_ffi.get_raw_stream(device))
+
+
+def _convert_arg(arg: Any, tvm_ffi: Any) -> Any:
+    if not isinstance(arg, tvm_ffi.Tensor):
+        return arg
+    import torch
+
+    return torch.from_dlpack(arg)
+
+
+def _torch_stream_context(stream: tuple[int, int] | None):
+    if stream is None:
+        return contextlib.nullcontext()
+    import torch
+
+    device_id, handle = stream
+    return torch.cuda.stream(torch.cuda.ExternalStream(handle, device=device_id))
+
+
+def _semantic_target(public_name: str):
+    planned = _planned_public_exports()
+    target = None if planned is None else planned.get(public_name)
+    if target is None:
+        return getattr(importlib.import_module(__package__), public_name)
+    module_name, separator, attr = target.partition(":")
+    if not separator:
+        raise ValueError(f"invalid package export target: {target!r}")
+    module = importlib.import_module(module_name, package=__package__)
+    return getattr(module, attr)
+
+
+def _semantic_wrapper(public_name: str, tvm_ffi: Any):
+    function = _semantic_target(public_name)
+
+    def call(*args):
+        stream = next((item for arg in args if (item := _tensor_stream(arg, tvm_ffi)) is not None), None)
+        converted = tuple(_convert_arg(arg, tvm_ffi) for arg in args)
+        with _torch_stream_context(stream):
+            return function(*converted)
+
+    return call
+
+
+def _kernel_wrapper(alias: str, tvm_ffi: Any):
+    kernel = get_kernel(alias)
+    parameter_count = len(kernel.parameters)
+
+    def call(*args):
+        expected = parameter_count + 7
+        if len(args) != expected:
+            raise TypeError(
+                f"{alias} TVM FFI launch expects {expected} positional arguments "
+                f"({parameter_count} kernel + grid xyz + block xyz + shared_mem), got {len(args)}"
+            )
+        kernel_args = args[:parameter_count]
+        config = tuple(int(value) for value in args[parameter_count:])
+        grid = config[:3]
+        block = config[3:6]
+        shared_mem = config[6]
+        stream = next(
+            (item for arg in kernel_args if (item := _tensor_stream(arg, tvm_ffi)) is not None),
+            None,
+        )
+        converted = tuple(_convert_arg(arg, tvm_ffi) for arg in kernel_args)
+        return kernel.launch(
+            *converted,
+            grid=grid,
+            block=block,
+            shared_mem=shared_mem,
+            stream=_RawCUDAStream(stream[1]) if stream is not None else None,
+        )
+
+    return call
+
+
+def register_tvm_ffi(namespace: str | None = None, *, override: bool = False) -> tuple[str, ...]:
+    """Register semantic and low-level launch functions in Apache TVM FFI."""
+
+    try:
+        import tvm_ffi
+    except ImportError as exc:
+        raise ImportError(
+            'TVM FFI support requires `python -m pip install -e ".[tvm-ffi]"`'
+        ) from exc
+
+    prefix = namespace or _PACKAGE
+    if prefix in _REGISTERED and not override:
+        return _REGISTERED[prefix]
+
+    registered: list[str] = []
+    for public_name in _public_export_names():
+        name = f"{prefix}.{public_name}"
+        tvm_ffi.register_global_func(
+            name, _semantic_wrapper(public_name, tvm_ffi), override=override
+        )
+        registered.append(name)
+    for alias in _KERNEL_ALIASES:
+        name = f"{prefix}.launch_{alias}"
+        tvm_ffi.register_global_func(name, _kernel_wrapper(alias, tvm_ffi), override=override)
+        registered.append(name)
+    result = tuple(registered)
+    _REGISTERED[prefix] = result
+    return result
+
diff --git a/cake_exports/kmeans/tests/test_benchmark_harness.py b/cake_exports/kmeans/tests/test_benchmark_harness.py
new file mode 100644
index 00000000..76ca7724
--- /dev/null
+++ b/cake_exports/kmeans/tests/test_benchmark_harness.py
@@ -0,0 +1,64 @@
+from __future__ import annotations
+
+import json
+import os
+import subprocess
+import sys
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+
+
+def test_benchmark_harness_metadata_mode(tmp_path):
+    output = tmp_path / "benchmark_metadata.json"
+    env = os.environ.copy()
+    env["PYTHONPATH"] = str(ROOT / "src")
+    result = subprocess.run(
+        [
+            sys.executable,
+            "benchmarks/benchmark_exported_kernels.py",
+            "--metadata-only",
+            "--json",
+            str(output),
+        ],
+        cwd=ROOT,
+        env=env,
+        check=False,
+        text=True,
+        capture_output=True,
+    )
+
+    assert result.returncode == 0, result.stdout + result.stderr
+    payload = json.loads(output.read_text(encoding="utf-8"))
+    assert payload["benchmark"] == "exported_kernel_compile"
+    assert payload["metadata_only"] is True
+    assert payload["kernels"]
+    assert payload["summary"]["kernel_count"] == len(payload["kernels"])
+
+
+def test_shape_benchmark_metadata_mode(tmp_path):
+    output = tmp_path / "shape_benchmark_metadata.json"
+    env = os.environ.copy()
+    env["PYTHONPATH"] = str(ROOT / "src")
+    result = subprocess.run(
+        [
+            sys.executable,
+            "benchmarks/benchmark_shapes.py",
+            "--metadata-only",
+            "--json",
+            str(output),
+        ],
+        cwd=ROOT,
+        env=env,
+        check=False,
+        text=True,
+        capture_output=True,
+    )
+
+    assert result.returncode == 0, result.stdout + result.stderr
+    payload = json.loads(output.read_text(encoding="utf-8"))
+    assert payload["benchmark"] == "exported_kernel_shapes"
+    assert payload["metadata_only"] is True
+    assert payload["timing_backend_requested"] == "cupti"
+
diff --git a/cake_exports/kmeans/tests/test_correctness.py b/cake_exports/kmeans/tests/test_correctness.py
new file mode 100644
index 00000000..23b5bfed
--- /dev/null
+++ b/cake_exports/kmeans/tests/test_correctness.py
@@ -0,0 +1,255 @@
+from __future__ import annotations
+
+import importlib.util
+import sys
+from pathlib import Path
+
+import pytest
+
+ROOT = Path(__file__).resolve().parents[1]
+BENCHMARKS = ROOT / "benchmarks"
+if str(BENCHMARKS) not in sys.path:
+    sys.path.insert(0, str(BENCHMARKS))
+
+
+def _benchmark_module():
+    spec = importlib.util.spec_from_file_location("kmeans_benchmark", BENCHMARKS / "benchmark.py")
+    assert spec is not None and spec.loader is not None
+    module = importlib.util.module_from_spec(spec)
+    spec.loader.exec_module(module)
+    return module
+
+
+BENCHMARK = _benchmark_module()
+
+
+def test_kmeans_runtime_api_is_exported():
+    from flashlib_cake_kmeans import FlashKMeansAssignRuntime, init
+
+    assert FlashKMeansAssignRuntime is not None
+    assert callable(init)
+
+
+@pytest.mark.export_validation_shape
+@pytest.mark.parametrize("row_index", range(len(BENCHMARK.FLASH_KMEANS_REGISTRY_SHAPES)))
+def test_kmeans_matches_reference(row_index: int):
+    torch = pytest.importorskip("torch")
+    if not torch.cuda.is_available():
+        pytest.skip("CUDA GPU required for exported-kernel correctness")
+    row = BENCHMARK.FLASH_KMEANS_REGISTRY_SHAPES[row_index]
+    from flashlib_cake_kmeans import init
+
+    runtime = init()
+    baseline_adapter = BENCHMARK.TritonH20007cfRawAdapter(
+        device_index=runtime.device_index,
+        arch=runtime.arch,
+    )
+    try:
+        result = BENCHMARK._run_shape(
+            row,
+            runtime=runtime,
+            baseline_adapter=baseline_adapter,
+            arch=None,
+            correctness=True,
+            benchmark=False,
+            reference_chunk_rows=128,
+            measurement_session_id="standalone-correctness-test",
+            measurement_order_seed=BENCHMARK.DEFAULT_MEASUREMENT_ORDER_SEED,
+        )
+    finally:
+        runtime.clear()
+        baseline_adapter.clear()
+    assert result["route_matches_expected"], result
+    assert result["correct"], result
+
+
+@pytest.mark.gpu
+def test_kmeans_runtime_reuses_shape_after_intervening_shape():
+    """Exercise A -> B -> fresh-pointer A on one live multi-shape runtime."""
+
+    torch = pytest.importorskip("torch")
+    if not torch.cuda.is_available():
+        pytest.skip("CUDA GPU required for exported-kernel correctness")
+    from flashlib_cake_kmeans import init
+
+    rows = {row["label"]: row for row in BENCHMARK.FLASH_KMEANS_SHAPES}
+    shape_a = rows["boundary_b1_n128_k256_d128"]
+    shape_b = rows["small_b1_n256_k256_d128"]
+    runtime = init()
+
+    def run(row, *, variant: int):
+        x, centroids = BENCHMARK._make_inputs(row, variant=variant)
+        out = torch.empty((int(row["B"]), int(row["N"])), dtype=torch.int32, device=x.device)
+        result, info = runtime.compute(
+            x,
+            centroids,
+            out=out,
+            return_info=True,
+        )
+        reference = BENCHMARK._reference_assign(x, centroids, chunk_rows=128)
+        torch.cuda.synchronize()
+        correctness = BENCHMARK._assignment_correctness(result, reference, x, centroids)
+        assert correctness["correct"], correctness
+        assert info["norm_mode"] == "fused_bf16_pair_row_norm:x_sq,c_sq"
+        assert info["norm_compute_fields"] == ["x_sq", "c_sq"]
+        return x, info
+
+    try:
+        first_x, first_info = run(shape_a, variant=101)
+        _, middle_info = run(shape_b, variant=201)
+        fresh_x, revisit_info = run(shape_a, variant=102)
+        assert first_x.data_ptr() != fresh_x.data_ptr()
+        assert first_info["runtime_cache_hit"] is False
+        assert middle_info["runtime_cache_hit"] is False
+        assert revisit_info["runtime_cache_hit"] is True
+        assert runtime.cache_info() == {
+            "size": 2,
+            "hits": 1,
+            "misses": 2,
+            "max_cached_shapes": None,
+        }
+    finally:
+        runtime.clear()
+
+
+@pytest.mark.gpu
+def test_internal_fused_norms_and_explicit_precomputed_norms_are_correct():
+    torch = pytest.importorskip("torch")
+    if not torch.cuda.is_available():
+        pytest.skip("CUDA GPU required for exported-kernel correctness")
+    from flashlib_cake_kmeans import init
+
+    rows = {row["label"]: row for row in BENCHMARK.FLASH_KMEANS_SHAPES}
+    row = rows["boundary_b1_n128_k256_d128"]
+    x, centroids = BENCHMARK._make_inputs(row, variant=250)
+    x_sq = (x.float() ** 2).sum(-1).contiguous()
+    c_sq = (centroids.float() ** 2).sum(-1).contiguous()
+    internal_out = torch.empty((1, 128), dtype=torch.int32, device=x.device)
+    explicit_out = torch.empty_like(internal_out)
+    x_explicit_out = torch.empty_like(internal_out)
+    c_explicit_out = torch.empty_like(internal_out)
+    runtime = init()
+    try:
+        internal_result, internal_info = runtime.compute(
+            x,
+            centroids,
+            out=internal_out,
+            return_info=True,
+        )
+        explicit_result, explicit_info = runtime.compute(
+            x,
+            centroids,
+            out=explicit_out,
+            x_sq=x_sq,
+            c_sq=c_sq,
+            return_info=True,
+        )
+        x_explicit_result, x_explicit_info = runtime.compute(
+            x,
+            centroids,
+            out=x_explicit_out,
+            x_sq=x_sq,
+            return_info=True,
+        )
+        c_explicit_result, c_explicit_info = runtime.compute(
+            x,
+            centroids,
+            out=c_explicit_out,
+            c_sq=c_sq,
+            return_info=True,
+        )
+        reference = BENCHMARK._reference_assign(x, centroids, chunk_rows=128)
+        torch.cuda.synchronize()
+        for result in (
+            internal_result,
+            explicit_result,
+            x_explicit_result,
+            c_explicit_result,
+        ):
+            correctness = BENCHMARK._assignment_correctness(
+                result,
+                reference,
+                x,
+                centroids,
+            )
+            assert correctness["correct"], correctness
+        assert internal_info["norm_mode"] == "fused_bf16_pair_row_norm:x_sq,c_sq"
+        assert internal_info["norm_compute_fields"] == ["x_sq", "c_sq"]
+        assert explicit_info["norm_mode"] == "explicit_precomputed"
+        assert explicit_info["norm_compute_fields"] == []
+        assert x_explicit_info["norm_mode"] == "fused_bf16_pair_row_norm:c_sq"
+        assert x_explicit_info["norm_compute_fields"] == ["c_sq"]
+        assert c_explicit_info["norm_mode"] == "fused_bf16_pair_row_norm:x_sq"
+        assert c_explicit_info["norm_compute_fields"] == ["x_sq"]
+        assert explicit_info["runtime_cache_hit"] is False
+        assert x_explicit_info["runtime_cache_hit"] is False
+        assert c_explicit_info["runtime_cache_hit"] is False
+        assert runtime.cache_info()["size"] == 4
+    finally:
+        runtime.clear()
+
+
+@pytest.mark.gpu
+def test_kmeans_runtime_isolates_tma_and_workspace_across_streams():
+    torch = pytest.importorskip("torch")
+    if not torch.cuda.is_available():
+        pytest.skip("CUDA GPU required for exported-kernel correctness")
+    from flashlib_cake_kmeans import init
+
+    rows = {row["label"]: row for row in BENCHMARK.FLASH_KMEANS_SHAPES}
+    row = rows["boundary_b1_n128_k256_d128"]
+    stream_a = torch.cuda.Stream()
+    stream_b = torch.cuda.Stream()
+    runtime = init()
+
+    def inputs(variant: int):
+        x, centroids = BENCHMARK._make_inputs(row, variant=variant)
+        return (
+            x,
+            centroids,
+            (x.float() ** 2).sum(-1).contiguous(),
+            (centroids.float() ** 2).sum(-1).contiguous(),
+            torch.empty((int(row["B"]), int(row["N"])), dtype=torch.int32, device=x.device),
+        )
+
+    values_a = inputs(301)
+    values_b = inputs(302)
+    try:
+        for stream, values in ((stream_a, values_a), (stream_b, values_b)):
+            x, centroids, x_sq, c_sq, out = values
+            with torch.cuda.stream(stream):
+                runtime.compute(
+                    x,
+                    centroids,
+                    x_sq=x_sq,
+                    c_sq=c_sq,
+                    out=out,
+                    stream=stream,
+                )
+        stream_a.synchronize()
+        stream_b.synchronize()
+
+        outputs = []
+        for stream, values in ((stream_a, values_a), (stream_b, values_b)):
+            x, centroids, x_sq, c_sq, out = values
+            with torch.cuda.stream(stream):
+                outputs.append(
+                    runtime.compute(
+                        x,
+                        centroids,
+                        x_sq=x_sq,
+                        c_sq=c_sq,
+                        out=out,
+                        stream=stream,
+                    )
+                )
+        stream_a.synchronize()
+        stream_b.synchronize()
+        for output, values in zip(outputs, (values_a, values_b), strict=True):
+            x, centroids, *_ = values
+            reference = BENCHMARK._reference_assign(x, centroids, chunk_rows=128)
+            correctness = BENCHMARK._assignment_correctness(output, reference, x, centroids)
+            assert correctness["correct"], correctness
+        assert runtime.cache_info()["size"] == 2
+    finally:
+        runtime.clear()
diff --git a/cake_exports/kmeans/tests/test_exported_kernels.py b/cake_exports/kmeans/tests/test_exported_kernels.py
new file mode 100644
index 00000000..093dc9cb
--- /dev/null
+++ b/cake_exports/kmeans/tests/test_exported_kernels.py
@@ -0,0 +1,165 @@
+from __future__ import annotations
+
+import importlib
+import json
+import sys
+import types
+from pathlib import Path
+
+import pytest
+
+
+ROOT = Path(__file__).resolve().parents[1]
+SRC = ROOT / "src"
+if str(SRC) not in sys.path:
+    sys.path.insert(0, str(SRC))
+
+PACKAGE_NAME = 'flashlib_cake_kmeans'
+
+
+def _manifest() -> dict:
+    return json.loads((SRC / PACKAGE_NAME / "manifest.json").read_text(encoding="utf-8"))
+
+
+def test_manifest_matches_package_exports():
+    pkg = importlib.import_module(PACKAGE_NAME)
+    manifest = _manifest()
+    names = [entry["name"] for entry in manifest["kernels"]]
+
+    assert names
+    assert set(pkg.KERNELS) == set(names)
+    assert manifest["package"] == PACKAGE_NAME
+    package_exports = manifest.get("export_plan", {}).get("package_exports", {})
+    for public_name in package_exports:
+        assert hasattr(pkg, public_name), public_name
+        assert public_name in pkg.__all__, public_name
+
+    if "export_plan" in manifest:
+        entrypoints = manifest["export_plan"].get("entrypoints", {})
+        assert set(entrypoints) == {
+            "python_interface",
+            "correctness_test",
+            "performance_benchmark",
+        }
+        for path in entrypoints.values():
+            assert (ROOT / path).is_file(), path
+
+
+def test_manifest_sources_exist_and_contain_symbols():
+    manifest = _manifest()
+    package_dir = SRC / PACKAGE_NAME
+
+    for entry in manifest["kernels"]:
+        source_path = package_dir / entry["source"]
+        assert source_path.is_file(), entry["source"]
+        source = source_path.read_text(encoding="utf-8")
+        assert entry["symbol"] in source
+        assert entry["parameters"]
+
+
+def test_package_import_and_source_text_do_not_require_cuda_runtime():
+    pkg = importlib.import_module(PACKAGE_NAME)
+
+    for name, kernel in pkg.KERNELS.items():
+        assert kernel.source_text().startswith("typedef "), name
+        assert kernel.parameters
+
+
+def test_exported_repo_docs_and_benchmarks_exist():
+    assert (ROOT / "README.md").is_file()
+    assert (ROOT / "RESULTS.md").is_file()
+    assert (ROOT / "benchmarks" / "benchmark_exported_kernels.py").is_file()
+    assert (ROOT / "benchmarks" / "benchmark_shapes.py").is_file()
+    assert (ROOT / "benchmarks" / "workload.py").is_file()
+    assert (SRC / PACKAGE_NAME / "tvm_ffi.py").is_file()
+    pyproject = (ROOT / "pyproject.toml").read_text(encoding="utf-8")
+    assert 'cake-std==0.1.13.dev20260704+g7b8dbc8' in pyproject
+
+
+def test_tvm_ffi_adapter_registers_low_level_functions_without_import_time_dependency(monkeypatch):
+    pkg = importlib.import_module(PACKAGE_NAME)
+    registrations = {}
+
+    class FakeTensor:
+        pass
+
+    def register_global_func(name, function, *, override=False):
+        assert override is False
+        registrations[name] = function
+
+    fake_tvm_ffi = types.SimpleNamespace(
+        Tensor=FakeTensor,
+        register_global_func=register_global_func,
+        get_raw_stream=lambda device: 0,
+    )
+    monkeypatch.setitem(sys.modules, "tvm_ffi", fake_tvm_ffi)
+
+    expected = pkg.tvm_ffi_function_names("export_test")
+    registered = pkg.register_tvm_ffi("export_test")
+    assert registered == expected
+    assert set(registrations) == set(expected)
+    assert registered == pkg.register_tvm_ffi("export_test")
+    assert len(registrations) == len(expected)
+
+
+def test_benchmark_runtime_requires_cupti_without_event_or_wall_clock_fallback():
+    source = (SRC / PACKAGE_NAME / "_benchmark.py").read_text(encoding="utf-8")
+    assert "activity_register_callbacks" in source
+    assert "torch.cuda.Event" not in source
+    assert "perf_counter" not in source
+    assert "active_union_times_ms" in source
+    assert "activity_counts" in source
+    assert "launch_activity_counts" in source
+    assert "kernel_activity_counts" in source
+    assert "submission_times_ms" in source
+    assert "synchronized_e2e_times_ms" in source
+    assert "cold_first_call_host_enqueue_ms" in source
+    assert "cold_first_call_synchronized_e2e_ms" in source
+    helper = source.split("def _complete_l2_flush_before_bracket", 1)[1].split(
+        "def _correlate", 1
+    )[0]
+    assert helper.index("flusher.flush()") < helper.index("synchronize()")
+    measured_loop = source.split("for _ in range(bench_iters):", 1)[1]
+    assert measured_loop.index("_complete_l2_flush_before_bracket") < measured_loop.index(
+        "start = cupti.get_timestamp()"
+    )
+
+
+def test_benchmark_runtime_preserves_exact_activity_diagnostics():
+    benchmark = importlib.import_module(f"{PACKAGE_NAME}._benchmark")
+    timing = benchmark._correlate(
+        [(0, 100, 10_000)],
+        [(10, 11, 1), (20, 21, 2)],
+        [(1_000, 4_000, 1), (2_000, 5_000, 2)],
+    )
+    assert timing.gpu_span_ms == [0.004]
+    assert timing.kernel_sum_ms == [0.006]
+    assert timing.active_union_ms == [0.004]
+    assert timing.inter_kernel_gap_ms == [0.0]
+    assert timing.activity_count == [2]
+    assert timing.launch_activity_count == [2]
+    assert timing.kernel_activity_count == [2]
+    with pytest.raises(ValueError, match="must be 'cupti'"):
+        benchmark.BenchResult(times_ms=[1.0], backend="cuda_event")
+
+
+def test_runtime_has_content_cache_and_launch_context():
+    source = (SRC / PACKAGE_NAME / "_runtime.py").read_text(encoding="utf-8")
+    assert "def launch_context" in source
+    assert "def load_cached_kernel" in source
+    assert "_CUBIN_CACHE" in source
+    assert "_MODULE_CACHE" in source
+    assert "_KERNEL_CACHE" in source
+    kernels_source = (SRC / PACKAGE_NAME / "kernels.py").read_text(encoding="utf-8")
+    assert "self._arg_types = tuple" in kernels_source
+    assert "self._default_block" in kernels_source
+
+
+def test_launch_argument_count_is_checked_before_compilation():
+    pkg = importlib.import_module(PACKAGE_NAME)
+    kernel = next(iter(pkg.KERNELS.values()))
+    bad_args = [object()] * (len(kernel.parameters) + 1)
+
+    with pytest.raises(TypeError, match="expects"):
+        kernel.launch(*bad_args, grid=(1, 1, 1))
+

From fd8499aded3ef43d505f08b09e820f21b295e322 Mon Sep 17 00:00:00 2001
From: Yingyi Huang <yingyihuang2000@outlook.com>
Date: Wed, 8 Jul 2026 21:31:05 -0700
Subject: [PATCH 2/2] Refresh KMeans export with the plan-runtime graph wiring

Re-exported from Cake main 42070e96d, which consumes the KMeans
plan-runtime wiring: per-signature LaunchPlans and CUDA-graph hot-path
capture (new _launch_plan.py exports), plus the synced registry baseline
identity. Validated on 4x GB200: 124/124 correctness and route parity,
hot public E2E vs the exact-07cf raw adapter min 1.0938 / geomean 2.1825
across all 124 contract records, 0 below the 1.0x floor.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
---
 cake_exports/kmeans/BENCHMARK_RESULTS.json    | 52256 ++++++++--------
 cake_exports/kmeans/EXPORT_TIMING.json        |     8 +-
 cake_exports/kmeans/README.md                 |    26 +-
 cake_exports/kmeans/RESULTS.md                |    30 +-
 cake_exports/kmeans/VALIDATION.json           |   240 +-
 cake_exports/kmeans/VALIDATION.md             |    26 +-
 cake_exports/kmeans/benchmarks/benchmark.py   |    15 +-
 .../src/flashlib_cake_kmeans/_row_norm.py     |    40 +-
 .../cuda/dispatch_kernel_0156.cu              |    12 +-
 .../cuda/dispatch_kernel_0157.cu              |    12 +-
 .../cuda/dispatch_kernel_0158.cu              |    12 +-
 .../cuda/dispatch_kernel_0161.cu              |    12 +-
 .../cuda/dispatch_kernel_0162.cu              |    12 +-
 .../cuda/dispatch_kernel_0165.cu              |    12 +-
 .../cuda/dispatch_kernel_0354.cu              |    12 +-
 .../cuda/dispatch_kernel_0356.cu              |    12 +-
 .../src/flashlib_cake_kmeans/interface.py     |   909 +-
 .../src/flashlib_cake_kmeans/manifest.json    |    10 +-
 18 files changed, 27075 insertions(+), 26581 deletions(-)

diff --git a/cake_exports/kmeans/BENCHMARK_RESULTS.json b/cake_exports/kmeans/BENCHMARK_RESULTS.json
index 60f3f07d..8558f297 100644
--- a/cake_exports/kmeans/BENCHMARK_RESULTS.json
+++ b/cake_exports/kmeans/BENCHMARK_RESULTS.json
@@ -41,10 +41,10 @@
     "shared_preprocess": {
       "implementation_entrypoint": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
       "result_source_sha256_field": "preprocess_source_sha256",
-      "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104"
+      "source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e"
     }
   },
-  "benchmark_registry_baseline_sha256": "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c",
+  "benchmark_registry_baseline_sha256": "bdfd30338aa614f09817af1498c1115a0b1732a3340a1acbc172d0e4dd4674c4",
   "benchmark_registry_candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
   "candidate_timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion",
   "evolution_summary": {
@@ -67,7 +67,7 @@
       "baseline_has_explicit_init": true,
       "cache_policy": "synchronize_and_clear_after_each_completed_shape",
       "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
-      "id": "3462c70f2aa84e4793077c9e9ca68837",
+      "id": "a591a388bda74a2890fb7b17b61b2608",
       "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
       "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
       "interleaved": true,
@@ -97,7 +97,7 @@
         "comparison_scope": "complete_raw_input_operators_not_assignment_only",
         "fixture_synchronized_before_cold_calls": true,
         "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
-        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "preprocess_source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
         "shared_preprocess_cold_compile_attributed_to_lane": null
       },
       "randomized_or_interleaved_order": true,
@@ -117,7 +117,7 @@
       "baseline_has_explicit_init": true,
       "cache_policy": "synchronize_and_clear_after_each_completed_shape",
       "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
-      "id": "a618b8f9b7234b02aa0a0e6f8a02f141",
+      "id": "41892d8f27794f7aba63e10273932712",
       "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
       "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
       "interleaved": true,
@@ -147,7 +147,7 @@
         "comparison_scope": "complete_raw_input_operators_not_assignment_only",
         "fixture_synchronized_before_cold_calls": true,
         "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
-        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "preprocess_source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
         "shared_preprocess_cold_compile_attributed_to_lane": null
       },
       "randomized_or_interleaved_order": true,
@@ -167,7 +167,7 @@
       "baseline_has_explicit_init": true,
       "cache_policy": "synchronize_and_clear_after_each_completed_shape",
       "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
-      "id": "bb057d64f5dd4a68a07fac499aa57dd5",
+      "id": "958ecd22358d4d5cb8ab46b2ff2cd831",
       "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
       "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
       "interleaved": true,
@@ -197,7 +197,7 @@
         "comparison_scope": "complete_raw_input_operators_not_assignment_only",
         "fixture_synchronized_before_cold_calls": true,
         "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
-        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "preprocess_source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
         "shared_preprocess_cold_compile_attributed_to_lane": null
       },
       "randomized_or_interleaved_order": true,
@@ -217,7 +217,7 @@
       "baseline_has_explicit_init": true,
       "cache_policy": "synchronize_and_clear_after_each_completed_shape",
       "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
-      "id": "3b3cb0beb21c413cab220416f38fa203",
+      "id": "429dbdfd2f734f02819474b9385e8bb8",
       "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
       "init_order_policy": "alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support",
       "interleaved": true,
@@ -247,7 +247,7 @@
         "comparison_scope": "complete_raw_input_operators_not_assignment_only",
         "fixture_synchronized_before_cold_calls": true,
         "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
-        "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "preprocess_source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
         "shared_preprocess_cold_compile_attributed_to_lane": null
       },
       "randomized_or_interleaved_order": true,
@@ -267,7 +267,7 @@
   "precomputed_baseline_name": "triton_h200_07cf_precomputed",
   "precomputed_parity_speedup_convention": "precomputed_gpu_speedup_vs_07cf = baseline_07cf_precomputed_gpu_span_ms / candidate_precomputed_gpu_span_ms",
   "preprocess_impl": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
-  "preprocess_source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+  "preprocess_source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
   "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
   "publication_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
   "publication_speedup_convention": "public_raw_e2e_speedup_vs_07cf_adapter = baseline_07cf_adapter_synchronized_e2e_ms / candidate_public_raw_synchronized_e2e_ms",
@@ -280,24 +280,24 @@
       "D": 112,
       "K": 4096,
       "N": 1408,
-      "baseline_07cf_adapter_bench_iters": 2218,
-      "baseline_07cf_adapter_gpu_span_ms": 0.088257,
-      "baseline_07cf_adapter_host_enqueue_ms": 0.1388325,
-      "baseline_07cf_adapter_inter_kernel_gap_ms": 0.037184,
-      "baseline_07cf_adapter_kernel_sum_ms": 0.051073,
-      "baseline_07cf_adapter_submission_ms": 0.1388325,
-      "baseline_07cf_adapter_synchronized_e2e_ms": 0.182849,
+      "baseline_07cf_adapter_bench_iters": 2727,
+      "baseline_07cf_adapter_gpu_span_ms": 0.088096,
+      "baseline_07cf_adapter_host_enqueue_ms": 0.139744,
+      "baseline_07cf_adapter_inter_kernel_gap_ms": 0.036928,
+      "baseline_07cf_adapter_kernel_sum_ms": 0.051137,
+      "baseline_07cf_adapter_submission_ms": 0.139744,
+      "baseline_07cf_adapter_synchronized_e2e_ms": 0.184032,
       "baseline_07cf_adapter_timing_backend": "cupti",
       "baseline_07cf_adapter_timing_diagnostics": {
         "active_union_ms": {
-          "median": 0.051073
+          "median": 0.051137
         },
         "activity_count": {
           "median": 2.0
         },
         "cold_first_call": {
-          "host_enqueue_ms": 0.256929,
-          "synchronized_e2e_ms": 0.293665
+          "host_enqueue_ms": 0.3072,
+          "synchronized_e2e_ms": 0.342048
         },
         "correlated_kernel_activity_count": {
           "median": 2.0
@@ -306,44 +306,44 @@
           "median": 2.0
         },
         "gpu_span_ms": {
-          "median": 0.088257
+          "median": 0.088096
         },
         "host_enqueue_ms": {
-          "median": 0.1388325
+          "median": 0.139744
         },
         "inter_kernel_gap_ms": {
-          "median": 0.037184
+          "median": 0.036928
         },
         "kernel_sum_ms": {
-          "median": 0.051073
+          "median": 0.051137
         },
         "lane_primary_metric": "synchronized_e2e_ms",
-        "sample_count": 2218,
+        "sample_count": 2727,
         "submission_ms": {
-          "median": 0.1388325
+          "median": 0.139744
         },
         "synchronized_e2e_ms": {
-          "median": 0.182849
+          "median": 0.184032
         }
       },
-      "baseline_07cf_precomputed_bench_iters": 2361,
-      "baseline_07cf_precomputed_gpu_span_ms": 0.052128,
-      "baseline_07cf_precomputed_host_enqueue_ms": 0.041953,
+      "baseline_07cf_precomputed_bench_iters": 2574,
+      "baseline_07cf_precomputed_gpu_span_ms": 0.052353,
+      "baseline_07cf_precomputed_host_enqueue_ms": 0.042016,
       "baseline_07cf_precomputed_inter_kernel_gap_ms": 0.0,
-      "baseline_07cf_precomputed_kernel_sum_ms": 0.052128,
-      "baseline_07cf_precomputed_submission_ms": 0.041953,
-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.100385,
+      "baseline_07cf_precomputed_kernel_sum_ms": 0.052353,
+      "baseline_07cf_precomputed_submission_ms": 0.042016,
+      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.101136,
       "baseline_07cf_precomputed_timing_backend": "cupti",
       "baseline_07cf_precomputed_timing_diagnostics": {
         "active_union_ms": {
-          "median": 0.052128
+          "median": 0.052353
         },
         "activity_count": {
           "median": 1.0
         },
         "cold_first_call": {
-          "host_enqueue_ms": 0.050561,
-          "synchronized_e2e_ms": 0.097825
+          "host_enqueue_ms": 0.044064,
+          "synchronized_e2e_ms": 0.091744
         },
         "correlated_kernel_activity_count": {
           "median": 1.0
@@ -352,33 +352,33 @@
           "median": 1.0
         },
         "gpu_span_ms": {
-          "median": 0.052128
+          "median": 0.052353
         },
         "host_enqueue_ms": {
-          "median": 0.041953
+          "median": 0.042016
         },
         "inter_kernel_gap_ms": {
           "median": 0.0
         },
         "kernel_sum_ms": {
-          "median": 0.052128
+          "median": 0.052353
         },
         "lane_primary_metric": "gpu_span_ms",
-        "sample_count": 2361,
+        "sample_count": 2574,
         "submission_ms": {
-          "median": 0.041953
+          "median": 0.042016
         },
         "synchronized_e2e_ms": {
-          "median": 0.100385
+          "median": 0.101136
         }
       },
       "baseline_commit": "07cf2a27928aacf6790c950a265d8b8dc83c87cf",
       "baseline_precomputed_norm_policy": "explicit_precomputed_outside_timing",
       "baseline_precomputed_output_policy": "preallocated_outside_timing",
       "baseline_public_prepared_ratios": {
-        "gpu_span": 1.6930824125230204,
-        "submission": 3.309238910209044,
-        "synchronized_e2e": 1.8214773123474624
+        "gpu_span": 1.6827306935610185,
+        "submission": 3.3259710586443263,
+        "synchronized_e2e": 1.8196487897484575
       },
       "baseline_public_raw_assignment_launch_count": 1,
       "baseline_public_raw_fresh_pointer_cache_hit": true,
@@ -395,31 +395,31 @@
         "amortization": {
           "call_counts": [
             {
-              "after_init_host_enqueue_ms_per_call": 363.555562,
-              "after_init_synchronized_e2e_ms_per_call": 363.593706,
-              "including_init_host_enqueue_ms_per_call": 401.85929500000003,
-              "including_init_synchronized_e2e_ms_per_call": 401.976064,
+              "after_init_host_enqueue_ms_per_call": 356.642449,
+              "after_init_synchronized_e2e_ms_per_call": 356.705265,
+              "including_init_host_enqueue_ms_per_call": 390.870356,
+              "including_init_synchronized_e2e_ms_per_call": 391.050708,
               "public_call_count": 1
             },
             {
-              "after_init_host_enqueue_ms_per_call": 36.480505449999995,
-              "after_init_synchronized_e2e_ms_per_call": 36.5239347,
-              "including_init_host_enqueue_ms_per_call": 40.31087875,
-              "including_init_synchronized_e2e_ms_per_call": 40.362170500000005,
+              "after_init_host_enqueue_ms_per_call": 35.7900145,
+              "after_init_synchronized_e2e_ms_per_call": 35.8361553,
+              "including_init_host_enqueue_ms_per_call": 39.212805200000005,
+              "including_init_synchronized_e2e_ms_per_call": 39.2706996,
               "public_call_count": 10
             },
             {
-              "after_init_host_enqueue_ms_per_call": 3.772999795,
-              "after_init_synchronized_e2e_ms_per_call": 3.81695757,
-              "including_init_host_enqueue_ms_per_call": 4.156037125,
-              "including_init_synchronized_e2e_ms_per_call": 4.20078115,
+              "after_init_host_enqueue_ms_per_call": 3.7047710499999997,
+              "after_init_synchronized_e2e_ms_per_call": 3.7492443300000002,
+              "including_init_host_enqueue_ms_per_call": 4.04705012,
+              "including_init_synchronized_e2e_ms_per_call": 4.09269876,
               "public_call_count": 100
             },
             {
-              "after_init_host_enqueue_ms_per_call": 0.5022492295000001,
-              "after_init_synchronized_e2e_ms_per_call": 0.546259857,
-              "including_init_host_enqueue_ms_per_call": 0.5405529625000001,
-              "including_init_synchronized_e2e_ms_per_call": 0.5846422150000001,
+              "after_init_host_enqueue_ms_per_call": 0.496246705,
+              "after_init_synchronized_e2e_ms_per_call": 0.540553233,
+              "including_init_host_enqueue_ms_per_call": 0.530474612,
+              "including_init_synchronized_e2e_ms_per_call": 0.574898676,
               "public_call_count": 1000
             }
           ],
@@ -433,68 +433,71 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
-          "host_enqueue_ms": 363.555562,
-          "synchronized_e2e_ms": 363.593706,
+          "host_enqueue_ms": 356.642449,
+          "synchronized_e2e_ms": 356.705265,
           "timing_class": "cupti_timestamp_host_diagnostic"
         },
         "hot_compute": {
           "cache_state": "fresh_pointer_shape_slot_hit",
           "gpu_span_ms": {
-            "max": 0.355522,
-            "median": 0.088257,
-            "min": 0.080448,
-            "p90": 0.1105059,
-            "sample_count": 2218
+            "max": 0.529889,
+            "median": 0.088096,
+            "min": 0.081024,
+            "p90": 0.107456,
+            "sample_count": 2727
           },
           "host_enqueue_ms": {
-            "max": 0.818469,
-            "median": 0.1388325,
-            "min": 0.121568,
-            "p90": 0.18294499999999997,
-            "sample_count": 2218
+            "max": 1.376257,
+            "median": 0.139744,
+            "min": 0.118721,
+            "p90": 0.2122496,
+            "sample_count": 2727
           },
-          "sample_count": 2218,
+          "sample_count": 2727,
           "synchronized_e2e_ms": {
-            "max": 0.916997,
-            "median": 0.182849,
-            "min": 0.165953,
-            "p90": 0.22368169999999998,
-            "sample_count": 2218
+            "max": 1.652769,
+            "median": 0.184032,
+            "min": 0.164257,
+            "p90": 0.2479424,
+            "sample_count": 2727
           },
           "timing_backend": "cupti"
         },
         "init_once": {
-          "host_enqueue_ms": 38.303733,
-          "sample_id": "3462c70f2aa84e4793077c9e9ca68837",
-          "synchronized_e2e_ms": 38.382357999999996,
+          "host_enqueue_ms": 34.227907,
+          "sample_id": "a591a388bda74a2890fb7b17b61b2608",
+          "synchronized_e2e_ms": 34.345443,
           "timing_class": "cupti_timestamp_host_diagnostic"
         },
-        "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
+        "measurement_session_id": "a591a388bda74a2890fb7b17b61b2608",
         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_shared_fused_pair_norm_plus_pinned_07cf_assign_synchronized_e2e"
       },
-      "candidate_precomputed_bench_iters": 2361,
-      "candidate_precomputed_gpu_span_ms": 0.038528,
-      "candidate_precomputed_host_enqueue_ms": 0.050944,
-      "candidate_precomputed_inter_kernel_gap_ms": 0.004416,
-      "candidate_precomputed_kernel_sum_ms": 0.03408,
+      "candidate_graph_capture_error": null,
+      "candidate_graph_kernel_count": 3,
+      "candidate_hot_launch_path": "cuda_graph",
+      "candidate_precomputed_bench_iters": 2574,
+      "candidate_precomputed_gpu_span_ms": 0.039072,
+      "candidate_precomputed_host_enqueue_ms": 0.052816,
+      "candidate_precomputed_inter_kernel_gap_ms": 0.004768,
+      "candidate_precomputed_kernel_sum_ms": 0.034208,
       "candidate_precomputed_launch_count": 2,
       "candidate_precomputed_norm_policy": "explicit_precomputed_outside_timing",
       "candidate_precomputed_output_policy": "preallocated_outside_timing",
-      "candidate_precomputed_submission_ms": 0.050944,
-      "candidate_precomputed_synchronized_e2e_ms": 0.071776,
+      "candidate_precomputed_submission_ms": 0.052816,
+      "candidate_precomputed_synchronized_e2e_ms": 0.073504,
       "candidate_precomputed_timing_backend": "cupti",
       "candidate_precomputed_timing_diagnostics": {
         "active_union_ms": {
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           "median": 2.0
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         "cold_first_call": {
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-          "synchronized_e2e_ms": 0.067424
+          "host_enqueue_ms": 0.043392,
+          "synchronized_e2e_ms": 0.064672
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         "correlated_kernel_activity_count": {
           "median": 2.0
@@ -503,24 +506,24 @@
           "median": 2.0
         },
         "gpu_span_ms": {
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+          "median": 0.039072
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         "host_enqueue_ms": {
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         "inter_kernel_gap_ms": {
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         "lane_primary_metric": "gpu_span_ms",
-        "sample_count": 2361,
+        "sample_count": 2574,
         "submission_ms": {
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         "synchronized_e2e_ms": {
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       "candidate_prepared_path_proof": {
@@ -532,18 +535,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc297fcb00",
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc297fc380"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc295c3ef0",
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282af410"
         ],
         "stream_bound": true
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       "candidate_public_prepared_ratios": {
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-        "submission": 1.4616834170854272,
-        "synchronized_e2e": 1.4712578020508247
+        "gpu_span": 0.941031941031941,
+        "submission": 0.807028173280824,
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       "candidate_public_raw_assignment_launch_count": 2,
-      "candidate_public_raw_bench_iters": 2218,
+      "candidate_public_raw_bench_iters": 2727,
       "candidate_public_raw_cold_first_call_activity": {
         "module_load_occurred": true,
         "nvrtc_compile_occurred": true,
@@ -551,10 +554,10 @@
         "source_read_occurred": true
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       "candidate_public_raw_fresh_pointer_cache_hit": true,
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-      "candidate_public_raw_inter_kernel_gap_ms": 0.007264,
-      "candidate_public_raw_kernel_sum_ms": 0.035232,
+      "candidate_public_raw_gpu_span_ms": 0.036768,
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+      "candidate_public_raw_inter_kernel_gap_ms": 0.0,
+      "candidate_public_raw_kernel_sum_ms": 0.03696,
       "candidate_public_raw_norm_compute_fields": [
         "x_sq",
         "c_sq"
@@ -563,46 +566,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
-      "candidate_public_raw_submission_ms": 0.074464,
-      "candidate_public_raw_synchronized_e2e_ms": 0.105601,
-      "candidate_public_raw_tflops_from_gpu_span": 30.376355154251318,
+      "candidate_public_raw_submission_ms": 0.042624,
+      "candidate_public_raw_synchronized_e2e_ms": 0.08192,
+      "candidate_public_raw_tflops_from_gpu_span": 35.135053089643165,
       "candidate_public_raw_timing_backend": "cupti",
       "candidate_public_raw_timing_diagnostics": {
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         "cold_first_call": {
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         "correlated_kernel_activity_count": {
           "median": 3.0
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       "candidate_public_raw_total_launch_count": 3,
@@ -610,31 +613,31 @@
         "amortization": {
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-              "including_init_host_enqueue_ms_per_call": 107.134324,
-              "including_init_synchronized_e2e_ms_per_call": 594.654962,
+              "after_init_host_enqueue_ms_per_call": 79.679571,
+              "after_init_synchronized_e2e_ms_per_call": 79.714707,
+              "including_init_host_enqueue_ms_per_call": 114.257111,
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               "public_call_count": 1
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-              "including_init_host_enqueue_ms_per_call": 10.78045,
-              "including_init_synchronized_e2e_ms_per_call": 59.5605371,
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+              "after_init_synchronized_e2e_ms_per_call": 8.0451987,
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-              "including_init_host_enqueue_ms_per_call": 1.1450626000000002,
-              "including_init_synchronized_e2e_ms_per_call": 6.05109461,
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-              "including_init_synchronized_e2e_ms_per_call": 0.7001503609999999,
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               "public_call_count": 1000
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           ],
@@ -648,99 +651,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 68.624639,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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-            "sample_count": 2218
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "schema": "loom-public-runtime-lifecycle-v1",
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       "cold_baseline_precomputed_fresh_pointer": {
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       "cold_measurement_order": [
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@@ -756,8 +759,6 @@
       "fresh_pointer_rebind_verified": true,
       "label": "adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112",
       "measurement_order": [
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
@@ -768,21 +769,21 @@
         "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
-        "candidate_precomputed",
         "baseline_precomputed",
+        "candidate_precomputed",
         "baseline_public_raw",
-        "candidate_public_raw"
+        "candidate_public_raw",
+        "candidate_precomputed",
+        "baseline_precomputed"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
+      "measurement_session_id": "a591a388bda74a2890fb7b17b61b2608",
       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
         "adjacent_candidate_baseline_pairs": true,
         "first_reportable_roles": [
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-          "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
           "baseline_precomputed",
@@ -793,60 +794,62 @@
           "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
-          "candidate_precomputed",
           "baseline_precomputed",
+          "candidate_precomputed",
           "baseline_public_raw",
-          "candidate_public_raw"
+          "candidate_public_raw",
+          "candidate_precomputed",
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-        "measurement_schedule_sha256": "5a6d6a351c95e494e2934f87f1205e6b3e2b85121dc227aade5f37ca2607be8b",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
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-        "public_pair_count": 2218,
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-          "candidate_precomputed": 2361,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 1834
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+      "paired_cupti_session_id": "a591a388bda74a2890fb7b17b61b2608:adjacent_1d49_d112_highk_tail_b1_n1408_k4096_d112",
       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.3529900332225915,
+      "precomputed_gpu_speedup_vs_07cf": 1.3399109336609334,
       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7315082243539361,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 2.2464843749999996,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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-            "including_init_synchronized_e2e_speedup": 0.6759820226640941,
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         ],
-        "hot_gpu_span_speedup": 2.0752680586907446,
-        "hot_synchronized_e2e_speedup": 1.7315082243539361,
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+        "hot_synchronized_e2e_speedup": 2.2464843749999996,
         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
       },
@@ -870,24 +873,24 @@
       "D": 128,
       "K": 512,
       "N": 7296,
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-      "baseline_07cf_adapter_submission_ms": 0.141536,
-      "baseline_07cf_adapter_synchronized_e2e_ms": 0.162433,
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+      "baseline_07cf_adapter_gpu_span_ms": 0.06488,
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+      "baseline_07cf_adapter_inter_kernel_gap_ms": 0.023328,
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+      "baseline_07cf_adapter_submission_ms": 0.1553445,
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       "baseline_07cf_adapter_timing_backend": "cupti",
       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -896,44 +899,44 @@
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@@ -942,33 +945,33 @@
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@@ -985,31 +988,31 @@
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@@ -1023,68 +1026,71 @@
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@@ -1093,24 +1099,24 @@
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@@ -1122,18 +1128,18 @@
         "root_dispatch_traversal_count": 0,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282a2f30"
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@@ -1141,10 +1147,10 @@
         "source_read_occurred": true
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@@ -1153,46 +1159,46 @@
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@@ -1200,31 +1206,31 @@
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@@ -1238,99 +1244,99 @@
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@@ -1365,7 +1371,7 @@
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@@ -1389,54 +1395,54 @@
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@@ -1460,24 +1466,24 @@
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@@ -1486,44 +1492,44 @@
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@@ -1532,33 +1538,33 @@
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@@ -1575,31 +1581,31 @@
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@@ -1613,68 +1619,71 @@
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@@ -1683,24 +1692,24 @@
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@@ -1712,18 +1721,18 @@
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-      "candidate_public_raw_bench_iters": 1493,
+      "candidate_public_raw_bench_iters": 1573,
       "candidate_public_raw_cold_first_call_activity": {
         "module_load_occurred": true,
         "nvrtc_compile_occurred": true,
@@ -1731,10 +1740,10 @@
         "source_read_occurred": true
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       "candidate_public_raw_fresh_pointer_cache_hit": true,
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-      "candidate_public_raw_inter_kernel_gap_ms": 0.0048,
-      "candidate_public_raw_kernel_sum_ms": 0.062528,
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       "candidate_public_raw_norm_compute_fields": [
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@@ -1743,46 +1752,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.132897,
-      "candidate_public_raw_tflops_from_gpu_span": 143.83459627974642,
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       "candidate_public_raw_timing_diagnostics": {
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       "candidate_public_raw_total_launch_count": 3,
@@ -1790,31 +1799,31 @@
         "amortization": {
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@@ -1828,99 +1837,99 @@
           "code_cache_state": "process_order_dependent",
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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@@ -1944,18 +1953,18 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed"
+        "baseline_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -1969,64 +1978,64 @@
           "candidate_precomputed",
           "baseline_precomputed",
           "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
           "candidate_precomputed",
-          "baseline_precomputed"
+          "baseline_precomputed",
+          "candidate_public_raw",
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-        "measurement_schedule_sha256": "c207cad615df8c99b658b484a7e7583f4949a349c36333c1e407bac6e1ebe5ba",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 3524,
-        "public_pair_count": 1493,
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-          "candidate_precomputed": 3524,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 2008
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.079954954954955,
+      "precomputed_gpu_speedup_vs_07cf": 1.0754716981132075,
       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.2932797580080815,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 1.5634209819485223,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -2050,24 +2059,24 @@
       "D": 288,
       "K": 2048,
       "N": 1152,
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@@ -2076,44 +2085,44 @@
           "median": 2.0
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@@ -2122,33 +2131,33 @@
           "median": 1.0
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@@ -2273,24 +2285,24 @@
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@@ -2302,18 +2314,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -2321,10 +2333,10 @@
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@@ -2333,46 +2345,46 @@
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@@ -2380,31 +2392,31 @@
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@@ -2545,7 +2557,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -2569,54 +2581,54 @@
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.3766265143409382,
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -2640,24 +2652,24 @@
       "D": 352,
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@@ -2666,44 +2678,44 @@
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@@ -2712,33 +2724,33 @@
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@@ -2755,31 +2767,31 @@
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@@ -2793,68 +2805,71 @@
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@@ -2863,24 +2878,24 @@
           "median": 2.0
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@@ -2892,18 +2907,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0274ea80"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04734620",
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@@ -2911,10 +2926,10 @@
         "source_read_occurred": true
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@@ -2922,46 +2937,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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       "candidate_public_raw_total_launch_count": 3,
@@ -2969,31 +2984,31 @@
         "amortization": {
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+              "after_init_synchronized_e2e_ms_per_call": 75.966031,
+              "including_init_host_enqueue_ms_per_call": 110.469843,
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-              "including_init_host_enqueue_ms_per_call": 13.08096405,
-              "including_init_synchronized_e2e_ms_per_call": 61.9239418,
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-              "including_init_synchronized_e2e_ms_per_call": 0.7932269679999999,
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+              "including_init_synchronized_e2e_ms_per_call": 0.6777879349999999,
               "public_call_count": 1000
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@@ -3007,99 +3022,99 @@
           "code_cache_state": "process_order_dependent",
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 91.62739,
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         "schema": "loom-public-runtime-lifecycle-v1",
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -3129,12 +3144,12 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_public_raw",
+        "baseline_public_raw"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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       "paired_cupti_session": {
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@@ -3154,58 +3169,58 @@
           "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed"
+          "candidate_public_raw",
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-        "measurement_schedule_sha256": "84c1cf3d617de318661f6077e5dde8a04f7a935c3134ac7808cfe6af6209ce4c",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 1196,
-        "public_pair_count": 914,
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         "reportable_cupti_session_count": 1,
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-          "candidate_precomputed": 1196,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 846
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 2.9486553445118666,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.983521579561296,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -3229,24 +3244,24 @@
       "D": 416,
       "K": 512,
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       "baseline_07cf_adapter_timing_backend": "cupti",
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@@ -3255,44 +3270,44 @@
           "median": 2.0
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-      "baseline_07cf_precomputed_gpu_span_ms": 0.042176,
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -3301,33 +3316,33 @@
           "median": 1.0
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@@ -3344,31 +3359,31 @@
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@@ -3452,24 +3470,24 @@
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@@ -3481,18 +3499,18 @@
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@@ -3500,10 +3518,10 @@
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@@ -3512,46 +3530,46 @@
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@@ -3559,31 +3577,31 @@
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@@ -3597,99 +3615,99 @@
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@@ -3724,7 +3742,7 @@
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@@ -3748,54 +3766,54 @@
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@@ -3819,24 +3837,24 @@
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@@ -3845,44 +3863,44 @@
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@@ -3891,33 +3909,33 @@
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@@ -3934,31 +3952,31 @@
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@@ -3972,68 +3990,71 @@
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@@ -4042,24 +4063,24 @@
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@@ -4071,18 +4092,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -4090,10 +4111,10 @@
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@@ -4102,46 +4123,46 @@
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@@ -4149,31 +4170,31 @@
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               "public_call_count": 1000
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-            "p90": 0.038144,
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@@ -4309,12 +4330,12 @@
         "candidate_precomputed",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed"
+        "baseline_public_raw",
+        "candidate_public_raw"
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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@@ -4334,58 +4355,58 @@
           "candidate_precomputed",
           "candidate_precomputed",
           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed"
+          "baseline_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -4409,24 +4430,24 @@
       "D": 48,
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@@ -4435,44 +4456,44 @@
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@@ -4481,33 +4502,33 @@
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@@ -4524,31 +4545,31 @@
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@@ -4562,68 +4583,71 @@
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@@ -4632,24 +4656,24 @@
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@@ -4661,18 +4685,18 @@
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@@ -4680,10 +4704,10 @@
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@@ -4692,46 +4716,46 @@
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@@ -4739,31 +4763,31 @@
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@@ -4885,97 +4909,97 @@
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -4999,24 +5023,24 @@
       "D": 112,
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       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -5025,44 +5049,44 @@
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@@ -5071,33 +5095,33 @@
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@@ -5114,31 +5138,31 @@
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@@ -5152,68 +5176,71 @@
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@@ -5222,24 +5249,24 @@
           "median": 1.0
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@@ -5251,18 +5278,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc02884bf0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffe4324f170",
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       "candidate_public_raw_cold_first_call_activity": {
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@@ -5270,10 +5297,10 @@
         "source_read_occurred": true
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@@ -5281,46 +5308,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -5328,31 +5355,31 @@
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@@ -5366,99 +5393,99 @@
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@@ -5493,7 +5520,7 @@
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@@ -5517,54 +5544,54 @@
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@@ -5588,24 +5615,24 @@
       "D": 128,
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@@ -5614,44 +5641,44 @@
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@@ -5660,33 +5687,33 @@
           "median": 1.0
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@@ -5703,31 +5730,31 @@
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@@ -5741,68 +5768,71 @@
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@@ -5811,24 +5841,24 @@
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@@ -5840,18 +5870,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04a9dee0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb7f305af0",
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@@ -5859,10 +5889,10 @@
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@@ -5871,46 +5901,46 @@
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@@ -5918,31 +5948,31 @@
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@@ -5956,99 +5986,99 @@
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@@ -6083,7 +6113,7 @@
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@@ -6107,54 +6137,54 @@
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -6178,24 +6208,24 @@
       "D": 224,
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@@ -6204,44 +6234,44 @@
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+      "baseline_07cf_precomputed_gpu_span_ms": 0.018272,
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-      "baseline_07cf_precomputed_submission_ms": 0.041472,
-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.0661285,
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       "baseline_07cf_precomputed_timing_backend": "cupti",
       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -6250,33 +6280,33 @@
           "median": 1.0
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@@ -6293,31 +6323,31 @@
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@@ -6331,68 +6361,71 @@
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@@ -6401,24 +6434,24 @@
           "median": 2.0
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@@ -6430,18 +6463,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc295a7b60"
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@@ -6449,10 +6482,10 @@
         "source_read_occurred": false
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@@ -6461,46 +6494,46 @@
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@@ -6508,31 +6541,31 @@
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@@ -6546,99 +6579,99 @@
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@@ -6660,6 +6693,8 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
         "candidate_precomputed",
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         "baseline_precomputed",
@@ -6667,13 +6702,11 @@
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed"
+        "candidate_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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@@ -6685,6 +6718,8 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "candidate_public_raw",
+          "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
           "baseline_precomputed",
@@ -6692,59 +6727,57 @@
           "candidate_public_raw",
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           "baseline_precomputed",
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-          "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.6212564578624478,
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       "route_matches_expected": true,
       "runtime_coverage": false,
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@@ -6768,24 +6801,24 @@
       "D": 288,
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@@ -6794,44 +6827,44 @@
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@@ -6840,33 +6873,33 @@
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@@ -6883,31 +6916,31 @@
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@@ -6921,68 +6954,71 @@
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@@ -6991,24 +7027,24 @@
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@@ -7020,18 +7056,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0491e660"
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@@ -7039,10 +7075,10 @@
         "source_read_occurred": false
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@@ -7051,46 +7087,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -7098,31 +7134,31 @@
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@@ -7136,99 +7172,99 @@
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@@ -7263,7 +7299,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -7287,54 +7323,54 @@
           "candidate_precomputed"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "route_matches_expected": true,
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       "runtime_lifecycle_comparison": {
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@@ -7358,24 +7394,24 @@
       "D": 352,
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@@ -7384,44 +7420,44 @@
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@@ -7430,33 +7466,33 @@
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@@ -7511,68 +7547,71 @@
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@@ -7581,24 +7620,24 @@
           "median": 2.0
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@@ -7610,18 +7649,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc02886690"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282afe90",
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       "candidate_public_raw_cold_first_call_activity": {
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         "nvrtc_compile_occurred": true,
@@ -7629,10 +7668,10 @@
         "source_read_occurred": true
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       "candidate_public_raw_norm_compute_fields": [
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@@ -7641,46 +7680,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_tflops_from_gpu_span": 75.38781699346406,
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@@ -7688,31 +7727,31 @@
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@@ -7726,99 +7765,99 @@
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       "cold_baseline_precomputed_first_pointer": {
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@@ -7844,16 +7883,16 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
+        "candidate_precomputed",
         "baseline_precomputed",
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+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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         "adaptive_probes_reportable": false,
@@ -7869,62 +7908,62 @@
           "baseline_public_raw",
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           "candidate_precomputed",
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-          "baseline_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -7948,24 +7987,24 @@
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@@ -7974,44 +8013,44 @@
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@@ -8020,33 +8059,33 @@
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@@ -8063,31 +8102,31 @@
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@@ -8101,68 +8140,71 @@
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@@ -8171,24 +8213,24 @@
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@@ -8200,18 +8242,18 @@
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         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282a3f80"
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@@ -8219,10 +8261,10 @@
         "source_read_occurred": true
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@@ -8230,46 +8272,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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       "candidate_public_raw_total_launch_count": 4,
@@ -8277,31 +8319,31 @@
         "amortization": {
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+              "after_init_synchronized_e2e_ms_per_call": 76.74536,
+              "including_init_host_enqueue_ms_per_call": 111.579572,
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-              "including_init_host_enqueue_ms_per_call": 10.1611547,
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-              "including_init_synchronized_e2e_ms_per_call": 0.21666860200000002,
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@@ -8315,99 +8357,99 @@
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
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@@ -8433,16 +8475,16 @@
         "candidate_public_raw",
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         "baseline_public_raw",
         "candidate_public_raw",
         "candidate_precomputed",
-        "baseline_precomputed"
+        "baseline_precomputed",
+        "candidate_public_raw",
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       "paired_cupti_session": {
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@@ -8458,62 +8500,62 @@
           "candidate_public_raw",
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           "candidate_precomputed",
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           "baseline_public_raw",
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           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 3.143360295577559,
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       "route_matches_expected": true,
       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -8537,24 +8579,24 @@
       "D": 480,
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@@ -8563,44 +8605,44 @@
           "median": 2.0
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@@ -8609,33 +8651,33 @@
           "median": 1.0
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@@ -8652,31 +8694,31 @@
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@@ -8690,68 +8732,71 @@
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 7.167912,
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+      "candidate_hot_launch_path": "cuda_graph",
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       "candidate_precomputed_norm_policy": "explicit_precomputed_outside_timing",
       "candidate_precomputed_output_policy": "preallocated_outside_timing",
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       "candidate_precomputed_timing_backend": "cupti",
       "candidate_precomputed_timing_diagnostics": {
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@@ -8760,24 +8805,24 @@
           "median": 2.0
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@@ -8789,18 +8834,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc03a32330",
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc03a32510"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282c66c0",
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       "candidate_public_prepared_ratios": {
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       "candidate_public_raw_cold_first_call_activity": {
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         "nvrtc_compile_occurred": false,
@@ -8808,10 +8853,10 @@
         "source_read_occurred": false
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       "candidate_public_raw_norm_compute_fields": [
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         "c_sq"
@@ -8820,46 +8865,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.094368,
-      "candidate_public_raw_tflops_from_gpu_span": 1.1196355353075171,
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       "candidate_public_raw_timing_diagnostics": {
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@@ -8867,31 +8912,31 @@
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@@ -8905,99 +8950,99 @@
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@@ -9019,6 +9064,8 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
         "baseline_precomputed",
@@ -9026,13 +9073,11 @@
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -9044,6 +9089,8 @@
           "baseline_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "candidate_public_raw",
+          "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
           "baseline_precomputed",
@@ -9051,59 +9098,57 @@
           "candidate_public_raw",
           "baseline_public_raw",
           "baseline_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "candidate_precomputed"
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-        "measurement_schedule_sha256": "245c091d3e871c8e8ab9123afe7131693ed39732896ed2c5b8485f4da5294a66",
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+        "measurement_schedule_sha256": "b2eb17b035664122487752e4a7890526b5d2f36f0629b82a6464b1e164ce3e59",
         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 7650,
-        "public_pair_count": 3276,
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@@ -9143,8 +9188,8 @@
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@@ -9242,31 +9287,31 @@
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@@ -9280,68 +9325,71 @@
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@@ -9350,24 +9398,24 @@
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@@ -9379,18 +9427,18 @@
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@@ -9398,10 +9446,10 @@
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@@ -9410,46 +9458,46 @@
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@@ -9457,31 +9505,31 @@
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-              "including_init_synchronized_e2e_ms_per_call": 0.502691865,
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               "public_call_count": 100
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               "public_call_count": 1000
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           ],
@@ -9495,99 +9543,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
-          "host_enqueue_ms": 2.13534,
-          "synchronized_e2e_ms": 2.159468,
+          "host_enqueue_ms": 3.566787,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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           "gpu_span_ms": {
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           "synchronized_e2e_ms": {
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-          "sample_id": "3b3cb0beb21c413cab220416f38fa203",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "schema": "loom-public-runtime-lifecycle-v1",
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -9603,97 +9651,97 @@
       "fresh_pointer_rebind_verified": true,
       "label": "adjacent_3328_d48_small_boundary_b1_n256_k256_d48",
       "measurement_order": [
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         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
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-        "candidate_precomputed",
-        "baseline_public_raw",
         "candidate_public_raw",
+        "baseline_public_raw",
         "candidate_precomputed",
-        "baseline_precomputed"
+        "baseline_precomputed",
+        "baseline_precomputed",
+        "candidate_precomputed"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
         "adjacent_candidate_baseline_pairs": true,
         "first_reportable_roles": [
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           "candidate_precomputed",
           "baseline_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
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           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7262358943426577,
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -9717,24 +9765,24 @@
       "D": 112,
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@@ -9743,33 +9791,33 @@
           "median": 2.0
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@@ -9779,8 +9827,8 @@
           "median": 1.0
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@@ -9792,7 +9840,7 @@
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@@ -9801,21 +9849,21 @@
           "median": 0.014048
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@@ -9832,31 +9880,31 @@
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@@ -9870,68 +9918,71 @@
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@@ -9940,24 +9991,24 @@
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@@ -9969,18 +10020,18 @@
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@@ -9988,10 +10039,10 @@
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@@ -10000,46 +10051,46 @@
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@@ -10047,31 +10098,31 @@
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@@ -10085,99 +10136,99 @@
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@@ -10199,20 +10250,20 @@
         "candidate_public_raw",
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@@ -10224,66 +10275,66 @@
           "candidate_public_raw",
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           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.9799107142857143,
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@@ -10379,33 +10430,33 @@
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@@ -10460,68 +10511,71 @@
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@@ -10530,24 +10584,24 @@
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@@ -10559,18 +10613,18 @@
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@@ -10578,10 +10632,10 @@
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@@ -10590,46 +10644,46 @@
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@@ -10637,31 +10691,31 @@
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@@ -10802,7 +10856,7 @@
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@@ -10826,54 +10880,54 @@
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@@ -10897,24 +10951,24 @@
       "D": 224,
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@@ -10923,44 +10977,44 @@
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@@ -10969,33 +11023,33 @@
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@@ -11012,31 +11066,31 @@
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@@ -11050,68 +11104,71 @@
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       "candidate_precomputed_timing_diagnostics": {
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@@ -11120,24 +11177,24 @@
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@@ -11149,18 +11206,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04e38230"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc01233710",
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@@ -11168,10 +11225,10 @@
         "source_read_occurred": false
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@@ -11180,46 +11237,46 @@
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       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -11227,31 +11284,31 @@
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@@ -11265,99 +11322,99 @@
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@@ -11379,20 +11436,20 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
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         "candidate_precomputed",
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         "baseline_public_raw",
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@@ -11404,66 +11461,66 @@
           "candidate_public_raw",
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           "candidate_precomputed",
+          "candidate_public_raw",
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           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -11487,24 +11544,24 @@
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@@ -11513,44 +11570,44 @@
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@@ -11559,33 +11616,33 @@
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@@ -11602,31 +11659,31 @@
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@@ -11640,68 +11697,71 @@
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@@ -11710,24 +11770,24 @@
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@@ -11739,18 +11799,18 @@
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@@ -11758,10 +11818,10 @@
         "source_read_occurred": false
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@@ -11770,46 +11830,46 @@
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@@ -11817,31 +11877,31 @@
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@@ -11982,7 +12042,7 @@
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@@ -12006,54 +12066,54 @@
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@@ -12077,24 +12137,24 @@
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@@ -12103,33 +12163,33 @@
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@@ -12139,8 +12199,8 @@
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@@ -12152,7 +12212,7 @@
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@@ -12161,21 +12221,21 @@
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@@ -12192,31 +12252,31 @@
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@@ -12230,68 +12290,71 @@
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@@ -12300,24 +12363,24 @@
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@@ -12329,18 +12392,18 @@
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         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0274cad0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04536f30",
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       "candidate_public_raw_cold_first_call_activity": {
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@@ -12348,10 +12411,10 @@
         "source_read_occurred": false
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@@ -12359,46 +12422,46 @@
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@@ -12406,31 +12469,31 @@
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@@ -12444,99 +12507,99 @@
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@@ -12558,20 +12621,20 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -12583,66 +12646,66 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "baseline_public_raw",
+          "candidate_public_raw",
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 3.0665622552858265,
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       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -12666,24 +12729,24 @@
       "D": 416,
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@@ -12692,44 +12755,44 @@
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-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.063104,
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -12738,33 +12801,33 @@
           "median": 1.0
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       "baseline_precomputed_norm_policy": "explicit_precomputed_outside_timing",
       "baseline_precomputed_output_policy": "preallocated_outside_timing",
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@@ -12781,31 +12844,31 @@
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@@ -12819,68 +12882,71 @@
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@@ -12889,24 +12955,24 @@
           "median": 2.0
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@@ -12918,18 +12984,18 @@
         "root_dispatch_traversal_count": 0,
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         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04b8b560"
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@@ -12937,10 +13003,10 @@
         "source_read_occurred": false
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@@ -12949,46 +13015,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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@@ -12996,31 +13062,31 @@
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@@ -13034,99 +13100,99 @@
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@@ -13150,18 +13216,18 @@
         "candidate_precomputed",
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         "baseline_public_raw",
         "baseline_precomputed",
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+        "baseline_precomputed",
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@@ -13175,64 +13241,64 @@
           "candidate_precomputed",
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@@ -13256,24 +13322,24 @@
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@@ -13282,44 +13348,44 @@
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@@ -13328,33 +13394,33 @@
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@@ -13371,31 +13437,31 @@
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@@ -13409,68 +13475,71 @@
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@@ -13479,24 +13548,24 @@
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@@ -13508,18 +13577,18 @@
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@@ -13527,10 +13596,10 @@
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@@ -13538,46 +13607,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.099424,
-      "candidate_public_raw_tflops_from_gpu_span": 47.75751779106177,
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       "candidate_public_raw_timing_diagnostics": {
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@@ -13585,31 +13654,31 @@
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@@ -13623,99 +13692,99 @@
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@@ -13741,16 +13810,16 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "baseline_precomputed",
         "candidate_precomputed",
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+        "baseline_public_raw",
+        "candidate_public_raw"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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@@ -13766,62 +13835,62 @@
           "candidate_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
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           "candidate_precomputed",
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-        "precomputed_pair_count": 4633,
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         "schema": "flash-kmeans-interleaved-cupti-session-v1",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.6235465116279069,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7708500965561635,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -13845,24 +13914,24 @@
       "D": 48,
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@@ -13871,44 +13940,44 @@
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@@ -13917,33 +13986,33 @@
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@@ -13998,68 +14067,71 @@
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@@ -14068,24 +14140,24 @@
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@@ -14097,18 +14169,18 @@
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@@ -14116,10 +14188,10 @@
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@@ -14128,46 +14200,46 @@
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@@ -14175,31 +14247,31 @@
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@@ -14213,99 +14285,99 @@
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@@ -14321,97 +14393,97 @@
       "fresh_pointer_rebind_verified": true,
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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@@ -14435,24 +14507,24 @@
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@@ -14461,44 +14533,44 @@
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@@ -14507,33 +14579,33 @@
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@@ -14550,31 +14622,31 @@
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@@ -14588,68 +14660,71 @@
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@@ -14658,24 +14733,24 @@
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@@ -14687,18 +14762,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -14706,10 +14781,10 @@
         "source_read_occurred": false
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@@ -14718,46 +14793,46 @@
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       "candidate_public_raw_timing_diagnostics": {
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@@ -14765,31 +14840,31 @@
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@@ -14803,99 +14878,99 @@
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@@ -14917,20 +14992,20 @@
         "candidate_public_raw",
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         "candidate_precomputed",
+        "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -14942,66 +15017,66 @@
           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -15025,24 +15100,24 @@
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@@ -15051,44 +15126,44 @@
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@@ -15097,33 +15172,33 @@
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@@ -15140,31 +15215,31 @@
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@@ -15248,24 +15326,24 @@
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@@ -15277,18 +15355,18 @@
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@@ -15296,10 +15374,10 @@
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@@ -15308,46 +15386,46 @@
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@@ -15355,31 +15433,31 @@
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@@ -15520,7 +15598,7 @@
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@@ -15544,54 +15622,54 @@
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@@ -15641,44 +15719,44 @@
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@@ -15838,24 +15919,24 @@
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@@ -15867,18 +15948,18 @@
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@@ -15886,10 +15967,10 @@
         "source_read_occurred": false
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@@ -15898,46 +15979,46 @@
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@@ -15945,31 +16026,31 @@
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@@ -15983,99 +16064,99 @@
           "code_cache_state": "process_order_dependent",
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@@ -16103,14 +16184,14 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
-        "baseline_public_raw"
+        "baseline_public_raw",
+        "baseline_precomputed",
+        "candidate_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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@@ -16128,60 +16209,60 @@
           "baseline_public_raw",
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           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "candidate_public_raw",
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-        "measurement_schedule_sha256": "267ec1de0575b2dfbdca51b7c507db887289b7d64fa602107b49719bbaef8931",
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         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 2662
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.6559470920840065,
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.5848160773149538,
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -16205,24 +16286,24 @@
       "D": 288,
       "K": 512,
       "N": 1920,
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@@ -16231,44 +16312,44 @@
           "median": 2.0
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -16277,33 +16358,33 @@
           "median": 1.0
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@@ -16320,31 +16401,31 @@
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@@ -16358,68 +16439,71 @@
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@@ -16428,24 +16512,24 @@
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@@ -16457,18 +16541,18 @@
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@@ -16476,10 +16560,10 @@
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@@ -16488,46 +16572,46 @@
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@@ -16535,31 +16619,31 @@
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@@ -16573,99 +16657,99 @@
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@@ -16687,6 +16771,8 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
         "baseline_precomputed",
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@@ -16694,13 +16780,11 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_public_raw",
-        "baseline_public_raw",
-        "baseline_precomputed",
-        "candidate_precomputed"
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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@@ -16712,6 +16796,8 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "candidate_public_raw",
+          "baseline_public_raw",
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@@ -16719,59 +16805,57 @@
           "candidate_precomputed",
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           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
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@@ -16821,44 +16905,44 @@
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@@ -16867,33 +16951,33 @@
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@@ -16910,31 +16994,31 @@
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@@ -16948,68 +17032,71 @@
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@@ -17018,24 +17105,24 @@
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@@ -17047,18 +17134,18 @@
         "root_dispatch_traversal_count": 0,
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         "stable_direct_launcher_tokens": [
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@@ -17066,10 +17153,10 @@
         "source_read_occurred": false
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@@ -17078,46 +17165,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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@@ -17125,31 +17212,31 @@
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+              "including_init_synchronized_e2e_ms_per_call": 0.539795379,
               "public_call_count": 1000
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           ],
@@ -17163,99 +17250,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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           "gpu_span_ms": {
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-            "median": 0.047329,
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-            "p90": 0.052582399999999994,
-            "sample_count": 2138
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+            "p90": 0.043296,
+            "sample_count": 2333
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           "host_enqueue_ms": {
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-            "min": 0.062048,
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           "synchronized_e2e_ms": {
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-            "min": 0.099937,
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-          "sample_id": "3462c70f2aa84e4793077c9e9ca68837",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
+        "measurement_session_id": "a591a388bda74a2890fb7b17b61b2608",
         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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@@ -17281,16 +17368,16 @@
         "baseline_public_raw",
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         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "baseline_precomputed",
+        "candidate_precomputed",
         "candidate_precomputed",
         "baseline_precomputed"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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       "paired_cupti_session": {
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@@ -17306,62 +17393,62 @@
           "baseline_public_raw",
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           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
+          "baseline_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -17385,24 +17472,24 @@
       "D": 416,
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@@ -17411,44 +17498,44 @@
           "median": 2.0
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@@ -17457,33 +17544,33 @@
           "median": 1.0
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@@ -17500,31 +17587,31 @@
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@@ -17538,68 +17625,71 @@
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@@ -17608,24 +17698,24 @@
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@@ -17637,18 +17727,18 @@
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@@ -17656,10 +17746,10 @@
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@@ -17668,46 +17758,46 @@
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@@ -17715,31 +17805,31 @@
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@@ -17753,99 +17843,99 @@
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@@ -17880,7 +17970,7 @@
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@@ -17904,54 +17994,54 @@
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@@ -17975,24 +18065,24 @@
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@@ -18001,44 +18091,44 @@
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@@ -18047,33 +18137,33 @@
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@@ -18090,31 +18180,31 @@
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@@ -18128,68 +18218,71 @@
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@@ -18198,24 +18291,24 @@
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@@ -18227,18 +18320,18 @@
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@@ -18246,10 +18339,10 @@
         "source_read_occurred": false
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@@ -18258,46 +18351,46 @@
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@@ -18305,31 +18398,31 @@
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@@ -18343,99 +18436,99 @@
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@@ -18463,14 +18556,14 @@
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         "baseline_precomputed",
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@@ -18488,60 +18581,60 @@
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@@ -18565,24 +18658,24 @@
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@@ -18591,44 +18684,44 @@
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@@ -18637,33 +18730,33 @@
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@@ -18680,31 +18773,31 @@
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@@ -18718,68 +18811,71 @@
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@@ -18788,24 +18884,24 @@
           "median": 2.0
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       "candidate_prepared_path_proof": {
@@ -18817,18 +18913,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc295a9760",
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282a31a0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc295c3230",
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-      "candidate_public_raw_bench_iters": 3364,
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       "candidate_public_raw_cold_first_call_activity": {
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@@ -18836,10 +18932,10 @@
         "source_read_occurred": false
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       "candidate_public_raw_norm_compute_fields": [
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@@ -18848,46 +18944,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_tflops_from_gpu_span": 20.456323699421965,
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@@ -18895,31 +18991,31 @@
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@@ -18933,99 +19029,99 @@
           "code_cache_state": "process_order_dependent",
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@@ -19047,6 +19143,8 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
         "baseline_precomputed",
@@ -19054,13 +19152,11 @@
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed"
+        "candidate_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -19072,6 +19168,8 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "candidate_public_raw",
+          "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
           "baseline_precomputed",
@@ -19079,59 +19177,57 @@
           "candidate_public_raw",
           "baseline_public_raw",
           "baseline_precomputed",
-          "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed"
+          "candidate_precomputed"
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-        "measurement_schedule_sha256": "9f9755238851e0bf178eae8fc437eb4f7bd04b55b7b9c28493b55241cf41b79c",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
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-        "public_pair_count": 3364,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 4882
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       },
-      "paired_cupti_session_id": "3b3cb0beb21c413cab220416f38fa203:adjacent_68cf_d48_boundary_b4_n2304_k512_d48",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.7914798206278028,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7512888805819042,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 2.43728595890411,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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-        "hot_synchronized_e2e_speedup": 1.7512888805819042,
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -19155,24 +19251,24 @@
       "D": 112,
       "K": 4096,
       "N": 384,
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-      "baseline_07cf_adapter_submission_ms": 0.1418085,
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+      "baseline_07cf_adapter_gpu_span_ms": 0.089088,
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       "baseline_07cf_adapter_timing_backend": "cupti",
       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -19181,44 +19277,44 @@
           "median": 2.0
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@@ -19227,33 +19323,33 @@
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@@ -19270,31 +19366,31 @@
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@@ -19308,68 +19404,71 @@
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@@ -19378,24 +19477,24 @@
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@@ -19407,18 +19506,18 @@
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@@ -19426,10 +19525,10 @@
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@@ -19484,31 +19583,31 @@
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@@ -19644,12 +19743,12 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_public_raw",
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@@ -19669,58 +19768,58 @@
           "candidate_public_raw",
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           "baseline_precomputed",
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@@ -19770,44 +19869,44 @@
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@@ -19816,33 +19915,33 @@
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@@ -19859,31 +19958,31 @@
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@@ -19897,68 +19996,71 @@
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@@ -19967,24 +20069,24 @@
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@@ -19996,18 +20098,18 @@
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@@ -20015,10 +20117,10 @@
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@@ -20074,31 +20176,31 @@
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@@ -20112,99 +20214,99 @@
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@@ -20239,7 +20341,7 @@
       ],
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@@ -20263,54 +20365,54 @@
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -20334,24 +20436,24 @@
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@@ -20360,44 +20462,44 @@
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@@ -20406,33 +20508,33 @@
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@@ -20557,24 +20662,24 @@
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@@ -20586,18 +20691,18 @@
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@@ -20605,10 +20710,10 @@
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@@ -20617,46 +20722,46 @@
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@@ -20664,31 +20769,31 @@
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@@ -20829,7 +20934,7 @@
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@@ -20853,54 +20958,54 @@
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@@ -21147,24 +21255,24 @@
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@@ -21176,18 +21284,18 @@
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@@ -21195,10 +21303,10 @@
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@@ -21207,46 +21315,46 @@
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@@ -21254,31 +21362,31 @@
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-              "including_init_host_enqueue_ms_per_call": 0.112852711,
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+              "including_init_synchronized_e2e_ms_per_call": 0.132122795,
               "public_call_count": 1000
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           ],
@@ -21292,99 +21400,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
-          "host_enqueue_ms": 2.003883,
-          "synchronized_e2e_ms": 2.025611,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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           "gpu_span_ms": {
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-            "median": 0.033921,
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-            "p90": 0.037248,
-            "sample_count": 2676
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+            "min": 0.03152,
+            "p90": 0.03232,
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           "host_enqueue_ms": {
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-            "p90": 0.099297,
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           "synchronized_e2e_ms": {
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+            "p90": 0.10425920000000004,
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-          "sample_id": "3b3cb0beb21c413cab220416f38fa203",
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-        "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
+        "measurement_session_id": "429dbdfd2f734f02819474b9385e8bb8",
         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -21410,16 +21518,16 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -21435,62 +21543,62 @@
           "baseline_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
           "baseline_precomputed",
-          "candidate_precomputed"
+          "candidate_precomputed",
+          "candidate_public_raw",
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-        "measurement_schedule_sha256": "aedf1033774401f170b07ae6f9ec6a89d7993545b4588cf537b2eb26608e751f",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 3919,
-        "public_pair_count": 2676,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 2640
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.8859357696566998,
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.6423966704081532,
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       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -21514,24 +21622,24 @@
       "D": 352,
       "K": 256,
       "N": 4096,
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-      "baseline_07cf_adapter_submission_ms": 0.149825,
-      "baseline_07cf_adapter_synchronized_e2e_ms": 0.167457,
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+      "baseline_07cf_adapter_submission_ms": 0.153728,
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       "baseline_07cf_adapter_timing_backend": "cupti",
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@@ -21540,44 +21648,44 @@
           "median": 2.0
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-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.073377,
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@@ -21586,33 +21694,33 @@
           "median": 1.0
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       "baseline_precomputed_norm_policy": "explicit_precomputed_outside_timing",
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@@ -21629,31 +21737,31 @@
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@@ -21737,24 +21848,24 @@
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@@ -21785,10 +21896,10 @@
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@@ -21844,31 +21955,31 @@
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@@ -21998,10 +22109,10 @@
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@@ -22009,7 +22120,7 @@
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@@ -22023,64 +22134,64 @@
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@@ -22176,33 +22287,33 @@
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@@ -22219,31 +22330,31 @@
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@@ -22327,24 +22441,24 @@
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@@ -22356,18 +22470,18 @@
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@@ -22375,10 +22489,10 @@
         "source_read_occurred": false
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@@ -22387,46 +22501,46 @@
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@@ -22434,31 +22548,31 @@
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@@ -22599,7 +22713,7 @@
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@@ -22623,54 +22737,54 @@
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@@ -22694,24 +22808,24 @@
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@@ -22720,44 +22834,44 @@
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@@ -22766,33 +22880,33 @@
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@@ -22809,31 +22923,31 @@
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@@ -22847,68 +22961,71 @@
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       "candidate_precomputed_output_policy": "preallocated_outside_timing",
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       "candidate_precomputed_timing_diagnostics": {
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@@ -22917,24 +23034,24 @@
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@@ -22946,18 +23063,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc02739c10"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc027162a0",
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@@ -22965,10 +23082,10 @@
         "source_read_occurred": false
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@@ -22976,46 +23093,46 @@
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       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -23023,31 +23140,31 @@
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@@ -23061,99 +23178,99 @@
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@@ -23183,12 +23300,12 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed"
+        "baseline_public_raw",
+        "candidate_public_raw"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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@@ -23208,58 +23325,58 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed"
+          "baseline_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 2.627881785480706,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.9688840610511569,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -23283,24 +23400,24 @@
       "D": 48,
       "K": 512,
       "N": 1792,
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@@ -23309,44 +23426,44 @@
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@@ -23355,33 +23472,33 @@
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@@ -23398,31 +23515,31 @@
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@@ -23506,24 +23626,24 @@
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@@ -23535,18 +23655,18 @@
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@@ -23554,10 +23674,10 @@
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@@ -23566,46 +23686,46 @@
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@@ -23613,31 +23733,31 @@
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@@ -23765,20 +23885,20 @@
         "candidate_public_raw",
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         "candidate_precomputed",
+        "baseline_public_raw",
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         "candidate_precomputed",
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-        "baseline_precomputed"
+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -23790,66 +23910,66 @@
           "candidate_public_raw",
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           "candidate_precomputed",
+          "baseline_public_raw",
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@@ -23873,24 +23993,24 @@
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@@ -23899,44 +24019,44 @@
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@@ -23945,33 +24065,33 @@
           "median": 1.0
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@@ -23988,31 +24108,31 @@
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@@ -24026,68 +24146,71 @@
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@@ -24096,24 +24219,24 @@
           "median": 2.0
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         "lane_primary_metric": "gpu_span_ms",
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@@ -24125,18 +24248,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc297fc7d0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282c6600",
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-      "candidate_public_raw_bench_iters": 3165,
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       "candidate_public_raw_cold_first_call_activity": {
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@@ -24144,10 +24267,10 @@
         "source_read_occurred": true
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@@ -24156,46 +24279,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_tflops_from_gpu_span": 67.09807150595883,
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@@ -24203,31 +24326,31 @@
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@@ -24241,99 +24364,99 @@
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@@ -24359,16 +24482,16 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
+        "candidate_precomputed",
+        "baseline_precomputed",
         "candidate_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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@@ -24384,62 +24507,62 @@
           "candidate_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
           "baseline_precomputed",
+          "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.006611570247934,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.700332692041964,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -24463,24 +24586,24 @@
       "D": 128,
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       "N": 8064,
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@@ -24489,44 +24612,44 @@
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -24535,33 +24658,33 @@
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@@ -24578,31 +24701,31 @@
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@@ -24616,68 +24739,71 @@
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@@ -24686,24 +24812,24 @@
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@@ -24715,18 +24841,18 @@
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@@ -24734,10 +24860,10 @@
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@@ -24746,46 +24872,46 @@
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@@ -24793,31 +24919,31 @@
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@@ -24958,7 +25084,7 @@
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@@ -24982,54 +25108,54 @@
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@@ -25115,8 +25241,8 @@
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@@ -25137,21 +25263,21 @@
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@@ -25168,31 +25294,31 @@
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@@ -25206,57 +25332,60 @@
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@@ -25266,8 +25395,8 @@
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@@ -25276,24 +25405,24 @@
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@@ -25305,18 +25434,18 @@
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@@ -25324,10 +25453,10 @@
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@@ -25336,46 +25465,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
-      "candidate_public_raw_submission_ms": 0.077473,
-      "candidate_public_raw_synchronized_e2e_ms": 0.093344,
-      "candidate_public_raw_tflops_from_gpu_span": 35.84875213675214,
+      "candidate_public_raw_submission_ms": 0.046368,
+      "candidate_public_raw_synchronized_e2e_ms": 0.070048,
+      "candidate_public_raw_tflops_from_gpu_span": 40.721398058252426,
       "candidate_public_raw_timing_backend": "cupti",
       "candidate_public_raw_timing_diagnostics": {
         "active_union_ms": {
-          "median": 0.022465
+          "median": 0.02304
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           "median": 3.0
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         "cold_first_call": {
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-          "synchronized_e2e_ms": 0.149761
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         "correlated_kernel_activity_count": {
           "median": 3.0
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         "correlated_launch_activity_count": {
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       "candidate_public_raw_total_launch_count": 3,
@@ -25383,31 +25512,31 @@
         "amortization": {
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-              "including_init_host_enqueue_ms_per_call": 40.141535,
-              "including_init_synchronized_e2e_ms_per_call": 448.07001599999995,
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+              "after_init_synchronized_e2e_ms_per_call": 2.232675,
+              "including_init_host_enqueue_ms_per_call": 38.044199,
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-              "including_init_host_enqueue_ms_per_call": 4.0838792,
-              "including_init_synchronized_e2e_ms_per_call": 44.891011199999994,
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-              "including_init_synchronized_e2e_ms_per_call": 4.57311072,
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+              "after_init_synchronized_e2e_ms_per_call": 0.072210627,
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@@ -25421,99 +25550,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 2.178412,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
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       "cold_baseline_precomputed_fresh_pointer": {
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       "cold_measurement_order": [
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@@ -25537,10 +25666,10 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
+        "baseline_precomputed",
+        "candidate_precomputed",
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
@@ -25548,7 +25677,7 @@
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -25562,64 +25691,64 @@
           "candidate_precomputed",
           "baseline_precomputed",
           "candidate_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
+          "baseline_precomputed",
+          "candidate_precomputed",
           "candidate_precomputed",
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           "candidate_precomputed",
           "baseline_precomputed"
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 9797,
-        "public_pair_count": 3522,
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-          "candidate_precomputed": 9797,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 5330
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       },
-      "paired_cupti_session_id": "bb057d64f5dd4a68a07fac499aa57dd5:adjacent_9ca0_d224_guard_overlap_b2_n4096_k256_d224",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.7024608501118568,
+      "precomputed_gpu_speedup_vs_07cf": 0.6977777777777777,
       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7531817792252313,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 2.5194152581087255,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -25643,24 +25772,24 @@
       "D": 288,
       "K": 4096,
       "N": 384,
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@@ -25669,44 +25798,44 @@
           "median": 2.0
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -25715,33 +25844,33 @@
           "median": 1.0
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@@ -25866,24 +25998,24 @@
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@@ -25895,18 +26027,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -25914,10 +26046,10 @@
         "source_read_occurred": true
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@@ -25925,46 +26057,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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@@ -25972,31 +26104,31 @@
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@@ -26010,99 +26142,99 @@
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@@ -26118,97 +26250,97 @@
       "fresh_pointer_rebind_verified": true,
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@@ -26347,31 +26479,31 @@
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@@ -26385,57 +26517,60 @@
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@@ -26445,8 +26580,8 @@
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@@ -26455,24 +26590,24 @@
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@@ -26484,18 +26619,18 @@
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@@ -26503,10 +26638,10 @@
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@@ -26514,46 +26649,46 @@
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@@ -26561,31 +26696,31 @@
         "amortization": {
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@@ -26599,99 +26734,99 @@
           "code_cache_state": "process_order_dependent",
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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@@ -26717,16 +26852,16 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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       "paired_cupti_session": {
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@@ -26742,62 +26877,62 @@
           "candidate_public_raw",
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           "baseline_precomputed",
-          "candidate_precomputed",
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           "candidate_public_raw",
           "baseline_public_raw",
           "candidate_precomputed",
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-        "measurement_schedule_sha256": "53c8b5eb530c9dad06eae9c96401e9dbd15c94c159d660d84cc318eb18e08e4e",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 3.04313932860262,
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       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -26821,24 +26956,24 @@
       "D": 416,
       "K": 4096,
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@@ -26847,44 +26982,44 @@
           "median": 2.0
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@@ -26893,33 +27028,33 @@
           "median": 1.0
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@@ -26936,31 +27071,31 @@
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@@ -26974,68 +27109,71 @@
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@@ -27044,24 +27182,24 @@
           "median": 3.0
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@@ -27073,18 +27211,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc282a2390"
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@@ -27092,10 +27230,10 @@
         "source_read_occurred": false
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@@ -27103,46 +27241,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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-      "candidate_public_raw_tflops_from_gpu_span": 98.77889855072463,
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@@ -27150,31 +27288,31 @@
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@@ -27188,99 +27326,99 @@
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@@ -27302,20 +27440,20 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
-        "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
+        "candidate_precomputed",
         "baseline_precomputed",
         "baseline_public_raw",
         "candidate_public_raw"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -27327,66 +27465,66 @@
           "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
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-          "candidate_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
-          "candidate_precomputed",
           "baseline_precomputed",
           "candidate_precomputed",
+          "baseline_public_raw",
+          "candidate_public_raw",
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           "baseline_public_raw",
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@@ -27482,33 +27620,33 @@
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@@ -27525,31 +27663,31 @@
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@@ -27633,24 +27774,24 @@
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@@ -27662,18 +27803,18 @@
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@@ -27681,10 +27822,10 @@
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@@ -27693,46 +27834,46 @@
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@@ -27740,31 +27881,31 @@
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+              "including_init_synchronized_e2e_ms_per_call": 0.574056888,
               "public_call_count": 1000
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           ],
@@ -27778,99 +27919,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 2.0371,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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           "gpu_span_ms": {
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-            "median": 0.044065,
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-            "p90": 0.0453123,
-            "sample_count": 2258
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+            "sample_count": 2508
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           "host_enqueue_ms": {
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           "synchronized_e2e_ms": {
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_baseline_public_raw_shape_miss": {
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@@ -27898,14 +28039,14 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
-        "baseline_public_raw"
+        "baseline_public_raw",
+        "candidate_precomputed",
+        "baseline_precomputed"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
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@@ -27923,60 +28064,60 @@
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "candidate_public_raw",
-          "baseline_public_raw"
+          "baseline_public_raw",
+          "candidate_precomputed",
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-        "measurement_schedule_sha256": "21e6d67dee48ddf1c7ebc66cf12a0c975e66920a9129b8d2f09942a00ec39cef",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 4341,
-        "public_pair_count": 2258,
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         "schema": "flash-kmeans-interleaved-cupti-session-v1",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.8759124087591241,
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.4842113515931616,
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       "route_matches_expected": true,
       "runtime_coverage": false,
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -28000,24 +28141,24 @@
       "D": 48,
       "K": 512,
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       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -28026,44 +28167,44 @@
           "median": 2.0
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-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.075808,
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -28072,33 +28213,33 @@
           "median": 1.0
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@@ -28115,31 +28256,31 @@
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@@ -28223,24 +28367,24 @@
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@@ -28252,18 +28396,18 @@
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@@ -28271,10 +28415,10 @@
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@@ -28283,46 +28427,46 @@
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@@ -28330,31 +28474,31 @@
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@@ -28495,7 +28639,7 @@
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@@ -28519,54 +28663,54 @@
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@@ -28616,44 +28760,44 @@
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@@ -28662,33 +28806,33 @@
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@@ -28705,31 +28849,31 @@
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@@ -28813,24 +28960,24 @@
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@@ -28842,18 +28989,18 @@
         "root_dispatch_traversal_count": 0,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04a4fc80"
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@@ -28861,10 +29008,10 @@
         "source_read_occurred": false
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@@ -28873,46 +29020,46 @@
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@@ -28920,31 +29067,31 @@
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-          "sample_id": "3462c70f2aa84e4793077c9e9ca68837",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -29068,24 +29215,24 @@
       "measurement_order": [
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         "candidate_precomputed",
-        "candidate_precomputed",
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         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
+        "baseline_precomputed",
+        "candidate_precomputed",
+        "baseline_precomputed",
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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       "paired_cupti_session": {
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@@ -29093,70 +29240,70 @@
         "first_reportable_roles": [
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           "candidate_precomputed",
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           "candidate_public_raw",
           "baseline_public_raw",
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -29180,24 +29327,24 @@
       "D": 128,
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@@ -29206,44 +29353,44 @@
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@@ -29252,33 +29399,33 @@
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@@ -29295,31 +29442,31 @@
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@@ -29333,68 +29480,71 @@
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@@ -29403,24 +29553,24 @@
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@@ -29432,18 +29582,18 @@
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@@ -29451,10 +29601,10 @@
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@@ -29463,46 +29613,46 @@
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@@ -29510,31 +29660,31 @@
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@@ -29548,99 +29698,99 @@
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@@ -29675,7 +29825,7 @@
       ],
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@@ -29699,54 +29849,54 @@
           "candidate_precomputed"
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@@ -29770,24 +29920,24 @@
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@@ -29796,44 +29946,44 @@
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@@ -29842,33 +29992,33 @@
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@@ -29885,31 +30035,31 @@
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@@ -29993,24 +30146,24 @@
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@@ -30022,18 +30175,18 @@
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@@ -30041,10 +30194,10 @@
         "source_read_occurred": false
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@@ -30053,46 +30206,46 @@
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@@ -30100,31 +30253,31 @@
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@@ -30138,99 +30291,99 @@
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@@ -30252,20 +30405,20 @@
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+        "baseline_precomputed",
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         "candidate_public_raw",
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+        "candidate_precomputed",
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@@ -30277,66 +30430,66 @@
           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -30360,24 +30513,24 @@
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@@ -30386,44 +30539,44 @@
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@@ -30432,33 +30585,33 @@
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@@ -30475,31 +30628,31 @@
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@@ -30513,68 +30666,71 @@
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       "candidate_precomputed_output_policy": "preallocated_outside_timing",
-      "candidate_precomputed_submission_ms": 0.048865,
-      "candidate_precomputed_synchronized_e2e_ms": 0.05984,
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       "candidate_precomputed_timing_backend": "cupti",
       "candidate_precomputed_timing_diagnostics": {
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         "cold_first_call": {
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@@ -30583,24 +30739,24 @@
           "median": 2.0
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+          "median": 0.021376
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         "lane_primary_metric": "gpu_span_ms",
-        "sample_count": 4853,
+        "sample_count": 4819,
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       "candidate_prepared_path_proof": {
@@ -30612,18 +30768,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb66e83d10",
-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb66e82090"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0042a4e0",
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0042bda0"
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       "candidate_public_prepared_ratios": {
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-        "submission": 1.6207919778982913,
-        "synchronized_e2e": 1.6459893048128342
+        "gpu_span": 1.2664670658682635,
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-      "candidate_public_raw_bench_iters": 2575,
+      "candidate_public_raw_bench_iters": 3743,
       "candidate_public_raw_cold_first_call_activity": {
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         "nvrtc_compile_occurred": false,
@@ -30631,10 +30787,10 @@
         "source_read_occurred": false
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       "candidate_public_raw_fresh_pointer_cache_hit": true,
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-      "candidate_public_raw_inter_kernel_gap_ms": 0.00416,
-      "candidate_public_raw_kernel_sum_ms": 0.027041,
+      "candidate_public_raw_gpu_span_ms": 0.027072,
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       "candidate_public_raw_norm_compute_fields": [
         "c_sq"
       ],
@@ -30642,46 +30798,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.098496,
-      "candidate_public_raw_tflops_from_gpu_span": 48.44550308008213,
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       "candidate_public_raw_timing_backend": "cupti",
       "candidate_public_raw_timing_diagnostics": {
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         "cold_first_call": {
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         "correlated_launch_activity_count": {
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       "candidate_public_raw_total_launch_count": 3,
@@ -30689,31 +30845,31 @@
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+              "after_init_synchronized_e2e_ms_per_call": 2.833123,
+              "including_init_host_enqueue_ms_per_call": 40.158986,
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-              "including_init_host_enqueue_ms_per_call": 4.1227298,
-              "including_init_synchronized_e2e_ms_per_call": 4.1503618,
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@@ -30727,99 +30883,99 @@
           "code_cache_state": "process_order_dependent",
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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@@ -30841,6 +30997,8 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
         "baseline_public_raw",
@@ -30848,13 +31006,11 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed",
-        "baseline_public_raw",
-        "candidate_public_raw"
+        "baseline_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
+      "measurement_session_id": "429dbdfd2f734f02819474b9385e8bb8",
       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -30866,6 +31022,8 @@
           "baseline_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "baseline_public_raw",
+          "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
           "baseline_public_raw",
@@ -30873,59 +31031,57 @@
           "candidate_precomputed",
           "baseline_precomputed",
           "candidate_precomputed",
-          "baseline_precomputed",
-          "baseline_public_raw",
-          "candidate_public_raw"
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-        "measurement_schedule_sha256": "b5027d77c0c18b0cf1912dc80f93aec7df27e4690aff4d3ae89b7841ff8e0e77",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 2972
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 5.535168195718655,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 2.485715155945419,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 3.2127220156959937,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -30949,24 +31105,24 @@
       "D": 352,
       "K": 256,
       "N": 1024,
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-      "baseline_07cf_adapter_submission_ms": 0.152993,
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+      "baseline_07cf_adapter_gpu_span_ms": 0.054368,
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       "baseline_07cf_adapter_timing_backend": "cupti",
       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -30975,44 +31131,44 @@
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@@ -31021,33 +31177,33 @@
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@@ -31064,31 +31220,31 @@
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@@ -31102,68 +31258,71 @@
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@@ -31172,24 +31331,24 @@
           "median": 2.0
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@@ -31201,18 +31360,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -31220,10 +31379,10 @@
         "source_read_occurred": false
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@@ -31232,46 +31391,46 @@
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@@ -31279,31 +31438,31 @@
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@@ -31317,99 +31476,99 @@
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@@ -31433,18 +31592,18 @@
         "candidate_precomputed",
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         "baseline_public_raw",
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         "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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       "paired_cupti_session": {
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@@ -31458,64 +31617,64 @@
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -31539,24 +31698,24 @@
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@@ -31565,44 +31724,44 @@
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@@ -31611,33 +31770,33 @@
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@@ -31654,31 +31813,31 @@
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@@ -31692,68 +31851,71 @@
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@@ -31762,24 +31924,24 @@
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@@ -31791,18 +31953,18 @@
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         "scratch_reused": true,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0447cc20"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb7dcd6f30",
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       "candidate_public_raw_cold_first_call_activity": {
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@@ -31810,10 +31972,10 @@
         "source_read_occurred": false
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@@ -31822,46 +31984,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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       "candidate_public_raw_shape_first_was_cache_hit": false,
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@@ -31869,31 +32031,31 @@
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@@ -31907,99 +32069,99 @@
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@@ -32021,10 +32183,10 @@
         "baseline_public_raw",
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         "candidate_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "baseline_precomputed",
+        "candidate_precomputed",
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@@ -32034,7 +32196,7 @@
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-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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@@ -32046,10 +32208,10 @@
           "baseline_public_raw",
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           "candidate_precomputed",
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-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
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@@ -32058,54 +32220,54 @@
           "baseline_precomputed"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.0921465968586388,
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@@ -32129,24 +32291,24 @@
       "D": 480,
       "K": 4096,
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@@ -32155,44 +32317,44 @@
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -32201,33 +32363,33 @@
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@@ -32244,31 +32406,31 @@
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@@ -32352,24 +32517,24 @@
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@@ -32381,18 +32546,18 @@
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@@ -32400,10 +32565,10 @@
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@@ -32411,46 +32576,46 @@
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@@ -32458,31 +32623,31 @@
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@@ -32618,12 +32783,12 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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@@ -32643,58 +32808,58 @@
           "baseline_public_raw",
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           "baseline_precomputed",
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+          "candidate_public_raw",
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@@ -32718,13 +32883,13 @@
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@@ -32734,8 +32899,8 @@
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@@ -32744,44 +32909,44 @@
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@@ -32790,33 +32955,33 @@
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@@ -32833,31 +32998,31 @@
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@@ -32871,68 +33036,71 @@
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@@ -32941,24 +33109,24 @@
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@@ -32970,18 +33138,18 @@
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@@ -32989,10 +33157,10 @@
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@@ -33001,9 +33169,9 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.093217,
-      "candidate_public_raw_tflops_from_gpu_span": 6.184262123197903,
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@@ -33013,34 +33181,34 @@
           "median": 3.0
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@@ -33048,31 +33216,31 @@
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@@ -33086,99 +33254,99 @@
           "code_cache_state": "process_order_dependent",
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           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
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@@ -33194,18 +33362,18 @@
       "fresh_pointer_rebind_verified": true,
       "label": "adjacent_a2f8_d48_k1024_boundary_b2_n768_k1024_d48",
       "measurement_order": [
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-        "candidate_precomputed",
         "candidate_public_raw",
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         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "candidate_precomputed",
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+        "baseline_public_raw",
         "candidate_precomputed",
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         "candidate_public_raw",
         "baseline_public_raw",
         "baseline_precomputed",
@@ -33213,78 +33381,78 @@
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
+      "measurement_session_id": "429dbdfd2f734f02819474b9385e8bb8",
       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
         "adjacent_candidate_baseline_pairs": true,
         "first_reportable_roles": [
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           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.1777528355387525,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7610628962528296,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -33308,24 +33476,24 @@
       "D": 112,
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@@ -33334,44 +33502,44 @@
           "median": 2.0
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@@ -33380,33 +33548,33 @@
           "median": 1.0
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@@ -33531,24 +33702,24 @@
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@@ -33560,18 +33731,18 @@
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@@ -33579,10 +33750,10 @@
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@@ -33591,46 +33762,46 @@
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@@ -33638,31 +33809,31 @@
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@@ -33784,18 +33955,18 @@
       "fresh_pointer_rebind_verified": true,
       "label": "adjacent_c44f_d112_odd_tail_b2_n3200_k768_d112",
       "measurement_order": [
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@@ -33803,78 +33974,78 @@
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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@@ -33898,24 +34069,24 @@
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@@ -33924,44 +34095,44 @@
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@@ -33970,33 +34141,33 @@
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@@ -34013,31 +34184,31 @@
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@@ -34051,68 +34222,71 @@
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@@ -34121,24 +34295,24 @@
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@@ -34150,18 +34324,18 @@
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         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb720d3980"
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@@ -34169,10 +34343,10 @@
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@@ -34181,46 +34355,46 @@
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@@ -34228,31 +34402,31 @@
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@@ -34393,7 +34567,7 @@
       ],
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@@ -34417,54 +34591,54 @@
           "candidate_precomputed"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -34488,24 +34662,24 @@
       "D": 224,
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@@ -34514,44 +34688,44 @@
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@@ -34560,33 +34734,33 @@
           "median": 1.0
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@@ -34603,31 +34777,31 @@
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@@ -34641,68 +34815,71 @@
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@@ -34711,24 +34888,24 @@
           "median": 2.0
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@@ -34740,18 +34917,18 @@
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@@ -34759,10 +34936,10 @@
         "source_read_occurred": false
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@@ -34771,46 +34948,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
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@@ -34818,31 +34995,31 @@
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@@ -34856,99 +35033,99 @@
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@@ -34978,12 +35155,12 @@
         "baseline_precomputed",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed"
+        "candidate_public_raw",
+        "baseline_public_raw"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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@@ -35003,58 +35180,58 @@
           "baseline_precomputed",
           "candidate_precomputed",
           "baseline_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed"
+          "candidate_public_raw",
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-        "public_pair_count": 2385,
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@@ -35193,31 +35370,31 @@
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@@ -35301,24 +35481,24 @@
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@@ -35330,18 +35510,18 @@
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@@ -35349,10 +35529,10 @@
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@@ -35360,46 +35540,46 @@
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@@ -35407,31 +35587,31 @@
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@@ -35572,7 +35752,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -35596,54 +35776,54 @@
           "candidate_precomputed"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 2.165090283748925,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -35667,24 +35847,24 @@
       "D": 352,
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@@ -35693,44 +35873,44 @@
           "median": 2.0
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@@ -35739,33 +35919,33 @@
           "median": 1.0
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@@ -35782,31 +35962,31 @@
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@@ -35820,68 +36000,71 @@
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@@ -35890,24 +36073,24 @@
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@@ -35919,18 +36102,18 @@
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@@ -35938,10 +36121,10 @@
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@@ -35950,46 +36133,46 @@
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@@ -35997,31 +36180,31 @@
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@@ -36035,99 +36218,99 @@
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@@ -36149,20 +36332,20 @@
         "baseline_public_raw",
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@@ -36174,66 +36357,66 @@
           "baseline_public_raw",
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -36283,44 +36466,44 @@
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@@ -36329,33 +36512,33 @@
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@@ -36372,31 +36555,31 @@
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@@ -36410,68 +36593,71 @@
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@@ -36480,24 +36666,24 @@
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@@ -36509,18 +36695,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb7d48db20"
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@@ -36528,10 +36714,10 @@
         "source_read_occurred": false
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@@ -36539,46 +36725,46 @@
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@@ -36586,31 +36772,31 @@
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@@ -36624,99 +36810,99 @@
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@@ -36738,10 +36924,10 @@
         "baseline_public_raw",
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         "baseline_precomputed",
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-        "baseline_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "candidate_precomputed",
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@@ -36751,7 +36937,7 @@
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@@ -36763,10 +36949,10 @@
           "baseline_public_raw",
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@@ -36775,54 +36961,54 @@
           "candidate_precomputed"
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@@ -36846,24 +37032,24 @@
       "D": 480,
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@@ -36872,44 +37058,44 @@
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@@ -36918,33 +37104,33 @@
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@@ -36961,31 +37147,31 @@
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@@ -36999,68 +37185,71 @@
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@@ -37072,21 +37261,21 @@
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@@ -37098,18 +37287,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04465a60"
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@@ -37117,10 +37306,10 @@
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@@ -37129,46 +37318,46 @@
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@@ -37176,31 +37365,31 @@
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@@ -37214,99 +37403,99 @@
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@@ -37328,12 +37517,12 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
+        "candidate_precomputed",
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         "candidate_precomputed",
@@ -37341,7 +37530,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -37353,66 +37542,66 @@
           "candidate_public_raw",
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           "baseline_public_raw",
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -37436,24 +37625,24 @@
       "D": 48,
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@@ -37462,44 +37651,44 @@
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@@ -37508,33 +37697,33 @@
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@@ -37551,31 +37740,31 @@
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@@ -37659,24 +37851,24 @@
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@@ -37688,18 +37880,18 @@
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@@ -37707,10 +37899,10 @@
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@@ -37719,46 +37911,46 @@
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@@ -37766,31 +37958,31 @@
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@@ -37804,99 +37996,99 @@
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@@ -37918,20 +38110,20 @@
         "candidate_public_raw",
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+        "candidate_public_raw",
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@@ -37943,66 +38135,66 @@
           "candidate_public_raw",
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@@ -38026,24 +38218,24 @@
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@@ -38052,44 +38244,44 @@
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@@ -38098,33 +38290,33 @@
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@@ -38141,31 +38333,31 @@
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@@ -38179,68 +38371,71 @@
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@@ -38249,24 +38444,24 @@
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@@ -38278,18 +38473,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04856030"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc01dba090",
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@@ -38297,10 +38492,10 @@
         "source_read_occurred": false
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@@ -38308,46 +38503,46 @@
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@@ -38355,31 +38550,31 @@
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@@ -38393,99 +38588,99 @@
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@@ -38520,7 +38715,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -38544,54 +38739,54 @@
           "candidate_public_raw"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -38615,24 +38810,24 @@
       "D": 128,
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@@ -38641,44 +38836,44 @@
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -38687,33 +38882,33 @@
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@@ -38730,31 +38925,31 @@
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@@ -38768,68 +38963,71 @@
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@@ -38838,24 +39036,24 @@
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@@ -38867,18 +39065,18 @@
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@@ -38886,10 +39084,10 @@
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@@ -38898,46 +39096,46 @@
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@@ -38945,31 +39143,31 @@
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@@ -38983,99 +39181,99 @@
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@@ -39110,7 +39308,7 @@
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@@ -39134,54 +39332,54 @@
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@@ -39205,24 +39403,24 @@
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@@ -39231,44 +39429,44 @@
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@@ -39277,33 +39475,33 @@
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@@ -39320,31 +39518,31 @@
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@@ -39358,68 +39556,71 @@
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@@ -39428,24 +39629,24 @@
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@@ -39457,18 +39658,18 @@
         "root_dispatch_traversal_count": 0,
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         "stable_direct_launcher_tokens": [
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@@ -39476,10 +39677,10 @@
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@@ -39488,46 +39689,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
-      "candidate_public_raw_submission_ms": 0.075009,
-      "candidate_public_raw_synchronized_e2e_ms": 0.097089,
-      "candidate_public_raw_tflops_from_gpu_span": 101.45476923076924,
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+      "candidate_public_raw_synchronized_e2e_ms": 0.078592,
+      "candidate_public_raw_tflops_from_gpu_span": 112.60721451440769,
       "candidate_public_raw_timing_backend": "cupti",
       "candidate_public_raw_timing_diagnostics": {
         "active_union_ms": {
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+          "median": 0.02992
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           "median": 3.0
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         "cold_first_call": {
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-          "synchronized_e2e_ms": 0.173345
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         "correlated_kernel_activity_count": {
           "median": 3.0
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       "candidate_public_raw_total_launch_count": 3,
@@ -39535,31 +39736,31 @@
         "amortization": {
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-              "including_init_host_enqueue_ms_per_call": 40.320864,
-              "including_init_synchronized_e2e_ms_per_call": 448.24924899999996,
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-              "including_init_host_enqueue_ms_per_call": 4.0995945,
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-              "including_init_host_enqueue_ms_per_call": 0.47746755,
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+              "after_init_synchronized_e2e_ms_per_call": 0.08123609899999999,
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+              "including_init_synchronized_e2e_ms_per_call": 0.565336312,
               "public_call_count": 1000
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           ],
@@ -39573,99 +39774,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 2.357645,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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-            "sample_count": 2439
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           "timing_backend": "cupti"
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-          "sample_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
+        "measurement_session_id": "958ecd22358d4d5cb8ab46b2ff2cd831",
         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_baseline_precomputed_first_pointer": {
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       "cold_baseline_precomputed_fresh_pointer": {
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       "cold_baseline_public_raw_fresh_pointer_hit": {
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       "cold_measurement_order": [
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@@ -39691,16 +39892,16 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -39716,62 +39917,62 @@
           "candidate_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
           "baseline_precomputed",
-          "candidate_precomputed"
+          "candidate_precomputed",
+          "baseline_public_raw",
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         "interleaved": true,
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-        "measurement_schedule_sha256": "a03332fc6adba4fbe2f996a2a3e1b9256b3dc50cd8c33e1b32f231c54bc61528",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
-        "precomputed_pair_count": 3839,
-        "public_pair_count": 2439,
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+        "public_pair_count": 3341,
         "reportable_cupti_session_count": 1,
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-          "candidate_precomputed": 3839,
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         "same_cupti_session": true,
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
-        "warmup_schedule_iteration_count": 2512
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       },
-      "paired_cupti_session_id": "bb057d64f5dd4a68a07fac499aa57dd5:adjacent_d9d5_d224_random_midk_b2_n2944_k1280_d224",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.7809239940387482,
+      "precomputed_gpu_speedup_vs_07cf": 1.7456395348837208,
       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7659776081739436,
+      "public_raw_e2e_speedup_vs_07cf_adapter": 2.380700325732899,
       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "schema": "loom-public-runtime-lifecycle-comparison-v1",
         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -39795,24 +39996,24 @@
       "D": 288,
       "K": 4096,
       "N": 896,
-      "baseline_07cf_adapter_bench_iters": 2635,
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+      "baseline_07cf_adapter_submission_ms": 0.161424,
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@@ -39821,44 +40022,44 @@
           "median": 2.0
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-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.167585,
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -39867,33 +40068,33 @@
           "median": 1.0
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@@ -39910,31 +40111,31 @@
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@@ -40008,8 +40212,8 @@
           "median": 2.0
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@@ -40018,24 +40222,24 @@
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@@ -40047,18 +40251,18 @@
         "root_dispatch_traversal_count": 0,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb66e81340"
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@@ -40066,10 +40270,10 @@
         "source_read_occurred": false
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@@ -40077,46 +40281,46 @@
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@@ -40124,31 +40328,31 @@
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@@ -40162,99 +40366,99 @@
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@@ -40276,20 +40480,20 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
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         "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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@@ -40410,44 +40614,44 @@
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@@ -40456,33 +40660,33 @@
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@@ -40499,31 +40703,31 @@
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@@ -40537,68 +40741,71 @@
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@@ -40607,24 +40814,24 @@
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@@ -40636,18 +40843,18 @@
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@@ -40655,10 +40862,10 @@
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@@ -40667,46 +40874,46 @@
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@@ -40714,31 +40921,31 @@
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@@ -40879,7 +41086,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -40903,54 +41110,54 @@
           "candidate_precomputed"
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 1.9190778221208669,
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.5738586659968647,
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@@ -40974,24 +41181,24 @@
       "D": 416,
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@@ -41000,44 +41207,44 @@
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@@ -41046,33 +41253,33 @@
           "median": 1.0
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@@ -41089,31 +41296,31 @@
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@@ -41197,24 +41407,24 @@
           "median": 3.0
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@@ -41226,18 +41436,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb7ee86240"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc02eb8ce0",
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@@ -41245,10 +41455,10 @@
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@@ -41256,46 +41466,46 @@
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@@ -41303,31 +41513,31 @@
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@@ -41341,99 +41551,99 @@
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@@ -41459,16 +41669,16 @@
         "baseline_public_raw",
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         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "candidate_precomputed",
+        "baseline_precomputed",
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@@ -41484,62 +41694,62 @@
           "baseline_public_raw",
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           "baseline_public_raw",
           "candidate_public_raw",
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -41635,33 +41845,33 @@
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@@ -41678,31 +41888,31 @@
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@@ -41786,24 +41999,24 @@
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@@ -41815,18 +42028,18 @@
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@@ -41834,10 +42047,10 @@
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@@ -41845,46 +42058,46 @@
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@@ -41892,31 +42105,31 @@
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@@ -42057,7 +42270,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -42081,54 +42294,54 @@
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -42152,24 +42365,24 @@
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@@ -42178,44 +42391,44 @@
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@@ -42224,33 +42437,33 @@
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@@ -42267,31 +42480,31 @@
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@@ -42305,68 +42518,71 @@
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@@ -42375,24 +42591,24 @@
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@@ -42404,18 +42620,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb66e68e00"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb7d24f560",
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@@ -42423,10 +42639,10 @@
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@@ -42435,46 +42651,46 @@
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@@ -42482,31 +42698,31 @@
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@@ -42520,99 +42736,99 @@
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@@ -42628,6 +42844,8 @@
       "fresh_pointer_rebind_verified": true,
       "label": "adjacent_d9d5_d48_highk_heldout_b2_n640_k4096_d48",
       "measurement_order": [
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+        "baseline_public_raw",
         "candidate_precomputed",
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@@ -42638,21 +42856,21 @@
         "baseline_public_raw",
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         "candidate_precomputed",
-        "candidate_public_raw",
         "baseline_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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         "adaptive_probes_reportable": false,
         "adjacent_candidate_baseline_pairs": true,
         "first_reportable_roles": [
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@@ -42663,62 +42881,60 @@
           "baseline_public_raw",
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           "candidate_precomputed",
-          "candidate_public_raw",
           "baseline_public_raw",
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@@ -42768,44 +42984,44 @@
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@@ -42814,33 +43030,33 @@
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@@ -42857,31 +43073,31 @@
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@@ -42965,24 +43184,24 @@
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@@ -42994,18 +43213,18 @@
         "root_dispatch_traversal_count": 0,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc02a1af90"
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@@ -43013,10 +43232,10 @@
         "source_read_occurred": false
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@@ -43025,46 +43244,46 @@
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@@ -43072,31 +43291,31 @@
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@@ -43110,99 +43329,99 @@
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@@ -43228,16 +43447,16 @@
         "candidate_public_raw",
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         "candidate_precomputed",
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@@ -43253,62 +43472,62 @@
           "candidate_public_raw",
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@@ -43332,24 +43551,24 @@
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@@ -43358,44 +43577,44 @@
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@@ -43404,33 +43623,33 @@
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@@ -43447,31 +43666,31 @@
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@@ -43485,68 +43704,71 @@
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@@ -43555,24 +43777,24 @@
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@@ -43584,18 +43806,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc044463c0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc047108f0",
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@@ -43603,10 +43825,10 @@
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@@ -43615,46 +43837,46 @@
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@@ -43662,31 +43884,31 @@
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@@ -43700,99 +43922,99 @@
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@@ -43827,7 +44049,7 @@
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@@ -43851,54 +44073,54 @@
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -43922,24 +44144,24 @@
       "D": 224,
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@@ -43948,44 +44170,44 @@
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@@ -43994,33 +44216,33 @@
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@@ -44037,31 +44259,31 @@
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@@ -44145,24 +44370,24 @@
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@@ -44174,18 +44399,18 @@
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@@ -44193,10 +44418,10 @@
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@@ -44205,46 +44430,46 @@
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@@ -44252,31 +44477,31 @@
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@@ -44404,12 +44629,12 @@
         "baseline_public_raw",
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@@ -44417,7 +44642,7 @@
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -44429,66 +44654,66 @@
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@@ -44512,24 +44737,24 @@
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@@ -44538,44 +44763,44 @@
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@@ -44584,33 +44809,33 @@
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@@ -44627,31 +44852,31 @@
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@@ -44665,68 +44890,71 @@
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@@ -44735,24 +44963,24 @@
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@@ -44764,18 +44992,18 @@
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@@ -44783,10 +45011,10 @@
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@@ -44841,31 +45069,31 @@
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@@ -44879,99 +45107,99 @@
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@@ -44997,16 +45225,16 @@
         "candidate_public_raw",
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         "candidate_precomputed",
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@@ -45022,62 +45250,62 @@
           "candidate_public_raw",
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           "candidate_precomputed",
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@@ -45101,24 +45329,24 @@
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@@ -45127,44 +45355,44 @@
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@@ -45173,33 +45401,33 @@
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@@ -45324,24 +45555,24 @@
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@@ -45372,10 +45603,10 @@
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@@ -45430,31 +45661,31 @@
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@@ -45595,7 +45826,7 @@
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@@ -45619,54 +45850,54 @@
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@@ -45690,24 +45921,24 @@
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@@ -45716,44 +45947,44 @@
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@@ -45762,33 +45993,33 @@
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@@ -45805,31 +46036,31 @@
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@@ -45843,68 +46074,71 @@
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@@ -45913,24 +46147,24 @@
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@@ -45942,18 +46176,18 @@
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@@ -45961,10 +46195,10 @@
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@@ -45973,46 +46207,46 @@
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@@ -46020,31 +46254,31 @@
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@@ -46058,99 +46292,99 @@
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@@ -46176,16 +46410,16 @@
         "candidate_public_raw",
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         "candidate_public_raw",
         "baseline_public_raw",
         "candidate_precomputed",
-        "baseline_precomputed"
+        "baseline_precomputed",
+        "candidate_public_raw",
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@@ -46201,62 +46435,62 @@
           "candidate_public_raw",
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           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -46280,24 +46514,24 @@
       "D": 480,
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@@ -46306,44 +46540,44 @@
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@@ -46352,33 +46586,33 @@
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@@ -46395,31 +46629,31 @@
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@@ -46503,24 +46740,24 @@
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@@ -46532,18 +46769,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04bbc2c0"
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@@ -46551,10 +46788,10 @@
         "source_read_occurred": false
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@@ -46563,46 +46800,46 @@
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       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -46610,31 +46847,31 @@
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@@ -46648,99 +46885,99 @@
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@@ -46764,18 +47001,18 @@
         "baseline_precomputed",
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         "baseline_precomputed",
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-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "baseline_precomputed",
+        "candidate_precomputed",
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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@@ -46789,64 +47026,64 @@
           "baseline_precomputed",
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-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
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@@ -47093,24 +47333,24 @@
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@@ -47122,18 +47362,18 @@
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@@ -47141,10 +47381,10 @@
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@@ -47153,46 +47393,46 @@
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@@ -47200,31 +47440,31 @@
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               "public_call_count": 100
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               "public_call_count": 1000
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           ],
@@ -47238,99 +47478,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
-          "host_enqueue_ms": 2.277676,
-          "synchronized_e2e_ms": 2.304876,
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           "timing_class": "cupti_timestamp_host_diagnostic"
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         "hot_compute": {
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-            "p90": 0.03358140000000002,
-            "sample_count": 2847
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+            "sample_count": 5947
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           "host_enqueue_ms": {
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           "synchronized_e2e_ms": {
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           "timing_backend": "cupti"
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_baseline_precomputed_first_pointer": {
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       "cold_baseline_public_raw_shape_miss": {
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -47348,6 +47588,8 @@
       "measurement_order": [
         "candidate_precomputed",
         "baseline_precomputed",
+        "baseline_public_raw",
+        "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
         "baseline_public_raw",
@@ -47356,8 +47598,6 @@
         "baseline_precomputed",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "candidate_precomputed",
@@ -47365,7 +47605,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
+      "measurement_session_id": "429dbdfd2f734f02819474b9385e8bb8",
       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -47373,6 +47613,8 @@
         "first_reportable_roles": [
           "candidate_precomputed",
           "baseline_precomputed",
+          "baseline_public_raw",
+          "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
           "baseline_public_raw",
@@ -47381,62 +47623,60 @@
           "baseline_precomputed",
           "candidate_precomputed",
           "baseline_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "baseline_public_raw",
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           "candidate_precomputed",
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-        "measurement_schedule_sha256": "8feeef8ceee50eb3bedcfc66da21a8c69bd140e8957619485abbcfb68189a5e1",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
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-        "public_pair_count": 2847,
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-          "candidate_precomputed": 8730,
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-        "warmup_schedule_iteration_count": 4632
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.8215102974828375,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7468569837357286,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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-        "hot_synchronized_e2e_speedup": 1.7468569837357286,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -47460,24 +47700,24 @@
       "D": 112,
       "K": 256,
       "N": 256,
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-      "baseline_07cf_adapter_submission_ms": 0.148225,
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+      "baseline_07cf_adapter_gpu_span_ms": 0.049792,
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+      "baseline_07cf_adapter_inter_kernel_gap_ms": 0.040864,
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+      "baseline_07cf_adapter_submission_ms": 0.145056,
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       "baseline_07cf_adapter_timing_backend": "cupti",
       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -47486,44 +47726,44 @@
           "median": 2.0
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-      "baseline_07cf_precomputed_synchronized_e2e_ms": 0.055584,
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -47532,33 +47772,33 @@
           "median": 1.0
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@@ -47575,31 +47815,31 @@
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@@ -47683,24 +47926,24 @@
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@@ -47712,18 +47955,18 @@
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@@ -47731,10 +47974,10 @@
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@@ -47742,46 +47985,46 @@
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@@ -47789,31 +48032,31 @@
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@@ -47827,99 +48070,99 @@
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@@ -47941,20 +48184,20 @@
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
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@@ -47966,66 +48209,66 @@
           "candidate_public_raw",
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           "candidate_precomputed",
+          "candidate_public_raw",
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@@ -48121,33 +48364,33 @@
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@@ -48164,31 +48407,31 @@
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@@ -48202,68 +48445,71 @@
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@@ -48272,24 +48518,24 @@
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@@ -48301,18 +48547,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -48320,10 +48566,10 @@
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@@ -48331,46 +48577,46 @@
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@@ -48378,31 +48624,31 @@
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               "public_call_count": 1000
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@@ -48416,99 +48662,99 @@
           "code_cache_state": "process_order_dependent",
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           "synchronized_e2e_ms": {
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         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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@@ -48534,16 +48780,16 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
+        "candidate_precomputed",
         "baseline_precomputed",
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+        "baseline_public_raw",
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-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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       "paired_cupti_session": {
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@@ -48559,62 +48805,62 @@
           "baseline_public_raw",
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           "baseline_precomputed",
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-          "baseline_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
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-        "measurement_schedule_sha256": "77ab7cb7299f2b99ae643e332e919a9a47d0aa1cddbce4a518ccae2e855177c3",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.806058820250221,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -48638,24 +48884,24 @@
       "D": 112,
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@@ -48664,44 +48910,44 @@
           "median": 2.0
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@@ -48710,33 +48956,33 @@
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@@ -48753,31 +48999,31 @@
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@@ -48791,68 +49037,71 @@
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@@ -48861,24 +49110,24 @@
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@@ -48890,18 +49139,18 @@
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@@ -48909,10 +49158,10 @@
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@@ -48920,46 +49169,46 @@
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@@ -48967,31 +49216,31 @@
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@@ -49005,99 +49254,99 @@
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@@ -49119,20 +49368,20 @@
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@@ -49144,66 +49393,66 @@
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -49253,44 +49502,44 @@
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@@ -49299,33 +49548,33 @@
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@@ -49342,31 +49591,31 @@
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@@ -49380,68 +49629,71 @@
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@@ -49450,24 +49702,24 @@
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@@ -49479,18 +49731,18 @@
         "root_dispatch_traversal_count": 0,
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         "stable_direct_launcher_tokens": [
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@@ -49498,10 +49750,10 @@
         "source_read_occurred": true
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@@ -49510,46 +49762,46 @@
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@@ -49557,31 +49809,31 @@
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@@ -49595,99 +49847,99 @@
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@@ -49709,12 +49961,12 @@
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@@ -49722,7 +49974,7 @@
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@@ -49734,66 +49986,66 @@
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@@ -49843,44 +50095,44 @@
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@@ -49889,33 +50141,33 @@
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@@ -49932,31 +50184,31 @@
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@@ -49970,68 +50222,71 @@
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@@ -50040,24 +50295,24 @@
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@@ -50069,18 +50324,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc023ff7d0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb9fb45a90",
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@@ -50088,10 +50343,10 @@
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@@ -50100,46 +50355,46 @@
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@@ -50147,31 +50402,31 @@
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@@ -50185,99 +50440,99 @@
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@@ -50295,8 +50550,6 @@
       "measurement_order": [
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "candidate_public_raw",
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@@ -50305,14 +50558,16 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "baseline_public_raw",
-        "candidate_public_raw"
+        "candidate_public_raw",
+        "baseline_precomputed",
+        "candidate_precomputed",
+        "candidate_precomputed",
+        "baseline_precomputed"
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3462c70f2aa84e4793077c9e9ca68837",
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       "paired_cupti_session": {
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@@ -50320,8 +50575,6 @@
         "first_reportable_roles": [
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           "baseline_precomputed",
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           "candidate_public_raw",
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@@ -50330,60 +50583,62 @@
           "candidate_precomputed",
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           "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "baseline_public_raw",
-          "candidate_public_raw"
+          "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -50407,24 +50662,24 @@
       "D": 128,
       "K": 512,
       "N": 2176,
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@@ -50433,44 +50688,44 @@
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@@ -50479,33 +50734,33 @@
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@@ -50522,31 +50777,31 @@
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@@ -50630,24 +50888,24 @@
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@@ -50659,18 +50917,18 @@
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@@ -50678,10 +50936,10 @@
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@@ -50690,46 +50948,46 @@
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@@ -50737,31 +50995,31 @@
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@@ -50885,24 +51143,24 @@
       "measurement_order": [
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         "candidate_precomputed",
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         "baseline_public_raw",
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+        "candidate_precomputed",
+        "baseline_precomputed",
         "candidate_precomputed"
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@@ -50910,70 +51168,70 @@
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@@ -50997,24 +51255,24 @@
       "D": 128,
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@@ -51023,33 +51281,33 @@
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@@ -51059,8 +51317,8 @@
           "median": 1.0
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@@ -51072,7 +51330,7 @@
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@@ -51081,21 +51339,21 @@
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@@ -51112,31 +51370,31 @@
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@@ -51150,68 +51408,71 @@
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@@ -51220,24 +51481,24 @@
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@@ -51249,18 +51510,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0273aed0"
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@@ -51268,10 +51529,10 @@
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@@ -51280,46 +51541,46 @@
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@@ -51327,31 +51588,31 @@
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@@ -51365,99 +51626,99 @@
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@@ -51492,7 +51753,7 @@
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@@ -51516,54 +51777,54 @@
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@@ -51588,23 +51849,23 @@
       "K": 256,
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@@ -51613,44 +51874,44 @@
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@@ -51659,33 +51920,33 @@
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@@ -51702,31 +51963,31 @@
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@@ -51810,24 +52074,24 @@
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@@ -51858,10 +52122,10 @@
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@@ -51917,31 +52181,31 @@
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@@ -52082,7 +52346,7 @@
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@@ -52106,54 +52370,54 @@
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@@ -52177,24 +52441,24 @@
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@@ -52203,44 +52467,44 @@
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@@ -52249,33 +52513,33 @@
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@@ -52292,31 +52556,31 @@
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@@ -52330,68 +52594,71 @@
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@@ -52400,24 +52667,24 @@
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@@ -52429,18 +52696,18 @@
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@@ -52448,10 +52715,10 @@
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@@ -52460,46 +52727,46 @@
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@@ -52507,31 +52774,31 @@
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@@ -52672,7 +52939,7 @@
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@@ -52696,54 +52963,54 @@
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@@ -52767,24 +53034,24 @@
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@@ -52793,44 +53060,44 @@
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@@ -52839,33 +53106,33 @@
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@@ -52882,31 +53149,31 @@
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@@ -52990,24 +53260,24 @@
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@@ -53019,18 +53289,18 @@
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@@ -53038,10 +53308,10 @@
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@@ -53050,46 +53320,46 @@
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@@ -53097,31 +53367,31 @@
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@@ -53135,99 +53405,99 @@
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@@ -53243,97 +53513,97 @@
       "fresh_pointer_rebind_verified": true,
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@@ -53472,31 +53742,31 @@
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@@ -53580,24 +53853,24 @@
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@@ -53609,18 +53882,18 @@
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@@ -53628,10 +53901,10 @@
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@@ -53640,46 +53913,46 @@
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@@ -53687,31 +53960,31 @@
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@@ -53833,12 +54106,10 @@
       "fresh_pointer_rebind_verified": true,
       "label": "post_d895_d144_b1_n512_k8192_d144",
       "measurement_order": [
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-        "candidate_precomputed",
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         "baseline_precomputed",
+        "candidate_precomputed",
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@@ -53848,22 +54119,22 @@
         "candidate_precomputed",
         "baseline_precomputed",
         "candidate_public_raw",
-        "baseline_public_raw"
+        "baseline_public_raw",
+        "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "bb057d64f5dd4a68a07fac499aa57dd5",
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         "adjacent_candidate_baseline_pairs": true,
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@@ -53873,57 +54144,59 @@
           "candidate_precomputed",
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           "candidate_public_raw",
-          "baseline_public_raw"
+          "baseline_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -53947,24 +54220,24 @@
       "D": 144,
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@@ -53973,44 +54246,44 @@
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@@ -54019,33 +54292,33 @@
           "median": 1.0
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@@ -54062,31 +54335,31 @@
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@@ -54170,24 +54446,24 @@
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@@ -54199,18 +54475,18 @@
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@@ -54218,10 +54494,10 @@
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@@ -54230,46 +54506,46 @@
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@@ -54277,31 +54553,31 @@
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@@ -54315,99 +54591,99 @@
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@@ -54433,16 +54709,16 @@
         "baseline_public_raw",
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         "candidate_precomputed",
-        "baseline_precomputed",
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         "baseline_public_raw",
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@@ -54458,62 +54734,62 @@
           "baseline_public_raw",
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           "candidate_precomputed",
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-          "candidate_precomputed",
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@@ -54609,33 +54885,33 @@
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@@ -54652,31 +54928,31 @@
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@@ -54690,68 +54966,71 @@
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@@ -54760,24 +55039,24 @@
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@@ -54789,18 +55068,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -54808,10 +55087,10 @@
         "source_read_occurred": true
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@@ -54820,46 +55099,46 @@
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@@ -54867,31 +55146,31 @@
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@@ -54905,99 +55184,99 @@
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@@ -55021,10 +55300,10 @@
         "candidate_precomputed",
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         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
+        "candidate_precomputed",
+        "baseline_precomputed",
         "baseline_precomputed",
         "candidate_precomputed",
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@@ -55032,7 +55311,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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       "paired_cupti_session": {
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@@ -55046,64 +55325,64 @@
           "candidate_precomputed",
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           "candidate_precomputed",
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           "candidate_public_raw",
           "baseline_public_raw",
+          "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -55127,24 +55406,24 @@
       "D": 16,
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@@ -55153,44 +55432,44 @@
           "median": 2.0
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@@ -55199,33 +55478,33 @@
           "median": 1.0
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@@ -55242,31 +55521,31 @@
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@@ -55280,68 +55559,71 @@
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@@ -55350,24 +55632,24 @@
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@@ -55398,10 +55680,10 @@
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@@ -55457,31 +55739,31 @@
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@@ -55622,7 +55904,7 @@
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@@ -55646,54 +55928,54 @@
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@@ -55743,44 +56025,44 @@
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@@ -55789,33 +56071,33 @@
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@@ -55832,31 +56114,31 @@
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@@ -55870,68 +56152,71 @@
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@@ -55940,24 +56225,24 @@
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@@ -55969,18 +56254,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -55988,10 +56273,10 @@
         "source_read_occurred": true
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@@ -55999,46 +56284,46 @@
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@@ -56046,31 +56331,31 @@
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@@ -56084,99 +56369,99 @@
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@@ -56211,7 +56496,7 @@
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@@ -56235,54 +56520,54 @@
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@@ -56306,24 +56591,24 @@
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@@ -56332,33 +56617,33 @@
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@@ -56368,8 +56653,8 @@
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@@ -56381,7 +56666,7 @@
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@@ -56392,19 +56677,19 @@
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@@ -56421,31 +56706,31 @@
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@@ -56459,68 +56744,71 @@
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@@ -56529,24 +56817,24 @@
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@@ -56558,18 +56846,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
         "stable_direct_launcher_tokens": [
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc0491fdd0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc295c2cc0",
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         "nvrtc_compile_occurred": true,
@@ -56577,10 +56865,10 @@
         "source_read_occurred": true
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@@ -56589,46 +56877,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_tflops_from_gpu_span": 1.0601411764705881,
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@@ -56636,31 +56924,31 @@
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@@ -56674,99 +56962,99 @@
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@@ -56788,20 +57076,20 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
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         "baseline_public_raw",
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         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed"
+        "baseline_public_raw",
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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       "paired_cupti_session": {
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@@ -56813,66 +57101,66 @@
           "baseline_public_raw",
           "candidate_precomputed",
           "baseline_precomputed",
+          "candidate_public_raw",
+          "baseline_public_raw",
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           "candidate_precomputed",
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           "baseline_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.6510538641686182,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -56896,24 +57184,24 @@
       "D": 176,
       "K": 8192,
       "N": 512,
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@@ -56922,44 +57210,44 @@
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       "baseline_07cf_precomputed_timing_diagnostics": {
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@@ -56968,33 +57256,33 @@
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@@ -57011,31 +57299,31 @@
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@@ -57049,68 +57337,71 @@
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@@ -57119,24 +57410,24 @@
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@@ -57148,18 +57439,18 @@
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@@ -57167,10 +57458,10 @@
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@@ -57179,46 +57470,46 @@
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@@ -57226,31 +57517,31 @@
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@@ -57264,99 +57555,99 @@
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@@ -57372,97 +57663,97 @@
       "fresh_pointer_rebind_verified": true,
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@@ -57512,44 +57803,44 @@
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@@ -57558,33 +57849,33 @@
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@@ -57601,31 +57892,31 @@
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@@ -57639,68 +57930,71 @@
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@@ -57709,24 +58003,24 @@
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@@ -57738,18 +58032,18 @@
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       "candidate_public_raw_cold_first_call_activity": {
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         "nvrtc_compile_occurred": true,
@@ -57757,10 +58051,10 @@
         "source_read_occurred": true
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       "candidate_public_raw_fresh_pointer_cache_hit": true,
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@@ -57769,46 +58063,46 @@
       "candidate_public_raw_norm_policy": "route_required_internal_fused_bf16_pair_row_norm",
       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
       "candidate_public_raw_shape_first_was_cache_hit": false,
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-      "candidate_public_raw_synchronized_e2e_ms": 0.097697,
-      "candidate_public_raw_tflops_from_gpu_span": 47.223484135107476,
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       "candidate_public_raw_timing_diagnostics": {
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@@ -57816,31 +58110,31 @@
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@@ -57854,99 +58148,99 @@
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@@ -57972,16 +58266,16 @@
         "baseline_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
+        "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed"
+        "candidate_public_raw",
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       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
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-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -57997,62 +58291,62 @@
           "baseline_public_raw",
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           "baseline_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
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         "schema": "flash-kmeans-interleaved-cupti-session-v1",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.7441681934962177,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -58076,24 +58370,24 @@
       "D": 176,
       "K": 1024,
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@@ -58102,44 +58396,44 @@
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@@ -58148,33 +58442,33 @@
           "median": 1.0
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@@ -58299,24 +58596,24 @@
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@@ -58328,18 +58625,18 @@
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@@ -58347,10 +58644,10 @@
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@@ -58359,46 +58656,46 @@
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@@ -58406,31 +58703,31 @@
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@@ -58444,99 +58741,99 @@
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@@ -58560,18 +58857,18 @@
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -58585,64 +58882,64 @@
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@@ -58666,24 +58963,24 @@
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@@ -58692,44 +58989,44 @@
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@@ -58738,33 +59035,33 @@
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@@ -58781,31 +59078,31 @@
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@@ -58819,57 +59116,60 @@
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@@ -58879,8 +59179,8 @@
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@@ -58889,24 +59189,24 @@
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@@ -58918,18 +59218,18 @@
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@@ -58937,10 +59237,10 @@
         "source_read_occurred": true
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@@ -58949,46 +59249,46 @@
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@@ -58996,31 +59296,31 @@
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@@ -59148,20 +59448,20 @@
         "candidate_public_raw",
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         "candidate_precomputed",
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-        "baseline_precomputed",
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+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -59173,66 +59473,66 @@
           "candidate_public_raw",
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           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -59256,24 +59556,24 @@
       "D": 224,
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@@ -59282,44 +59582,44 @@
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@@ -59328,33 +59628,33 @@
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@@ -59371,31 +59671,31 @@
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@@ -59479,24 +59782,24 @@
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@@ -59508,18 +59811,18 @@
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@@ -59527,10 +59830,10 @@
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@@ -59539,46 +59842,46 @@
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@@ -59586,31 +59889,31 @@
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@@ -59751,7 +60054,7 @@
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@@ -59775,54 +60078,54 @@
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@@ -59961,31 +60264,31 @@
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@@ -60069,24 +60375,24 @@
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@@ -60098,18 +60404,18 @@
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@@ -60117,10 +60423,10 @@
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@@ -60129,46 +60435,46 @@
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@@ -60176,31 +60482,31 @@
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@@ -60214,99 +60520,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 53.515498,
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         "hot_compute": {
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         "schema": "loom-public-runtime-lifecycle-v1",
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@@ -60332,16 +60638,16 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_precomputed",
-        "baseline_precomputed",
         "candidate_public_raw",
         "baseline_public_raw",
+        "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_public_raw",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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       "paired_cupti_session": {
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@@ -60357,62 +60663,62 @@
           "baseline_public_raw",
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           "candidate_precomputed",
-          "candidate_precomputed",
-          "baseline_precomputed",
           "candidate_public_raw",
           "baseline_public_raw",
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         "order_seed": "flashlib-kmeans-export-paired-replay-v1",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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       "runtime_coverage": false,
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -60436,24 +60742,24 @@
       "D": 224,
       "K": 1024,
       "N": 8192,
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@@ -60462,44 +60768,44 @@
           "median": 2.0
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@@ -60508,33 +60814,33 @@
           "median": 1.0
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@@ -60551,31 +60857,31 @@
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@@ -60659,24 +60968,24 @@
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@@ -60688,18 +60997,18 @@
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@@ -60707,10 +61016,10 @@
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@@ -60766,31 +61075,31 @@
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@@ -60924,14 +61233,14 @@
         "candidate_public_raw",
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@@ -60949,60 +61258,60 @@
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -61042,8 +61351,8 @@
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@@ -61141,31 +61450,31 @@
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@@ -61179,68 +61488,71 @@
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@@ -61249,24 +61561,24 @@
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@@ -61278,18 +61590,18 @@
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@@ -61297,10 +61609,10 @@
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@@ -61309,46 +61621,46 @@
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@@ -61356,31 +61668,31 @@
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+              "including_init_host_enqueue_ms_per_call": 0.08376167300000001,
+              "including_init_synchronized_e2e_ms_per_call": 0.09949562499999999,
               "public_call_count": 1000
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           ],
@@ -61394,99 +61706,99 @@
           "code_cache_state": "process_order_dependent",
           "gpu_span_ms": null,
           "gpu_span_status": "not_collected_for_slot_miss_host_diagnostic",
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-          "synchronized_e2e_ms": 1.888426,
+          "host_enqueue_ms": 2.096002,
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           "timing_class": "cupti_timestamp_host_diagnostic"
         },
         "hot_compute": {
           "cache_state": "fresh_pointer_shape_slot_hit",
           "gpu_span_ms": {
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-            "median": 0.0216,
-            "min": 0.017888,
-            "p90": 0.029696,
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+            "min": 0.013984,
+            "p90": 0.015008,
+            "sample_count": 7071
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           "synchronized_e2e_ms": {
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-          "sample_id": "3b3cb0beb21c413cab220416f38fa203",
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           "timing_class": "cupti_timestamp_host_diagnostic"
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-        "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
+        "measurement_session_id": "429dbdfd2f734f02819474b9385e8bb8",
         "output_policy": "default_output_allocated_before_preprocessing_inside_timing",
         "schema": "loom-public-runtime-lifecycle-v1",
         "timing_boundary": "raw_inputs_default_output_internal_required_norms_cached_dispatch_and_synchronized_completion"
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       "cold_baseline_precomputed_first_pointer": {
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       "cold_baseline_precomputed_fresh_pointer": {
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       "cold_baseline_public_raw_fresh_pointer_hit": {
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       "cold_candidate_public_raw_fresh_pointer_hit": {
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@@ -61508,20 +61820,20 @@
         "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "baseline_precomputed",
-        "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
-        "candidate_public_raw",
-        "baseline_public_raw"
+        "baseline_public_raw",
+        "candidate_public_raw"
       ],
       "measurement_order_policy": "deterministic_interleaved_adjacent_ab_pairs",
       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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       "paired_cupti_session": {
         "adaptive_probe_cupti_session_count": 4,
         "adaptive_probes_reportable": false,
@@ -61533,66 +61845,66 @@
           "baseline_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
-          "baseline_precomputed",
-          "candidate_precomputed",
           "baseline_public_raw",
           "candidate_public_raw",
           "baseline_precomputed",
           "candidate_precomputed",
+          "candidate_public_raw",
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           "baseline_precomputed",
           "candidate_precomputed",
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-          "baseline_public_raw"
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-        "measurement_schedule_sha256": "ece7239f25db1053083ff5cc7adbdbbb2c13cbcd8d2cbff1667d2a9e8f77ab09",
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-      "paired_cupti_session_id": "3b3cb0beb21c413cab220416f38fa203:post_d895_d288_b1_n256_k256_d288",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.9012048192771084,
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.8166917074102178,
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       "route_matches_expected": true,
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       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -61616,24 +61928,24 @@
       "D": 288,
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       "N": 512,
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       "baseline_07cf_adapter_timing_diagnostics": {
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@@ -61642,44 +61954,44 @@
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@@ -61688,33 +62000,33 @@
           "median": 1.0
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@@ -61731,31 +62043,31 @@
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@@ -61769,68 +62081,71 @@
           "code_cache_state": "process_order_dependent",
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@@ -61839,24 +62154,24 @@
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@@ -61887,10 +62202,10 @@
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@@ -61898,46 +62213,46 @@
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@@ -61945,31 +62260,31 @@
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@@ -61983,99 +62298,99 @@
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@@ -62110,7 +62425,7 @@
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@@ -62134,54 +62449,54 @@
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@@ -62205,24 +62520,24 @@
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@@ -62277,33 +62592,33 @@
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@@ -62320,31 +62635,31 @@
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@@ -62428,24 +62746,24 @@
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@@ -62457,18 +62775,18 @@
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@@ -62476,10 +62794,10 @@
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@@ -62535,31 +62853,31 @@
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@@ -62695,12 +63013,12 @@
         "candidate_public_raw",
         "candidate_precomputed",
         "baseline_precomputed",
-        "candidate_public_raw",
-        "baseline_public_raw"
+        "candidate_precomputed",
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@@ -62720,58 +63038,58 @@
           "candidate_public_raw",
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           "baseline_precomputed",
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@@ -62795,24 +63113,24 @@
       "D": 288,
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@@ -62821,44 +63139,44 @@
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@@ -62867,33 +63185,33 @@
           "median": 1.0
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@@ -62910,31 +63228,31 @@
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@@ -62948,68 +63266,71 @@
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-      "candidate_precomputed_submission_ms": 0.039008,
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@@ -63018,24 +63339,24 @@
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@@ -63047,18 +63368,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc049b71d0"
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@@ -63066,10 +63387,10 @@
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@@ -63078,46 +63399,46 @@
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@@ -63125,31 +63446,31 @@
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@@ -63163,99 +63484,99 @@
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@@ -63290,7 +63611,7 @@
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@@ -63314,54 +63635,54 @@
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@@ -63385,24 +63706,24 @@
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@@ -63411,44 +63732,44 @@
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@@ -63457,33 +63778,33 @@
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@@ -63500,31 +63821,31 @@
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@@ -63538,68 +63859,71 @@
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@@ -63608,24 +63932,24 @@
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@@ -63637,18 +63961,18 @@
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@@ -63656,10 +63980,10 @@
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@@ -63668,46 +63992,46 @@
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@@ -63715,31 +64039,31 @@
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@@ -63904,54 +64228,54 @@
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@@ -64001,44 +64325,44 @@
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@@ -64047,33 +64371,33 @@
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@@ -64090,31 +64414,31 @@
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@@ -64128,68 +64452,71 @@
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@@ -64198,24 +64525,24 @@
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@@ -64227,15 +64554,15 @@
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@@ -64246,10 +64573,10 @@
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@@ -64258,46 +64585,46 @@
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@@ -64305,31 +64632,31 @@
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@@ -64470,7 +64797,7 @@
       ],
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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       "paired_cupti_session": {
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         "adaptive_probes_reportable": false,
@@ -64510,38 +64837,38 @@
         "schema": "flash-kmeans-interleaved-cupti-session-v1",
         "warmup_schedule_iteration_count": 500
       },
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
-      "precomputed_gpu_speedup_vs_07cf": 0.8800232056732676,
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       "public_raw_baseline_name": "triton_h200_07cf_raw_adapter_v1",
-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.038602901150967,
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       "route_matches_expected": true,
       "runtime_coverage": false,
       "runtime_lifecycle_comparison": {
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -64565,24 +64892,24 @@
       "D": 352,
       "K": 256,
       "N": 256,
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@@ -64594,41 +64921,41 @@
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@@ -64637,33 +64964,33 @@
           "median": 1.0
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@@ -64680,31 +65007,31 @@
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@@ -64718,68 +65045,71 @@
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@@ -64788,24 +65118,24 @@
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@@ -64817,18 +65147,18 @@
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@@ -64836,10 +65166,10 @@
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@@ -64895,31 +65225,31 @@
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@@ -65047,12 +65377,12 @@
         "baseline_public_raw",
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         "candidate_precomputed",
+        "baseline_public_raw",
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@@ -65060,7 +65390,7 @@
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@@ -65072,66 +65402,66 @@
           "baseline_public_raw",
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           "candidate_precomputed",
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@@ -65181,44 +65511,44 @@
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@@ -65227,33 +65557,33 @@
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@@ -65270,31 +65600,31 @@
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@@ -65378,24 +65711,24 @@
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@@ -65407,18 +65740,18 @@
         "root_dispatch_traversal_count": 0,
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         "stable_direct_launcher_tokens": [
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@@ -65426,10 +65759,10 @@
         "source_read_occurred": false
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@@ -65437,46 +65770,46 @@
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@@ -65484,31 +65817,31 @@
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@@ -65522,99 +65855,99 @@
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@@ -65640,16 +65973,16 @@
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@@ -65665,62 +65998,62 @@
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@@ -65744,24 +66077,24 @@
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@@ -65770,44 +66103,44 @@
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@@ -65816,33 +66149,33 @@
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@@ -65859,31 +66192,31 @@
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@@ -65897,68 +66230,71 @@
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@@ -65967,24 +66303,24 @@
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@@ -65996,18 +66332,18 @@
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@@ -66015,10 +66351,10 @@
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@@ -66026,46 +66362,46 @@
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@@ -66073,31 +66409,31 @@
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@@ -66111,99 +66447,99 @@
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@@ -66229,16 +66565,16 @@
         "candidate_public_raw",
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-        "candidate_precomputed",
         "candidate_public_raw",
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         "baseline_precomputed",
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+        "candidate_precomputed",
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@@ -66254,62 +66590,62 @@
           "candidate_public_raw",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -66333,24 +66669,24 @@
       "D": 352,
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@@ -66359,44 +66695,44 @@
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@@ -66405,33 +66741,33 @@
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@@ -66448,31 +66784,31 @@
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@@ -66556,24 +66895,24 @@
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@@ -66585,18 +66924,18 @@
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@@ -66604,10 +66943,10 @@
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@@ -66616,46 +66955,46 @@
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@@ -66663,31 +67002,31 @@
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@@ -66821,14 +67160,14 @@
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@@ -66846,60 +67185,60 @@
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@@ -66923,24 +67262,24 @@
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@@ -66949,44 +67288,44 @@
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@@ -66995,33 +67334,33 @@
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@@ -67038,31 +67377,31 @@
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@@ -67076,68 +67415,71 @@
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@@ -67146,24 +67488,24 @@
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@@ -67175,18 +67517,18 @@
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc04b8a540"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb731860c0",
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@@ -67194,10 +67536,10 @@
         "source_read_occurred": false
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@@ -67206,46 +67548,46 @@
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@@ -67253,31 +67595,31 @@
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@@ -67291,99 +67633,99 @@
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@@ -67399,97 +67741,97 @@
       "fresh_pointer_rebind_verified": true,
       "label": "post_d895_d416_b1_n256_k256_d416",
       "measurement_order": [
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         "baseline_precomputed",
         "candidate_precomputed",
         "baseline_public_raw",
         "candidate_public_raw",
         "baseline_precomputed",
         "candidate_precomputed",
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+        "candidate_public_raw",
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-      "measurement_session_id": "a618b8f9b7234b02aa0a0e6f8a02f141",
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           "candidate_public_raw",
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         "speedup_convention": "baseline_latency_divided_by_candidate_latency"
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@@ -67513,24 +67855,24 @@
       "D": 416,
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@@ -67539,44 +67881,44 @@
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@@ -67585,33 +67927,33 @@
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@@ -67628,31 +67970,31 @@
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@@ -67736,24 +68081,24 @@
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@@ -67765,18 +68110,18 @@
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@@ -67784,10 +68129,10 @@
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@@ -67842,31 +68187,31 @@
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@@ -67988,12 +68333,10 @@
       "fresh_pointer_rebind_verified": true,
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       "measurement_order": [
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@@ -68002,23 +68345,23 @@
         "candidate_public_raw",
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         "baseline_precomputed",
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-        "candidate_precomputed"
+        "candidate_public_raw",
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+        "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
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@@ -68027,58 +68370,60 @@
           "candidate_public_raw",
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           "baseline_precomputed",
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@@ -68128,44 +68473,44 @@
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@@ -68174,33 +68519,33 @@
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@@ -68217,31 +68562,31 @@
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@@ -68255,68 +68600,71 @@
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@@ -68325,24 +68673,24 @@
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@@ -68354,18 +68702,18 @@
         "root_dispatch_traversal_count": 0,
         "scratch_reused": true,
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-          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffc00358ce0"
+          "flashlib_cake_kmeans._dispatch_runtime.PreparedKernelSequence@fffb6b3d1010",
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@@ -68373,10 +68721,10 @@
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@@ -68385,46 +68733,46 @@
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@@ -68432,31 +68780,31 @@
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@@ -68470,99 +68818,99 @@
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@@ -68588,16 +68936,16 @@
         "baseline_public_raw",
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-        "baseline_precomputed",
         "candidate_public_raw",
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-        "baseline_precomputed"
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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@@ -68613,62 +68961,62 @@
           "baseline_public_raw",
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           "baseline_precomputed",
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           "candidate_public_raw",
           "baseline_public_raw",
           "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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-      "public_raw_e2e_speedup_vs_07cf_adapter": 1.5121497611958543,
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@@ -68692,24 +69040,24 @@
       "D": 416,
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@@ -68718,44 +69066,44 @@
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@@ -68764,33 +69112,33 @@
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@@ -68807,31 +69155,31 @@
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@@ -68915,24 +69266,24 @@
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@@ -68944,18 +69295,18 @@
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@@ -68963,10 +69314,10 @@
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@@ -68975,46 +69326,46 @@
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@@ -69022,31 +69373,31 @@
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@@ -69187,7 +69538,7 @@
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@@ -69211,54 +69562,54 @@
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@@ -69282,24 +69633,24 @@
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@@ -69308,44 +69659,44 @@
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@@ -69354,33 +69705,33 @@
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@@ -69397,31 +69748,31 @@
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@@ -69505,24 +69859,24 @@
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@@ -69534,18 +69888,18 @@
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@@ -69553,10 +69907,10 @@
         "source_read_occurred": false
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@@ -69565,46 +69919,46 @@
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       "candidate_public_raw_output_policy": "default_output_allocated_before_preprocessing_inside_timing",
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-      "candidate_public_raw_tflops_from_gpu_span": 2.275555555555556,
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       "candidate_public_raw_timing_diagnostics": {
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@@ -69612,31 +69966,31 @@
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@@ -69758,18 +70112,18 @@
       "fresh_pointer_rebind_verified": true,
       "label": "post_d895_d480_b1_n256_k256_d480",
       "measurement_order": [
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@@ -69777,78 +70131,78 @@
       ],
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@@ -69872,24 +70226,24 @@
       "D": 480,
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@@ -69898,44 +70252,44 @@
           "median": 2.0
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@@ -69944,33 +70298,33 @@
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@@ -70095,24 +70452,24 @@
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@@ -70124,18 +70481,18 @@
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@@ -70143,10 +70500,10 @@
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@@ -70201,31 +70558,31 @@
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@@ -70366,7 +70723,7 @@
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@@ -70390,54 +70747,54 @@
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@@ -70487,44 +70844,44 @@
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@@ -70533,33 +70890,33 @@
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@@ -70576,31 +70933,31 @@
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@@ -70614,57 +70971,60 @@
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@@ -70674,8 +71034,8 @@
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@@ -70684,10 +71044,10 @@
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@@ -70696,12 +71056,12 @@
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@@ -70713,18 +71073,18 @@
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@@ -70732,10 +71092,10 @@
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@@ -70743,46 +71103,46 @@
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@@ -70790,31 +71150,31 @@
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@@ -70828,99 +71188,99 @@
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@@ -70946,16 +71306,16 @@
         "baseline_public_raw",
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         "baseline_public_raw",
         "candidate_public_raw",
         "baseline_precomputed",
-        "candidate_precomputed"
+        "candidate_precomputed",
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       "measurement_order_seed": "flashlib-kmeans-export-paired-replay-v1",
-      "measurement_session_id": "3b3cb0beb21c413cab220416f38fa203",
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@@ -70971,62 +71331,62 @@
           "baseline_public_raw",
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+          "candidate_precomputed",
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       "precomputed_baseline_name": "triton_h200_07cf_precomputed",
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@@ -71050,24 +71410,24 @@
       "D": 480,
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@@ -71076,44 +71436,44 @@
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@@ -71122,33 +71482,33 @@
           "median": 1.0
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@@ -71165,31 +71525,31 @@
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@@ -71273,24 +71636,24 @@
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@@ -71321,10 +71684,10 @@
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@@ -71380,31 +71743,31 @@
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@@ -71545,7 +71908,7 @@
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@@ -71569,54 +71932,54 @@
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@@ -71666,44 +72029,44 @@
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@@ -71712,33 +72075,33 @@
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@@ -71755,31 +72118,31 @@
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@@ -71793,68 +72156,71 @@
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@@ -71863,24 +72229,24 @@
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@@ -71892,18 +72258,18 @@
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@@ -71911,10 +72277,10 @@
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@@ -71923,46 +72289,46 @@
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@@ -71970,31 +72336,31 @@
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@@ -72116,97 +72482,97 @@
       "fresh_pointer_rebind_verified": true,
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@@ -72256,44 +72622,44 @@
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@@ -72302,33 +72668,33 @@
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@@ -72345,31 +72711,31 @@
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@@ -72383,68 +72749,71 @@
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@@ -72453,24 +72822,24 @@
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@@ -72482,18 +72851,18 @@
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@@ -72501,10 +72870,10 @@
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@@ -72513,46 +72882,46 @@
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@@ -72560,31 +72929,31 @@
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@@ -72598,99 +72967,99 @@
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@@ -72712,20 +73081,20 @@
         "baseline_public_raw",
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         "baseline_precomputed",
+        "candidate_public_raw",
+        "baseline_public_raw",
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@@ -72737,66 +73106,66 @@
           "baseline_public_raw",
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           "baseline_precomputed",
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@@ -72846,44 +73215,44 @@
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@@ -72892,33 +73261,33 @@
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@@ -72935,31 +73304,31 @@
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@@ -73043,24 +73415,24 @@
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@@ -73072,18 +73444,18 @@
         "root_dispatch_traversal_count": 0,
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@@ -73091,10 +73463,10 @@
         "source_read_occurred": false
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@@ -73103,46 +73475,46 @@
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@@ -73150,31 +73522,31 @@
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@@ -73188,99 +73560,99 @@
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@@ -73308,14 +73680,14 @@
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@@ -73333,60 +73705,60 @@
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@@ -73619,14 +73991,14 @@
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@@ -73685,169 +74057,169 @@
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+        "median": 2.2809542656641058,
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         "sample_count": 124
       },
       "10": {
-        "geomean": 0.9883599649332888,
-        "max": 14.74946941441697,
-        "median": 2.3838259809720013,
-        "min": 0.07827496375561803,
-        "p90": 14.52521021193764,
+        "geomean": 0.9590724810364581,
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+        "median": 2.2785747135963885,
+        "min": 0.08144088410284854,
+        "p90": 12.756198569243546,
         "sample_count": 124
       },
       "100": {
-        "geomean": 1.0625734771300246,
-        "max": 12.280738012861928,
-        "median": 2.266977314672681,
-        "min": 0.10470166796960959,
-        "p90": 11.64426554947311,
+        "geomean": 1.0709455274785604,
+        "max": 21.448324006518714,
+        "median": 2.256511456266482,
+        "min": 0.1092928565392167,
+        "p90": 10.92530869455313,
         "sample_count": 124
       },
       "1000": {
-        "geomean": 1.3037983467106373,
-        "max": 6.147177463228467,
-        "median": 1.3855552638525674,
-        "min": 0.3072695344894631,
-        "p90": 4.849531660761203,
+        "geomean": 1.4680428292344323,
+        "max": 10.378991521881256,
+        "median": 1.5029920226671636,
+        "min": 0.3509947998170528,
+        "p90": 6.045445059831923,
         "sample_count": 124
       }
     },
     "baseline_has_explicit_init": true,
     "baseline_hot_public_synchronized_e2e_ms": {
-      "geomean": 0.20105525733859214,
-      "max": 0.48014650000000003,
-      "median": 0.172529,
-      "min": 0.159457,
-      "p90": 0.3341426500000001,
+      "geomean": 0.20757016572840578,
+      "max": 0.5228809999999999,
+      "median": 0.18443199999999998,
+      "min": 0.16128,
+      "p90": 0.32694080000000014,
       "sample_count": 124
     },
     "baseline_init_host_enqueue_ms": {
-      "geomean": 36.37204484396895,
-      "max": 38.303733,
-      "median": 37.78005,
-      "min": 32.011411,
-      "p90": 38.1521769,
+      "geomean": 35.27461542656189,
+      "max": 36.934438,
+      "median": 35.000356,
+      "min": 34.227907,
+      "p90": 36.519487,
       "sample_count": 4
     },
     "baseline_init_synchronized_e2e_ms": {
-      "geomean": 134.60988585908277,
-      "max": 511.423938,
-      "median": 240.2103465,
-      "min": 37.838611,
-      "p90": 490.6082571,
+      "geomean": 128.13715080146187,
+      "max": 484.041494,
+      "median": 245.37127800000002,
+      "min": 34.345443,
+      "p90": 475.36244150000005,
       "sample_count": 4
     },
     "cache_policy": "synchronize_and_clear_after_each_completed_shape",
     "candidate_first_compute_host_enqueue_ms": {
-      "geomean": 6.0825652761787,
-      "max": 91.566558,
-      "median": 2.2524765,
-      "min": 1.560873,
-      "p90": 67.7166651,
+      "geomean": 7.402417492079541,
+      "max": 83.722038,
+      "median": 3.0477155,
+      "min": 1.974882,
+      "p90": 70.15640230000001,
       "sample_count": 124
     },
     "candidate_first_compute_synchronized_e2e_ms": {
-      "geomean": 6.151633003253004,
-      "max": 91.62739,
-      "median": 2.3083485,
-      "min": 1.583753,
-      "p90": 67.7591774,
+      "geomean": 7.475266319780226,
+      "max": 83.779798,
+      "median": 3.1303549999999998,
+      "min": 2.05613,
+      "p90": 70.21168870000001,
       "sample_count": 124
     },
     "candidate_hot_compute_gpu_span_ms": {
-      "geomean": 0.044683032963121115,
-      "max": 0.390658,
-      "median": 0.0421445,
-      "min": 0.014848,
-      "p90": 0.1080554,
+      "geomean": 0.03929959622925097,
+      "max": 0.389696,
+      "median": 0.038976,
+      "min": 0.009792,
+      "p90": 0.1054144,
       "sample_count": 124
     },
     "candidate_hot_compute_host_enqueue_ms": {
-      "geomean": 0.07779807502075908,
-      "max": 0.13169599999999998,
-      "median": 0.07708899999999999,
-      "min": 0.066816,
-      "p90": 0.0829399,
+      "geomean": 0.04880204368462327,
+      "max": 0.06767999999999999,
+      "median": 0.047231999999999996,
+      "min": 0.040064,
+      "p90": 0.0595648,
       "sample_count": 124
     },
     "candidate_hot_compute_synchronized_e2e_ms": {
-      "geomean": 0.11884894656730967,
-      "max": 0.459266,
-      "median": 0.10857675,
-      "min": 0.088064,
-      "p90": 0.1767082,
+      "geomean": 0.09510640113954803,
+      "max": 0.438208,
+      "median": 0.08894425,
+      "min": 0.056224,
+      "p90": 0.1581216,
       "sample_count": 124
     },
     "candidate_init_host_enqueue_ms": {
-      "geomean": 36.68171053908005,
-      "max": 38.535318000000004,
-      "median": 38.086867999999996,
-      "min": 32.388565,
-      "p90": 38.4300921,
+      "geomean": 35.64562210040985,
+      "max": 37.358022999999996,
+      "median": 35.356052,
+      "min": 34.57754,
+      "p90": 36.902022099999996,
       "sample_count": 4
     },
     "candidate_init_synchronized_e2e_ms": {
-      "geomean": 130.63995290830067,
-      "max": 526.030323,
-      "median": 242.07677249999998,
-      "min": 32.456148999999996,
-      "p90": 501.9887073,
+      "geomean": 129.7884798704558,
+      "max": 484.100213,
+      "median": 242.7617075,
+      "min": 34.943076,
+      "p90": 473.29648670000006,
       "sample_count": 4
     },
     "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
     "hot_gpu_span_speedup": {
-      "geomean": 2.008775202457142,
-      "max": 5.886473025071239,
-      "median": 1.9678408409147718,
-      "min": 0.9682996380465778,
-      "p90": 3.371271168769499,
+      "geomean": 2.316300717543746,
+      "max": 6.406190408085431,
+      "median": 2.159249130548963,
+      "min": 0.9709337534898999,
+      "p90": 4.868219371609404,
       "sample_count": 124
     },
     "hot_synchronized_e2e_speedup": {
-      "geomean": 1.6916873320768158,
-      "max": 3.1904450554863906,
-      "median": 1.6730758887255512,
-      "min": 1.038602901150967,
-      "p90": 2.2643380868174727,
+      "geomean": 2.1825046815076243,
+      "max": 3.8773006134969323,
+      "median": 2.1942486496321694,
+      "min": 1.093838998831605,
+      "p90": 2.842345086787142,
       "sample_count": 124
     },
     "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
diff --git a/cake_exports/kmeans/EXPORT_TIMING.json b/cake_exports/kmeans/EXPORT_TIMING.json
index add831ab..adab9ef1 100644
--- a/cake_exports/kmeans/EXPORT_TIMING.json
+++ b/cake_exports/kmeans/EXPORT_TIMING.json
@@ -1,10 +1,10 @@
 {
   "host_wall_phase_seconds": {
-    "benchmark": 154.0538639901206,
-    "correctness": 17.579008210916072,
-    "validation_total": 171.63287220103666
+    "benchmark": 204.77159006567672,
+    "correctness": 18.721056894399226,
+    "validation_total": 223.49264696007594
   },
-  "recorded_at_utc": "2026-07-08T23:29:04+00:00",
+  "recorded_at_utc": "2026-07-09T04:30:10+00:00",
   "reportable_gpu_timing_source": "BENCHMARK_RESULTS.json:CUPTI",
   "schema": "loom-export-host-wall-phases-v1",
   "validation_shard_count": 4
diff --git a/cake_exports/kmeans/README.md b/cake_exports/kmeans/README.md
index 2a6881e2..d879d320 100644
--- a/cake_exports/kmeans/README.md
+++ b/cake_exports/kmeans/README.md
@@ -4,33 +4,33 @@
 
 - Hardware: `NVIDIA GB200` (`sm_100a`)
 - Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
-- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
-- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
-- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+- Validation shards: `4`; host wall time: correctness `18.72s`, benchmark `204.77s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0938x`, geomean `2.1825x`, median `2.1942x`, p90 `2.8423x`, max `3.8773x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.7617 ms`; first-signature compute median/p90 `3.1304/70.2117 ms`; hot compute median/p90 `0.0889/0.1581 ms`
 
 #### Hot steady-state synchronized E2E speedup
 
 | Validated shape scope | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0938x | 2.1825x | 2.1942x | 2.8423x | 3.8773x |
 
 #### Modeled after-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
-| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
-| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
-| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+| 1 | 0.0865x | 1.2309x | 2.7840x | 3.3516x | 163.7986x |
+| 10 | 0.1110x | 1.2589x | 2.6667x | 3.0908x | 137.3500x |
+| 100 | 0.2850x | 1.5093x | 2.1682x | 2.9894x | 53.5582x |
+| 1000 | 1.0120x | 1.9957x | 2.0271x | 2.8424x | 9.5268x |
 
 #### Modeled including-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
-| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
-| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
-| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+| 1 | 0.0772x | 0.9450x | 2.2810x | 12.9363x | 24.8909x |
+| 10 | 0.0814x | 0.9591x | 2.2786x | 12.7562x | 24.5273x |
+| 100 | 0.1093x | 1.0709x | 2.2565x | 10.9253x | 21.4483x |
+| 1000 | 0.3510x | 1.4680x | 1.5030x | 6.0454x | 10.3790x |
 
 - All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
 - `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
@@ -39,7 +39,7 @@
 - Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
 - Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
 
-- Measured: `2026-07-08T23:29:04+00:00`
+- Measured: `2026-07-09T04:30:10+00:00`
 - Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
 
 This repository was generated by `loom.export.kernel_repo`. It contains frozen
diff --git a/cake_exports/kmeans/RESULTS.md b/cake_exports/kmeans/RESULTS.md
index 1e27fdd3..7e7e114b 100644
--- a/cake_exports/kmeans/RESULTS.md
+++ b/cake_exports/kmeans/RESULTS.md
@@ -4,8 +4,8 @@
 
 - Package: `flashlib_cake_kmeans`
 - Source repository: `ssh://git@gitlab-master.nvidia.com:12051/cake/cake.git`
-- Source commit: `a03428fc8362e2785d2e6a657fd70a74c8ed1c0d`
-- Generated at: `2026-07-08T23:26:07.392069+00:00`
+- Source commit: `42070e96d0734cb580854baef60f17625ba33bb5`
+- Generated at: `2026-07-09T04:26:21.680464+00:00`
 
 ## Latest Recorded Results
 
@@ -13,33 +13,33 @@
 
 - Hardware: `NVIDIA GB200` (`sm_100a`)
 - Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
-- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
-- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
-- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+- Validation shards: `4`; host wall time: correctness `18.72s`, benchmark `204.77s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0938x`, geomean `2.1825x`, median `2.1942x`, p90 `2.8423x`, max `3.8773x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.7617 ms`; first-signature compute median/p90 `3.1304/70.2117 ms`; hot compute median/p90 `0.0889/0.1581 ms`
 
 #### Hot steady-state synchronized E2E speedup
 
 | Validated shape scope | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0938x | 2.1825x | 2.1942x | 2.8423x | 3.8773x |
 
 #### Modeled after-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
-| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
-| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
-| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+| 1 | 0.0865x | 1.2309x | 2.7840x | 3.3516x | 163.7986x |
+| 10 | 0.1110x | 1.2589x | 2.6667x | 3.0908x | 137.3500x |
+| 100 | 0.2850x | 1.5093x | 2.1682x | 2.9894x | 53.5582x |
+| 1000 | 1.0120x | 1.9957x | 2.0271x | 2.8424x | 9.5268x |
 
 #### Modeled including-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
-| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
-| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
-| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+| 1 | 0.0772x | 0.9450x | 2.2810x | 12.9363x | 24.8909x |
+| 10 | 0.0814x | 0.9591x | 2.2786x | 12.7562x | 24.5273x |
+| 100 | 0.1093x | 1.0709x | 2.2565x | 10.9253x | 21.4483x |
+| 1000 | 0.3510x | 1.4680x | 1.5030x | 6.0454x | 10.3790x |
 
 - All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
 - `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
@@ -48,7 +48,7 @@
 - Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
 - Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
 
-- Measured: `2026-07-08T23:29:04+00:00`
+- Measured: `2026-07-09T04:30:10+00:00`
 - Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
 
 The machine-readable per-shape public lifecycle and CUPTI evidence is in [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json).
diff --git a/cake_exports/kmeans/VALIDATION.json b/cake_exports/kmeans/VALIDATION.json
index e1669133..e66206ff 100644
--- a/cake_exports/kmeans/VALIDATION.json
+++ b/cake_exports/kmeans/VALIDATION.json
@@ -5,17 +5,17 @@
     "floor_enforced": true,
     "shape_count": 124,
     "speedup_vs_baseline": {
-      "geomean": 1.6916873320768158,
-      "max": 3.1904450554863906,
-      "median": 1.6730758887255512,
-      "min": 1.038602901150967,
-      "p90": 2.2643380868174727,
+      "geomean": 2.1825046815076243,
+      "max": 3.8773006134969323,
+      "median": 2.1942486496321694,
+      "min": 1.093838998831605,
+      "p90": 2.842345086787142,
       "sample_count": 124
     }
   },
   "benchmark_commands": [
     [
-      "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+      "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
       "benchmarks/benchmark.py",
       "--no-correctness",
       "--json",
@@ -27,7 +27,7 @@
       "--quiet"
     ],
     [
-      "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+      "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
       "benchmarks/benchmark.py",
       "--no-correctness",
       "--json",
@@ -39,7 +39,7 @@
       "--quiet"
     ],
     [
-      "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+      "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
       "benchmarks/benchmark.py",
       "--no-correctness",
       "--json",
@@ -51,7 +51,7 @@
       "--quiet"
     ],
     [
-      "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+      "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
       "benchmarks/benchmark.py",
       "--no-correctness",
       "--json",
@@ -65,7 +65,7 @@
   ],
   "benchmark_passed": 124,
   "correctness_collection_command": [
-    "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+    "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
     "-m",
     "pytest",
     "tests/test_correctness.py",
@@ -75,7 +75,7 @@
     "export_validation_shape"
   ],
   "correctness_command": [
-    "/home/averyh/cake-export-venv-v5r4-kmeans/bin/python",
+    "/home/averyh/cake-export-venv-v6-kmeans/bin/python",
     "-m",
     "pytest",
     "tests/test_correctness.py",
@@ -88,16 +88,16 @@
     "arch": "sm_100a",
     "device": "NVIDIA GB200"
   },
-  "measured_at_utc": "2026-07-08T23:29:04+00:00",
+  "measured_at_utc": "2026-07-09T04:30:10+00:00",
   "minimum_speedup": 1.0,
   "performance_shape_count": 124,
   "performance_speedup_denominator_metric": "candidate_public_raw_synchronized_e2e_ms",
   "performance_speedup_metric": "public_raw_e2e_speedup_vs_07cf_adapter",
   "performance_speedup_numerator_metric": "baseline_07cf_adapter_synchronized_e2e_ms",
   "phase_seconds": {
-    "benchmark": 154.0538639901206,
-    "correctness": 17.579008210916072,
-    "validation_total": 171.63287220103666
+    "benchmark": 204.77159006567672,
+    "correctness": 18.721056894399226,
+    "validation_total": 223.49264696007594
   },
   "publication_performance_floor": {
     "below_floor": [],
@@ -232,11 +232,11 @@
       "post_d895_d48_b4_n8192_k1024_d48"
     ],
     "speedup_vs_baseline": {
-      "geomean": 1.6916873320768158,
-      "max": 3.1904450554863906,
-      "median": 1.6730758887255512,
-      "min": 1.038602901150967,
-      "p90": 2.2643380868174727,
+      "geomean": 2.1825046815076243,
+      "max": 3.8773006134969323,
+      "median": 2.1942486496321694,
+      "min": 1.093838998831605,
+      "p90": 2.842345086787142,
       "sample_count": 124
     },
     "status": "passed"
@@ -245,169 +245,169 @@
   "runtime_lifecycle": {
     "amortized_after_init_synchronized_e2e_speedup": {
       "1": {
-        "geomean": 1.3889160389178896,
-        "max": 10.779323991419206,
-        "median": 3.355393396642872,
-        "min": 0.07586420392417595,
-        "p90": 4.006561914159356,
+        "geomean": 1.2309434323137933,
+        "max": 163.79859302023343,
+        "median": 2.7839934141126323,
+        "min": 0.08647202905817367,
+        "p90": 3.351566582003962,
         "sample_count": 124
       },
       "10": {
-        "geomean": 1.307355798617821,
-        "max": 10.53411537391263,
-        "median": 2.7971699472139107,
-        "min": 0.1082360578653832,
-        "p90": 3.2902130577424313,
+        "geomean": 1.2588822989268478,
+        "max": 137.34998767211528,
+        "median": 2.6667329239063666,
+        "min": 0.11096680845482784,
+        "p90": 3.090755401506125,
         "sample_count": 124
       },
       "100": {
-        "geomean": 1.321002621423908,
-        "max": 8.649797268629165,
-        "median": 1.8382901113434449,
-        "min": 0.2874713583728166,
-        "p90": 2.447388612352715,
+        "geomean": 1.509344986064645,
+        "max": 53.5581614291322,
+        "median": 2.1681602849557455,
+        "min": 0.28495469134404755,
+        "p90": 2.989410840698895,
         "sample_count": 124
       },
       "1000": {
-        "geomean": 1.5936102009532662,
-        "max": 3.8584927877502286,
-        "median": 1.6051653436433109,
-        "min": 0.9247614976643037,
-        "p90": 2.2810664792185826,
+        "geomean": 1.9957356325578275,
+        "max": 9.526755432882533,
+        "median": 2.02714552137833,
+        "min": 1.0119821488655745,
+        "p90": 2.8424059645989446,
         "sample_count": 124
       }
     },
     "amortized_including_init_synchronized_e2e_speedup": {
       "1": {
-        "geomean": 0.9787867358001275,
-        "max": 15.098129694717327,
-        "median": 2.392392494120844,
-        "min": 0.07339598623291214,
-        "p90": 14.903145960609656,
+        "geomean": 0.9449946730011419,
+        "max": 24.89092858456689,
+        "median": 2.2809542656641058,
+        "min": 0.07723037119783416,
+        "p90": 12.93634198448204,
         "sample_count": 124
       },
       "10": {
-        "geomean": 0.9883599649332888,
-        "max": 14.74946941441697,
-        "median": 2.3838259809720013,
-        "min": 0.07827496375561803,
-        "p90": 14.52521021193764,
+        "geomean": 0.9590724810364581,
+        "max": 24.52727808638291,
+        "median": 2.2785747135963885,
+        "min": 0.08144088410284854,
+        "p90": 12.756198569243546,
         "sample_count": 124
       },
       "100": {
-        "geomean": 1.0625734771300246,
-        "max": 12.280738012861928,
-        "median": 2.266977314672681,
-        "min": 0.10470166796960959,
-        "p90": 11.64426554947311,
+        "geomean": 1.0709455274785604,
+        "max": 21.448324006518714,
+        "median": 2.256511456266482,
+        "min": 0.1092928565392167,
+        "p90": 10.92530869455313,
         "sample_count": 124
       },
       "1000": {
-        "geomean": 1.3037983467106373,
-        "max": 6.147177463228467,
-        "median": 1.3855552638525674,
-        "min": 0.3072695344894631,
-        "p90": 4.849531660761203,
+        "geomean": 1.4680428292344323,
+        "max": 10.378991521881256,
+        "median": 1.5029920226671636,
+        "min": 0.3509947998170528,
+        "p90": 6.045445059831923,
         "sample_count": 124
       }
     },
     "baseline_has_explicit_init": true,
     "baseline_hot_public_synchronized_e2e_ms": {
-      "geomean": 0.20105525733859214,
-      "max": 0.48014650000000003,
-      "median": 0.172529,
-      "min": 0.159457,
-      "p90": 0.3341426500000001,
+      "geomean": 0.20757016572840578,
+      "max": 0.5228809999999999,
+      "median": 0.18443199999999998,
+      "min": 0.16128,
+      "p90": 0.32694080000000014,
       "sample_count": 124
     },
     "baseline_init_host_enqueue_ms": {
-      "geomean": 36.37204484396895,
-      "max": 38.303733,
-      "median": 37.78005,
-      "min": 32.011411,
-      "p90": 38.1521769,
+      "geomean": 35.27461542656189,
+      "max": 36.934438,
+      "median": 35.000356,
+      "min": 34.227907,
+      "p90": 36.519487,
       "sample_count": 4
     },
     "baseline_init_synchronized_e2e_ms": {
-      "geomean": 134.60988585908277,
-      "max": 511.423938,
-      "median": 240.2103465,
-      "min": 37.838611,
-      "p90": 490.6082571,
+      "geomean": 128.13715080146187,
+      "max": 484.041494,
+      "median": 245.37127800000002,
+      "min": 34.345443,
+      "p90": 475.36244150000005,
       "sample_count": 4
     },
     "cache_policy": "synchronize_and_clear_after_each_completed_shape",
     "candidate_first_compute_host_enqueue_ms": {
-      "geomean": 6.0825652761787,
-      "max": 91.566558,
-      "median": 2.2524765,
-      "min": 1.560873,
-      "p90": 67.7166651,
+      "geomean": 7.402417492079541,
+      "max": 83.722038,
+      "median": 3.0477155,
+      "min": 1.974882,
+      "p90": 70.15640230000001,
       "sample_count": 124
     },
     "candidate_first_compute_synchronized_e2e_ms": {
-      "geomean": 6.151633003253004,
-      "max": 91.62739,
-      "median": 2.3083485,
-      "min": 1.583753,
-      "p90": 67.7591774,
+      "geomean": 7.475266319780226,
+      "max": 83.779798,
+      "median": 3.1303549999999998,
+      "min": 2.05613,
+      "p90": 70.21168870000001,
       "sample_count": 124
     },
     "candidate_hot_compute_gpu_span_ms": {
-      "geomean": 0.044683032963121115,
-      "max": 0.390658,
-      "median": 0.0421445,
-      "min": 0.014848,
-      "p90": 0.1080554,
+      "geomean": 0.03929959622925097,
+      "max": 0.389696,
+      "median": 0.038976,
+      "min": 0.009792,
+      "p90": 0.1054144,
       "sample_count": 124
     },
     "candidate_hot_compute_host_enqueue_ms": {
-      "geomean": 0.07779807502075908,
-      "max": 0.13169599999999998,
-      "median": 0.07708899999999999,
-      "min": 0.066816,
-      "p90": 0.0829399,
+      "geomean": 0.04880204368462327,
+      "max": 0.06767999999999999,
+      "median": 0.047231999999999996,
+      "min": 0.040064,
+      "p90": 0.0595648,
       "sample_count": 124
     },
     "candidate_hot_compute_synchronized_e2e_ms": {
-      "geomean": 0.11884894656730967,
-      "max": 0.459266,
-      "median": 0.10857675,
-      "min": 0.088064,
-      "p90": 0.1767082,
+      "geomean": 0.09510640113954803,
+      "max": 0.438208,
+      "median": 0.08894425,
+      "min": 0.056224,
+      "p90": 0.1581216,
       "sample_count": 124
     },
     "candidate_init_host_enqueue_ms": {
-      "geomean": 36.68171053908005,
-      "max": 38.535318000000004,
-      "median": 38.086867999999996,
-      "min": 32.388565,
-      "p90": 38.4300921,
+      "geomean": 35.64562210040985,
+      "max": 37.358022999999996,
+      "median": 35.356052,
+      "min": 34.57754,
+      "p90": 36.902022099999996,
       "sample_count": 4
     },
     "candidate_init_synchronized_e2e_ms": {
-      "geomean": 130.63995290830067,
-      "max": 526.030323,
-      "median": 242.07677249999998,
-      "min": 32.456148999999996,
-      "p90": 501.9887073,
+      "geomean": 129.7884798704558,
+      "max": 484.100213,
+      "median": 242.7617075,
+      "min": 34.943076,
+      "p90": 473.29648670000006,
       "sample_count": 4
     },
     "cold_order_policy": "deterministic_balanced_per_publication_contract_portfolio",
     "hot_gpu_span_speedup": {
-      "geomean": 2.008775202457142,
-      "max": 5.886473025071239,
-      "median": 1.9678408409147718,
-      "min": 0.9682996380465778,
-      "p90": 3.371271168769499,
+      "geomean": 2.316300717543746,
+      "max": 6.406190408085431,
+      "median": 2.159249130548963,
+      "min": 0.9709337534898999,
+      "p90": 4.868219371609404,
       "sample_count": 124
     },
     "hot_synchronized_e2e_speedup": {
-      "geomean": 1.6916873320768158,
-      "max": 3.1904450554863906,
-      "median": 1.6730758887255512,
-      "min": 1.038602901150967,
-      "p90": 2.2643380868174727,
+      "geomean": 2.1825046815076243,
+      "max": 3.8773006134969323,
+      "median": 2.1942486496321694,
+      "min": 1.093838998831605,
+      "p90": 2.842345086787142,
       "sample_count": 124
     },
     "init_composition": "runtime_init_plus_shared_preprocess_support_each_standalone_lane",
diff --git a/cake_exports/kmeans/VALIDATION.md b/cake_exports/kmeans/VALIDATION.md
index 3a0fc81d..81d24ced 100644
--- a/cake_exports/kmeans/VALIDATION.md
+++ b/cake_exports/kmeans/VALIDATION.md
@@ -2,33 +2,33 @@
 
 - Hardware: `NVIDIA GB200` (`sm_100a`)
 - Shapes: correctness `124/124`, CUPTI benchmark `124/124`; full generated suite `128` tests
-- Validation shards: `4`; host wall time: correctness `17.58s`, benchmark `154.05s`
-- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0386x`, geomean `1.6917x`, median `1.6731x`, p90 `2.2643x`, max `3.1904x` across all `124` floor-gated shapes (required minimum `1.0000x`)
-- Candidate lifecycle latency diagnostics: init-once median `242.0768 ms`; first-signature compute median/p90 `2.3083/67.7592 ms`; hot compute median/p90 `0.1086/0.1767 ms`
+- Validation shards: `4`; host wall time: correctness `18.72s`, benchmark `204.77s`
+- `public_raw_e2e_speedup_vs_07cf_adapter` vs `triton_h200_07cf_raw_adapter_v1`: min `1.0938x`, geomean `2.1825x`, median `2.1942x`, p90 `2.8423x`, max `3.8773x` across all `124` floor-gated shapes (required minimum `1.0000x`)
+- Candidate lifecycle latency diagnostics: init-once median `242.7617 ms`; first-signature compute median/p90 `3.1304/70.2117 ms`; hot compute median/p90 `0.0889/0.1581 ms`
 
 #### Hot steady-state synchronized E2E speedup
 
 | Validated shape scope | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| All 124 benchmarked shapes (diagnostic scope) | 1.0386x | 1.6917x | 1.6731x | 2.2643x | 3.1904x |
+| All 124 benchmarked shapes (diagnostic scope) | 1.0938x | 2.1825x | 2.1942x | 2.8423x | 3.8773x |
 
 #### Modeled after-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0759x | 1.3889x | 3.3554x | 4.0066x | 10.7793x |
-| 10 | 0.1082x | 1.3074x | 2.7972x | 3.2902x | 10.5341x |
-| 100 | 0.2875x | 1.3210x | 1.8383x | 2.4474x | 8.6498x |
-| 1000 | 0.9248x | 1.5936x | 1.6052x | 2.2811x | 3.8585x |
+| 1 | 0.0865x | 1.2309x | 2.7840x | 3.3516x | 163.7986x |
+| 10 | 0.1110x | 1.2589x | 2.6667x | 3.0908x | 137.3500x |
+| 100 | 0.2850x | 1.5093x | 2.1682x | 2.9894x | 53.5582x |
+| 1000 | 1.0120x | 1.9957x | 2.0271x | 2.8424x | 9.5268x |
 
 #### Modeled including-init amortized synchronized E2E speedup
 
 | Public calls N | Min | Geomean | Median | P90 | Max |
 | --- | ---: | ---: | ---: | ---: | ---: |
-| 1 | 0.0734x | 0.9788x | 2.3924x | 14.9031x | 15.0981x |
-| 10 | 0.0783x | 0.9884x | 2.3838x | 14.5252x | 14.7495x |
-| 100 | 0.1047x | 1.0626x | 2.2670x | 11.6443x | 12.2807x |
-| 1000 | 0.3073x | 1.3038x | 1.3856x | 4.8495x | 6.1472x |
+| 1 | 0.0772x | 0.9450x | 2.2810x | 12.9363x | 24.8909x |
+| 10 | 0.0814x | 0.9591x | 2.2786x | 12.7562x | 24.5273x |
+| 100 | 0.1093x | 1.0709x | 2.2565x | 10.9253x | 21.4483x |
+| 1000 | 0.3510x | 1.4680x | 1.5030x | 6.0454x | 10.3790x |
 
 - All three tables report synchronized host E2E speedups as `baseline/candidate`. `Hot steady-state` measures a repeated public call at each lane's declared hot cache state; its per-shape values supply the official metric used by the separate publication-floor section.
 - `After-init amortized(N) = (first_compute + (N-1) * hot_median) / N`; it excludes init.
@@ -37,5 +37,5 @@
 - Cache policy: `synchronize_and_clear_after_each_completed_shape`; resident multi-shape cache benchmarked: `no`; cold order: `deterministic_balanced_per_publication_contract_portfolio`; init order: `alternate_candidate_baseline_first_by_validation_shard_parity_then_shared_support`
 - Lifecycle timing convention: all three lifecycle tables are synchronized host E2E. Init/first-call brackets are CUPTI timestamp host diagnostics; separately, the hot GPU-span diagnostic remains strict correlated CUPTI activity timing.
 
-- Measured: `2026-07-08T23:29:04+00:00`
+- Measured: `2026-07-09T04:30:10+00:00`
 - Full summary: [`VALIDATION.json`](VALIDATION.json); per-shape results: [`BENCHMARK_RESULTS.json`](BENCHMARK_RESULTS.json)
diff --git a/cake_exports/kmeans/benchmarks/benchmark.py b/cake_exports/kmeans/benchmarks/benchmark.py
index 1baf0f47..df81bdcd 100644
--- a/cake_exports/kmeans/benchmarks/benchmark.py
+++ b/cake_exports/kmeans/benchmarks/benchmark.py
@@ -80,7 +80,7 @@ def _shape_from_record(record: dict[str, Any]) -> dict[str, Any]:
 PRECOMPUTED_BASELINE_NAME = "triton_h200_07cf_precomputed"
 BASELINE_REGISTRY_KEY = "triton_h200_07cf_dual_lane_v1"
 # Updated together with benchmark_data.json by the registry sync gate.
-BASELINE_REGISTRY_SHA256 = "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c"
+BASELINE_REGISTRY_SHA256 = "bdfd30338aa614f09817af1498c1115a0b1732a3340a1acbc172d0e4dd4674c4"
 REGISTRY_CANDIDATE_ENTRYPOINT = SEMANTIC_ENTRYPOINT
 MEASURED_CANDIDATE_ENTRYPOINT = "flashlib_cake_kmeans.interface:FlashKMeansAssignRuntime.compute"
 BASELINE_ENTRYPOINT = "benchmarks.flash_kmeans_triton_h200_raw_adapter:TritonH20007cfRawAdapter.compute"
@@ -99,7 +99,7 @@ def _shape_from_record(record: dict[str, Any]) -> dict[str, Any]:
     "registry_candidate_entrypoint": REGISTRY_CANDIDATE_ENTRYPOINT,
     "shared_preprocess": {
         "implementation_entrypoint": PREPROCESS_IMPL,
-        "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104",
+        "source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e",
         "result_source_sha256_field": "preprocess_source_sha256",
     },
     "official": {
@@ -901,6 +901,14 @@ def candidate_public_raw_fresh_pointer_call():
         raise RuntimeError("fresh-pointer runtime.compute call did not reuse the shape/stream launch plan")
     if not baseline_public_raw_fresh_info["runtime_cache_hit"]:
         raise RuntimeError("fresh-pointer 07cf raw-adapter call did not reuse the shape/stream norm plan")
+    if candidate_public_raw_info.get("hot_launch_path") != "cuda_graph":
+        raise RuntimeError(
+            "Flash-KMeans signature did not capture into a CUDA graph: "
+            f"hot_launch_path={candidate_public_raw_info.get('hot_launch_path')!r}, "
+            f"graph_capture_error={candidate_public_raw_info.get('graph_capture_error')!r}; "
+            "every contract signature freezes to a LaunchPlan today, so a "
+            "prepared-path fallback means the graph runtime silently degraded"
+        )
     candidate_shape_norm_fields = tuple(candidate_public_raw_shape_info.get("norm_compute_fields", ()))
     candidate_fresh_norm_fields = tuple(candidate_public_raw_info.get("norm_compute_fields", ()))
     if candidate_shape_norm_fields != candidate_fresh_norm_fields:
@@ -997,6 +1005,9 @@ def candidate_public_raw_fresh_pointer_call():
         "candidate_public_raw_fresh_pointer_cache_hit": bool(candidate_public_raw_info["runtime_cache_hit"]),
         "baseline_public_raw_fresh_pointer_cache_hit": bool(baseline_public_raw_fresh_info["runtime_cache_hit"]),
         "fresh_pointer_rebind_verified": True,
+        "candidate_hot_launch_path": candidate_public_raw_info.get("hot_launch_path"),
+        "candidate_graph_kernel_count": candidate_public_raw_info.get("graph_kernel_count"),
+        "candidate_graph_capture_error": candidate_public_raw_info.get("graph_capture_error"),
         "candidate_public_raw_cold_first_call_activity": candidate_public_raw_shape_info[
             "cold_first_call_activity"
         ],
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py
index 92905d4f..eea6567f 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/_row_norm.py
@@ -2,7 +2,7 @@
 
 from __future__ import annotations
 
-from dataclasses import dataclass
+from dataclasses import dataclass, field
 from typing import Any
 
 from .kernels import ExportedKernel, KernelSpec
@@ -78,6 +78,7 @@ class PreparedBF16PairRowNorm:
     dim: int
     compute_x: bool
     compute_c: bool
+    _input_carriers: Any = field(default=None, repr=False)
 
     def rebind(
         self,
@@ -99,6 +100,43 @@ def rebind(
     def launch(self, *, stream: Any = None, timeout_ms: float | None = None) -> None:
         self.launch_plan.launch(stream=stream, timeout_ms=timeout_ms)
 
+    def bind_hot(self, x: Any, centroids: Any) -> None:
+        """Overwrite both input pointer carriers in place without submitting.
+
+        Graph-captured runtimes bind here and replay the captured kernel
+        chain themselves; the carriers target the same persistent packed
+        argument buffer the captured node's parameter update reads. The
+        prepared norm outputs stay bound (slot-owned scratch with stable
+        pointers), so the caller's signature cache must guarantee the tensor
+        topology matches the preparation.
+        """
+
+        carriers = self._input_carriers
+        if carriers is None:
+            prevent_gc = self.launch_plan._packed._prevent_gc
+            carriers = (prevent_gc[0], prevent_gc[1])
+            self._input_carriers = carriers
+        carriers[0].value = x.data_ptr()
+        carriers[1].value = centroids.data_ptr()
+
+    def launch_hot(self, x: Any, centroids: Any) -> None:
+        """Overwrite both input pointer carriers and submit the launch.
+
+        The launch goes to its preparation-time stream — no re-marshal, no
+        per-launch stream query.
+        """
+
+        self.bind_hot(x, centroids)
+        self.launch_plan.launch(stream=None, timeout_ms=None)
+
+    def record_stream(self, stream: Any) -> None:
+        """Tie every prepared launch argument to ``stream`` before release."""
+
+        for value in self.launch_plan._keepalive:
+            record_stream = getattr(value, "record_stream", None)
+            if callable(record_stream):
+                record_stream(stream)
+
     def release_bound_callers(self, keepalive: Any, *, stream: Any = None) -> None:
         """Drop caller tensors while retaining one slot-owned scratch tensor."""
 
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0156.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0157.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0158.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0161.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0162.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0165.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
index fad9fa7f..4f6e1450 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0354.cu
@@ -268,10 +268,10 @@ kernel_flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1(__nv_bfloat
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3856035760 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3856035760 = *(uint16_t*)&_bval_3856035760;
-                uint32_t _addr_3856035760 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3856035760), "h"(_bits_3856035760) : "memory");
+                __nv_bfloat16 _bval_3404602512 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404602512 = *(uint16_t*)&_bval_3404602512;
+                uint32_t _addr_3404602512 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404602512), "h"(_bits_3404602512) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -455,8 +455,8 @@ kernel_flash_kmeans_assign_d112_k512_two_owner_peer_only_mma_f826_v1(__nv_bfloat
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3856021056 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3856021056), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405267776 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405267776), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
index c09a29a5..7ed658bb 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/cuda/dispatch_kernel_0356.cu
@@ -275,10 +275,10 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
             int row = i / 112;
             int col = i % 112;
             {
-                __nv_bfloat16 _bval_3843058912 = __float2bfloat16_rn(x_raw[i]);
-                uint16_t _bits_3843058912 = *(uint16_t*)&_bval_3843058912;
-                uint32_t _addr_3843058912 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
-                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3843058912), "h"(_bits_3843058912) : "memory");
+                __nv_bfloat16 _bval_3404531696 = __float2bfloat16_rn(x_raw[i]);
+                uint16_t _bits_3404531696 = *(uint16_t*)&_bval_3404531696;
+                uint32_t _addr_3404531696 = static_cast<uint32_t>((sx_addr + (unsigned int)(row * 224 + col * 2)));
+                asm volatile("st.shared.b16 [%0], %1;" :: "r"(_addr_3404531696), "h"(_bits_3404531696) : "memory");
             }
         }
         asm volatile("barrier.sync 3, %0;" :: "r"(256));
@@ -462,8 +462,8 @@ kernel_flash_kmeans_assign_d112_consumer_scoped_direct_mma_view_handoff_e5e1_v1(
                     int rr = lane / 4 + rp * 8;
                     int cc = lane % 4 * 2 + cp;
                     {
-                        uint32_t _addr_3843008560 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
-                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3843008560), "f"(acc[rp * 2 + cp]) : "memory");
+                        uint32_t _addr_3405188304 = static_cast<uint32_t>((ss_addr + (unsigned int)((group * 64 + row_base + rr) * 32 + cc * 4)));
+                        asm volatile("st.shared.f32 [%0], %1;" :: "r"(_addr_3405188304), "f"(acc[rp * 2 + cp]) : "memory");
                     }
                 }
             }
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py b/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
index f93bb51c..87fed6c0 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/interface.py
@@ -4,13 +4,17 @@
 from collections import OrderedDict
 from contextlib import contextmanager
 from dataclasses import dataclass, field
+from functools import wraps
 from threading import Condition, Event, RLock
 from typing import Any
 
 from ._dispatch import flash_kmeans_assign_dispatcher as _dispatcher
-from ._runtime import detect_gpu_arch, launch_context, runtime_activity_snapshot
+from ._dispatch_runtime import dispatch_launch_options
+from ._launch_plan import GraphCaptureUnsupported, build_graph_exec_plan, build_launch_plan
+from ._runtime import detect_gpu_arch, runtime_activity_snapshot
 
 SEMANTIC_ENTRYPOINT = "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval"
+_PREPARE_LOCK = RLock()
 
 
 @dataclass(frozen=True)
@@ -31,17 +35,63 @@ def selected_route(self) -> str:
         return self.launch_plan.selected_route
 
 
+@dataclass(frozen=True)
+class _ResolvedRoute:
+    """Frozen-cascade decision adapted to the shared plan-constructor contract.
+
+    ``launch`` submits through the root dispatcher, which re-derives exactly
+    this decision from the same frozen guard cascade — the cascade remains the
+    single source of routing truth and runs once per signature, at plan
+    construction (or per call for host-data-dependent routes).
+    """
+
+    route_id: str
+    launch_entrypoint: str
+    exact_contract: bool = True
+
+    def launch(
+        self,
+        inputs: dict[str, Any],
+        *,
+        stream: Any = None,
+        timeout_ms: float | None = None,
+    ) -> Any:
+        with dispatch_launch_options(stream=stream, timeout_ms=timeout_ms):
+            return _dispatcher.launch_for_eval(inputs)
+
+
 @dataclass
 class _RuntimeSlot:
-    inputs: dict[str, Any]
-    launch_plan: Any
-    norm_plan: Any = None
-    internal_x_sq: bool = False
-    internal_c_sq: bool = False
-    norm_compute_fields: tuple[str, ...] = ()
-    record_each_call_fields: tuple[str, ...] = ("x", "centroids")
-    norm_rebind_program: tuple[tuple[str, Any], ...] = ()
+    """One stream-bound, signature-specialized LaunchPlan plus support state.
+
+    ``plan`` freezes the resolved route's leaf launches — including any
+    zero-pad staging kernels the route delegates through — or keeps the cached
+    per-call launcher for host-data-dependent routes. ``norm_plan`` is the
+    route-required fused BF16 pair row-norm support launch, bound by pointer
+    overwrite before the plan; its outputs are the slot-owned ``x_sq``/``c_sq``
+    scratch with stable pointers. ``graph`` is the signature's captured CUDA
+    graph over the full norm + route kernel chain; when set, a hot call binds
+    pointers host-side and replays the graph instead of submitting the
+    prepared launches one by one (``graph_capture_error`` records why a frozen
+    plan stayed on the prepared path). ``default_outputs`` alternates between
+    two plan-owned tensors so consecutive default-output calls never hand the
+    caller the allocation the previous call returned. ``default_flip`` is only
+    read or written while ``lock`` is held.
+    """
+
+    plan: Any
+    route: Any
+    norm_plan: Any
+    x_sq: Any
+    c_sq: Any
+    internal_x_sq: bool
+    internal_c_sq: bool
+    norm_compute_fields: tuple[str, ...]
+    default_outputs: tuple[Any, Any]
+    graph: Any = None
+    graph_capture_error: str | None = None
     lock: RLock = field(default_factory=RLock, repr=False)
+    default_flip: int = 0
 
 
 @dataclass
@@ -50,6 +100,26 @@ class _PendingPreparation:
     error: BaseException | None = field(default=None, repr=False)
 
 
+def _guard_runtime_compute(method: Any) -> Any:
+    """Keep clear() from crossing an in-progress lookup/rebind/enqueue call."""
+
+    @wraps(method)
+    def guarded(self: Any, *args: Any, **kwargs: Any) -> Any:
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            self._active_computes += 1
+        try:
+            return method(self, *args, **kwargs)
+        finally:
+            with self._lifecycle:
+                self._active_computes -= 1
+                if self._active_computes == 0:
+                    self._lifecycle.notify_all()
+
+    return guarded
+
+
 def _normalize_device_index(torch: Any, device: Any) -> int:
     if device is None:
         return int(torch.cuda.current_device())
@@ -123,12 +193,23 @@ def _device_stream_context(
             yield resolved_stream
 
 
-def _pointer_alias_topology(*tensors: Any) -> tuple[int, ...]:
-    """Canonical pointer-equivalence classes independent of concrete addresses."""
+def _signature_alias_topology(
+    x: Any,
+    centroids: Any,
+    x_sq: Any,
+    c_sq: Any,
+    out: Any,
+) -> tuple[int, ...]:
+    """Canonical pointer-equivalence classes independent of concrete addresses.
+
+    A default output comes from the signature slot's plan-owned pool, which
+    can never alias a live caller tensor, so ``out is None`` contributes a
+    fresh class without reading any pointer.
+    """
 
     classes: dict[int, int] = {}
     topology: list[int] = []
-    for tensor in tensors:
+    for tensor in (x, centroids, x_sq, c_sq):
         if tensor is None:
             topology.append(-1)
             continue
@@ -136,17 +217,71 @@ def _pointer_alias_topology(*tensors: Any) -> tuple[int, ...]:
         if pointer not in classes:
             classes[pointer] = len(classes)
         topology.append(classes[pointer])
+    if out is None:
+        topology.append(len(classes))
+    else:
+        pointer = int(out.data_ptr())
+        if pointer not in classes:
+            classes[pointer] = len(classes)
+        topology.append(classes[pointer])
     return tuple(topology)
 
 
+def _require_owned_output(result: Any, inputs: dict[str, Any]) -> None:
+    """Reject routes whose hot path would require an uncaptured output copy."""
+
+    produced = result.get("cluster_ids") if isinstance(result, dict) else result
+    if produced is None:
+        return
+    out = inputs["out"]
+    if produced is not out and int(produced.data_ptr()) != int(out.data_ptr()):
+        raise RuntimeError(
+            "prepared Flash-KMeans route must write the caller-owned output through captured launches"
+        )
+
+
+def _validate_compute_tensors(
+    torch: Any,
+    x: Any,
+    centroids: Any,
+    *,
+    device_index: int,
+) -> tuple[int, int, int, int]:
+    """Validate the public compute ABI without allocating anything."""
+
+    if not all(isinstance(item, torch.Tensor) and item.is_cuda for item in (x, centroids)):
+        raise TypeError("x and centroids must be CUDA torch.Tensor objects")
+    if x.dtype is not torch.bfloat16 or centroids.dtype is not torch.bfloat16:
+        raise TypeError("x and centroids dtype must be bfloat16")
+    if x.ndim != 3 or centroids.ndim != 3 or not x.is_contiguous() or not centroids.is_contiguous():
+        raise ValueError("x and centroids must be contiguous [B, rows, D] tensors")
+    bsz, n_points, dim = map(int, x.shape)
+    c_bsz, n_clusters, c_dim = map(int, centroids.shape)
+    if (bsz, dim) != (c_bsz, c_dim) or x.device != centroids.device:
+        raise ValueError("x and centroids batch/feature dimensions and device must match")
+    input_device_index = x.device.index
+    if input_device_index is None:
+        input_device_index = torch.cuda.current_device()
+    if int(input_device_index) != int(device_index):
+        raise ValueError(
+            f"Flash-KMeans runtime targets CUDA device {device_index}, got input device {input_device_index}"
+        )
+    return bsz, n_points, dim, n_clusters
+
+
 class FlashKMeansAssignRuntime:
     """Long-lived KMeans assignment runtime with per-shape, per-stream plans.
 
-    ``compute`` accepts new tensors and new shapes.  The first call for one
-    shape/stream resolves and captures the exact route; later calls only
-    refresh data-derived norms, rebind caller tensor pointers, and enqueue the
-    already captured launch sequence.  Workspace is never shared across CUDA
-    streams.
+    ``compute`` accepts new tensors and new shapes. The first call for one
+    signature runs the frozen guard cascade once, freezes the resolved
+    route's exact leaf launches (plus the route-required fused pair row-norm
+    support launch) into a per-signature plan, and captures the full kernel
+    chain into one CUDA graph. Cache hits overwrite the recorded pointer
+    carriers in place and replay the graph on the plan's stream — no dispatch
+    re-evaluation, no argument re-marshalling, no per-launch stream query,
+    and no per-call default-output allocation (defaults ping-pong between two
+    plan-owned tensors, so consecutive default-output calls never alias).
+    Workspace is never shared across CUDA streams.
     """
 
     def __init__(
@@ -187,22 +322,6 @@ def __init__(
         self._hits = 0
         self._misses = 0
 
-    @contextmanager
-    def _compute_lifecycle(self):
-        """Admit concurrent compute calls while making clear() an exclusive barrier."""
-
-        with self._lifecycle:
-            while self._clearing:
-                self._lifecycle.wait()
-            self._active_computes += 1
-        try:
-            yield
-        finally:
-            with self._lifecycle:
-                self._active_computes -= 1
-                if self._active_computes == 0:
-                    self._lifecycle.notify_all()
-
     def cache_info(self) -> dict[str, int | None]:
         with self._cache_lock:
             return {
@@ -212,92 +331,7 @@ def cache_info(self) -> dict[str, int | None]:
                 "max_cached_shapes": self.max_cached_shapes,
             }
 
-    def _cache_key(
-        self,
-        inputs: dict[str, Any],
-        stream_handle: int,
-        *,
-        caller_supplied_out: bool = True,
-    ) -> tuple[Any, ...]:
-        alias_topology: tuple[int, ...]
-        if not caller_supplied_out and inputs["x_sq"] is None and inputs["c_sq"] is None:
-            x_pointer = int(inputs["x"].data_ptr())
-            centroids_pointer = int(inputs["centroids"].data_ptr())
-            if x_pointer and centroids_pointer:
-                # The internally allocated output cannot alias either live
-                # input. Preserve the canonical class numbering for both
-                # possible x/centroid relationships without reading it.
-                alias_topology = (
-                    0,
-                    0 if x_pointer == centroids_pointer else 1,
-                    -1,
-                    -1,
-                    1 if x_pointer == centroids_pointer else 2,
-                )
-            else:
-                alias_topology = _pointer_alias_topology(
-                    inputs["x"],
-                    inputs["centroids"],
-                    inputs["x_sq"],
-                    inputs["c_sq"],
-                    inputs["out"],
-                )
-        else:
-            alias_topology = _pointer_alias_topology(
-                inputs["x"],
-                inputs["centroids"],
-                inputs["x_sq"],
-                inputs["c_sq"],
-                inputs["out"],
-            )
-        return (
-            self.device_index,
-            self.arch,
-            int(inputs["B"]),
-            int(inputs["N"]),
-            int(inputs["D"]),
-            int(inputs["K"]),
-            str(inputs["dtype"]),
-            alias_topology,
-            int(stream_handle),
-        )
-
-    def clear(self, *, synchronize: bool = True) -> None:
-        """Exclusively release slots after admitted host calls finish.
-
-        The default waits for device completion. With ``synchronize=False``,
-        recorded-stream ownership keeps tensor storage allocator-safe, but the
-        caller remains responsible for observing asynchronous completion.
-        """
-        import torch
-
-        with self._lifecycle:
-            while self._clearing:
-                self._lifecycle.wait()
-            try:
-                self._clearing = True
-                while self._active_computes:
-                    self._lifecycle.wait()
-                if synchronize:
-                    with torch.cuda.device(self.device_index):
-                        torch.cuda.synchronize()
-                with self._cache_lock:
-                    self._slots.clear()
-                    self._hits = 0
-                    self._misses = 0
-            finally:
-                self._clearing = False
-                self._lifecycle.notify_all()
-
-    def warmup(self, *args: Any, synchronize: bool = True, **kwargs: Any):
-        result = self.compute(*args, **kwargs)
-        if synchronize:
-            import torch
-
-            with torch.cuda.device(self.device_index):
-                torch.cuda.synchronize()
-        return result
-
+    @_guard_runtime_compute
     def compute(
         self,
         x: Any,
@@ -310,117 +344,132 @@ def compute(
         timeout_ms: float | None = None,
         return_info: bool = False,
     ):
-        with self._compute_lifecycle():
-            torch = self._torch
-            if int(torch.cuda.current_device()) == self.device_index:
-                if stream is None:
-                    resolved_stream = torch.cuda.current_stream(self.device_index)
-                    return self._compute(
-                        x,
-                        centroids,
-                        out=out,
-                        x_sq=x_sq,
-                        c_sq=c_sq,
-                        stream=resolved_stream,
-                        timeout_ms=timeout_ms,
-                        return_info=return_info,
-                    )
-                resolved_stream = _resolve_stream(torch, self.device_index, stream)
-                current_stream = torch.cuda.current_stream(self.device_index)
-                if _same_cuda_stream(resolved_stream, current_stream):
-                    return self._compute(
-                        x,
-                        centroids,
-                        out=out,
-                        x_sq=x_sq,
-                        c_sq=c_sq,
-                        stream=resolved_stream,
-                        timeout_ms=timeout_ms,
-                        return_info=return_info,
-                    )
-                with torch.cuda.stream(resolved_stream):
-                    return self._compute(
-                        x,
-                        centroids,
-                        out=out,
-                        x_sq=x_sq,
-                        c_sq=c_sq,
-                        stream=resolved_stream,
-                        timeout_ms=timeout_ms,
-                        return_info=return_info,
-                    )
-            with torch.cuda.device(self.device_index):
-                resolved_stream = _resolve_stream(torch, self.device_index, stream)
-                current_stream = torch.cuda.current_stream(self.device_index)
-                if _same_cuda_stream(resolved_stream, current_stream):
-                    return self._compute(
-                        x,
-                        centroids,
-                        out=out,
-                        x_sq=x_sq,
-                        c_sq=c_sq,
-                        stream=resolved_stream,
-                        timeout_ms=timeout_ms,
-                        return_info=return_info,
-                    )
-                with torch.cuda.stream(resolved_stream):
-                    return self._compute(
-                        x,
-                        centroids,
-                        out=out,
-                        x_sq=x_sq,
-                        c_sq=c_sq,
-                        stream=resolved_stream,
-                        timeout_ms=timeout_ms,
-                        return_info=return_info,
-                    )
+        """Run one KMeans assignment through this signature's launch plan.
+
+        A cache miss runs the frozen guard cascade once and freezes its exact
+        leaf launches into a per-signature plan with a captured CUDA graph.
+        Cache hits are host-side pointer binding plus one graph replay on the
+        plan's stream. A caller-provided ``out=`` is written through; default
+        outputs come from the signature's plan-owned pool, so a default-output
+        result must be consumed before two further default-output calls of the
+        same signature reuse its storage.
+        """
 
-    def _compute(
-        self,
-        x: Any,
-        centroids: Any,
-        *,
-        out: Any | None,
-        x_sq: Any | None,
-        c_sq: Any | None,
-        stream: Any,
-        timeout_ms: float | None,
-        return_info: bool,
-    ):
-        caller_supplied_out = out is not None
-        effective_timeout_ms = self.timeout_ms if timeout_ms is None else _validate_timeout(timeout_ms)
-        inputs, resolved_stream, resolved_arch = _prepare_inputs(
+        torch = self._torch
+        bsz, n_points, dim, n_clusters = _validate_compute_tensors(
+            torch,
             x,
             centroids,
-            out=out,
-            x_sq=x_sq,
-            c_sq=c_sq,
             device_index=self.device_index,
-            arch=self.arch,
-            stream=stream,
-            arch_is_validated=True,
-            timeout_ms=effective_timeout_ms,
-            defer_missing_norms=True,
-            _context_is_active=True,
-            _torch=self._torch,
         )
+        effective_timeout_ms = self.timeout_ms if timeout_ms is None else _validate_timeout(timeout_ms)
+        resolved_stream = _resolve_stream(torch, self.device_index, stream)
         stream_handle = int(resolved_stream.cuda_stream)
-        key = self._cache_key(
-            inputs,
+        if out is not None:
+            _require_aux_tensor(
+                out,
+                name="out",
+                shape=(bsz, n_points),
+                dtype=torch.int32,
+                device=x.device,
+            )
+        if x_sq is not None:
+            _require_aux_tensor(
+                x_sq,
+                name="x_sq",
+                shape=(bsz, n_points),
+                dtype=torch.float32,
+                device=x.device,
+            )
+        if c_sq is not None:
+            _require_aux_tensor(
+                c_sq,
+                name="c_sq",
+                shape=(bsz, n_clusters),
+                dtype=torch.float32,
+                device=x.device,
+            )
+        key = (
+            self.device_index,
+            self.arch,
+            bsz,
+            n_points,
+            dim,
+            n_clusters,
+            "bfloat16",
+            x_sq is None,
+            c_sq is None,
+            _signature_alias_topology(x, centroids, x_sq, c_sq, out),
             stream_handle,
-            caller_supplied_out=caller_supplied_out,
         )
         activity_before = runtime_activity_snapshot() if return_info else None
-        slot, cache_hit, owns_slot_lock = self._get_or_create_slot(
-            key,
-            inputs,
-            resolved_stream=resolved_stream,
-            resolved_arch=resolved_arch,
-            _context_is_active=True,
-        )
+        with self._cache_lock:
+            slot = self._slots.get(key)
+            if slot is not None:
+                self._slots.move_to_end(key)
+                self._hits += 1
+        cache_hit = slot is not None
+        owns_slot_lock = False
+        if slot is None:
+            slot, owns_slot_lock = self._create_slot(
+                key,
+                x=x,
+                centroids=centroids,
+                out=out,
+                x_sq=x_sq,
+                c_sq=c_sq,
+                shape=(bsz, n_points, dim, n_clusters),
+                stream=resolved_stream,
+            )
+            cache_hit = not owns_slot_lock
         activity_after = runtime_activity_snapshot() if return_info else None
         if not owns_slot_lock:
             slot.lock.acquire()
+        try:
+            if slot.plan.stream_handle != stream_handle:
+                raise RuntimeError("cached Flash-KMeans slot changed its prepared stream")
+            if out is None:
+                bound_out = slot.default_outputs[slot.default_flip]
+                slot.default_flip ^= 1
+            else:
+                bound_out = out
+            bindings = {
+                "x": x,
+                "centroids": centroids,
+                "x_sq": slot.x_sq if slot.internal_x_sq else x_sq,
+                "c_sq": slot.c_sq if slot.internal_c_sq else c_sq,
+                "out": bound_out,
+            }
+            try:
+                # Bind first (tensor-map refresh + pointer overwrite are host
+                # work), then enqueue the norm support launch, then submit
+                # the plan's kernels. Binding after the norm would turn a
+                # fresh-pointer tensor-map re-encode into a GPU inter-kernel
+                # gap between the norm kernel and the route's first kernel.
+                # A captured signature does every bind host-side, then one
+                # graph replay covers the whole norm + route kernel chain.
+                if slot.graph is not None:
+                    slot.plan.bind_hot(bindings)
+                    if slot.norm_plan is not None:
+                        slot.norm_plan.bind_hot(x, centroids)
+                    slot.graph.submit_hot(timeout_ms=effective_timeout_ms)
+                else:
+                    slot.plan.bind_hot(bindings)
+                    if slot.norm_plan is not None:
+                        slot.norm_plan.launch_hot(x, centroids)
+                    slot.plan.submit_hot(timeout_ms=effective_timeout_ms)
+            finally:
+                # Slot-owned norm scratch and pooled default outputs are
+                # allocated on the plan's stream and only released through
+                # clear(); caller-provided tensors may live on another
+                # stream, so record those for allocator safety even on
+                # partial submission.
+                _record_stream(resolved_stream, x, centroids, x_sq, c_sq, out)
+        finally:
+            slot.lock.release()
+
+        if not return_info:
+            return bound_out
         norm_mode = (
             "fused_bf16_pair_row_norm:" + ",".join(slot.norm_compute_fields)
             if slot.norm_compute_fields
@@ -428,74 +477,6 @@ def _compute(
             if slot.internal_x_sq or slot.internal_c_sq
             else "explicit_precomputed"
         )
-        try:
-            if cache_hit:
-                if slot.launch_plan.stream_handle != stream_handle:
-                    raise RuntimeError("cached Flash-KMeans slot changed its prepared stream")
-                for name in ("x", "centroids", "out"):
-                    slot.inputs[name] = inputs[name]
-                if not slot.internal_x_sq:
-                    slot.inputs["x_sq"] = inputs["x_sq"]
-                if not slot.internal_c_sq:
-                    slot.inputs["c_sq"] = inputs["c_sq"]
-                slot.inputs["_norm_mode"] = norm_mode
-            # Protect every new caller-owned tensor before non-retaining
-            # rebind. Slot-owned norms and a default output are allocated
-            # on this permanently bound stream, so they do not need
-            # repeated allocator ownership calls.
-            _record_stream_inputs(
-                resolved_stream,
-                slot.inputs,
-                slot.record_each_call_fields,
-            )
-            if caller_supplied_out:
-                _record_stream(resolved_stream, slot.inputs["out"])
-            if cache_hit:
-                # Slot lookup already proved the public alias topology and
-                # stream identity. Rebind only the scrubbed pointer carriers
-                # needed by this fixed-stream launch sequence.
-                slot.launch_plan.direct_launcher._rebind_stream_bound_scrubbed_inputs(
-                    slot.inputs,
-                    stream=resolved_stream,
-                )
-            if slot.norm_plan is not None:
-                try:
-                    if cache_hit:
-                        _rebind_stream_bound_norm_inputs(slot)
-                    else:
-                        slot.norm_plan.rebind(
-                            slot.inputs["x"],
-                            slot.inputs["centroids"],
-                            slot.inputs["x_sq"],
-                            slot.inputs["c_sq"],
-                            stream=resolved_stream,
-                        )
-                    slot.norm_plan.launch(
-                        stream=resolved_stream,
-                        timeout_ms=effective_timeout_ms,
-                    )
-                finally:
-                    if not cache_hit:
-                        _prepare_stream_bound_norm_rebind(slot)
-            slot.launch_plan._launch_stream_bound_recorded(
-                timeout_ms=effective_timeout_ms,
-            )
-            output = slot.inputs["out"]
-        finally:
-            try:
-                if not cache_hit:
-                    slot.launch_plan.direct_launcher.release_bound_inputs()
-            finally:
-                for name in ("x", "centroids", "out"):
-                    slot.inputs[name] = None
-                if not slot.internal_x_sq:
-                    slot.inputs["x_sq"] = None
-                if not slot.internal_c_sq:
-                    slot.inputs["c_sq"] = None
-                slot.lock.release()
-
-        if not return_info:
-            return output
         cold_activity = {
             "source_read_occurred": bool(activity_after["source_reads"] > activity_before["source_reads"]),
             "nvrtc_compile_occurred": bool(
@@ -504,42 +485,55 @@ def _compute(
             "module_load_occurred": bool(activity_after["module_loads"] > activity_before["module_loads"]),
             "scratch_allocation_occurred": not cache_hit,
         }
-        return output, {
+        return bound_out, {
             "semantic_entrypoint": SEMANTIC_ENTRYPOINT,
-            "selected_route": slot.launch_plan.selected_route,
-            "launch_entrypoint": slot.launch_plan.launch_entrypoint,
-            "exact_launch_plan": True,
+            "selected_route": slot.route.route_id,
+            "launch_entrypoint": slot.route.launch_entrypoint,
+            "exact_launch_plan": slot.route.exact_contract,
             "runtime_cache_hit": cache_hit,
-            "assignment_launch_count": slot.launch_plan.launch_count,
+            "assignment_launch_count": int(slot.plan.launch_count),
             "norm_launch_count": int(slot.norm_plan is not None),
             "norm_compute_fields": list(slot.norm_compute_fields),
-            "runtime_launch_count": slot.launch_plan.launch_count + int(slot.norm_plan is not None),
+            "runtime_launch_count": int(slot.plan.launch_count) + int(slot.norm_plan is not None),
             "norm_mode": norm_mode,
-            "arch": slot.launch_plan.arch,
-            "device_index": slot.launch_plan.device_index,
-            "stream_handle": slot.launch_plan.stream_handle,
+            "hot_launch_path": "cuda_graph" if slot.graph is not None else "prepared_launches",
+            "graph_kernel_count": None if slot.graph is None else int(slot.graph.launch_count),
+            "graph_capture_error": slot.graph_capture_error,
+            "arch": self.arch,
+            "device_index": self.device_index,
+            "stream_handle": stream_handle,
             "cold_first_call_activity": cold_activity,
         }
 
-    def _get_or_create_slot(
+    def _create_slot(
         self,
         key: tuple[Any, ...],
-        inputs: dict[str, Any],
         *,
-        resolved_stream: Any,
-        resolved_arch: str,
-        _context_is_active: bool = False,
-    ) -> tuple[_RuntimeSlot, bool, bool]:
-        """Return a slot; a newly published slot is returned with its lock held."""
-
-        import torch
+        x: Any,
+        centroids: Any,
+        out: Any | None,
+        x_sq: Any | None,
+        c_sq: Any | None,
+        shape: tuple[int, int, int, int],
+        stream: Any,
+    ) -> tuple[_RuntimeSlot, bool]:
+        """Construct and publish this signature's LaunchPlan (the slow path).
+
+        Returns ``(slot, owns_slot_lock)``. A newly published slot is returned
+        with its lock held so the constructing call launches first; when
+        another thread published the slot while this one waited, the existing
+        slot is returned unlocked and counted as a cache hit. Preparation
+        never holds the runtime cache lock, so resident hot shapes stay
+        unblocked while a cold signature captures.
+        """
 
         while True:
             with self._cache_lock:
                 slot = self._slots.get(key)
                 if slot is not None:
+                    self._slots.move_to_end(key)
                     self._hits += 1
-                    return slot, True, False
+                    return slot, False
                 pending = self._preparing.get(key)
                 if pending is None:
                     if (
@@ -558,70 +552,104 @@ def _get_or_create_slot(
 
         slot: _RuntimeSlot | None = None
         try:
-            with _device_stream_context(
-                torch,
-                self.device_index,
-                resolved_stream,
-                context_is_active=_context_is_active,
-            ):
-                internal_x_sq = inputs["x_sq"] is None
-                internal_c_sq = inputs["c_sq"] is None
-                if internal_x_sq:
-                    inputs["x_sq"] = torch.empty(
-                        (int(inputs["B"]), int(inputs["N"])),
-                        dtype=torch.float32,
-                        device=inputs["x"].device,
+            import torch
+
+            from ._row_norm import prepare_bf16_pair_row_norm
+
+            bsz, n_points, dim, n_clusters = shape
+            internal_x_sq = x_sq is None
+            internal_c_sq = c_sq is None
+            with torch.cuda.device(self.device_index), torch.cuda.stream(stream):
+                default_outputs = tuple(
+                    torch.empty((bsz, n_points), dtype=torch.int32, device=x.device) for _pair in range(2)
+                )
+                slot_x_sq = (
+                    torch.empty((bsz, n_points), dtype=torch.float32, device=x.device)
+                    if internal_x_sq
+                    else x_sq
+                )
+                slot_c_sq = (
+                    torch.empty((bsz, n_clusters), dtype=torch.float32, device=x.device)
+                    if internal_c_sq
+                    else c_sq
+                )
+                capture_out = out if out is not None else default_outputs[0]
+                inputs = {
+                    "B": bsz,
+                    "N": n_points,
+                    "D": dim,
+                    "K": n_clusters,
+                    "dtype": "bfloat16",
+                    "x": x,
+                    "centroids": centroids,
+                    "x_sq": slot_x_sq,
+                    "c_sq": slot_c_sq,
+                    "out": capture_out,
+                }
+                with _PREPARE_LOCK:
+                    decision = _dispatcher.select_route(inputs)
+                    route = _ResolvedRoute(
+                        route_id=str(decision.route_id),
+                        launch_entrypoint=str(decision.entrypoint),
                     )
-                if internal_c_sq:
-                    inputs["c_sq"] = torch.empty(
-                        (int(inputs["B"]), int(inputs["K"])),
-                        dtype=torch.float32,
-                        device=inputs["x"].device,
+                    plan = build_launch_plan(
+                        inputs,
+                        stream=stream,
+                        arch=self.arch,
+                        validate_result=_require_owned_output,
+                        route=route,
                     )
-                launch_plan = _dispatcher.prepare_launch_plan(
-                    inputs,
-                    arch=resolved_arch,
-                    stream=resolved_stream,
-                    timeout_ms=None,
-                )
-                # This slot is permanently bound to resolved_stream. Record
-                # route-private scratch and descriptor storage once while the
-                # plan owns its original caller tensors; subsequent computes
-                # separately record every new public tensor before rebinding.
-                launch_plan.direct_launcher.record_stream(resolved_stream)
-                bound_input_keys = set(launch_plan.direct_launcher.bound_input_keys)
-                compute_x_sq = internal_x_sq and "x_sq" in bound_input_keys
-                compute_c_sq = internal_c_sq and "c_sq" in bound_input_keys
+                bound_keys = getattr(plan, "bound_input_keys", None)
+                bound = None if bound_keys is None else set(bound_keys)
+                # A frozen plan reports exactly which public inputs its
+                # captured launches bind; routes whose kernels never read a
+                # norm skip computing it. A per-call plan re-executes the
+                # route's host program, so provide every internal norm it
+                # could consume.
+                compute_x_sq = internal_x_sq and (bound is None or "x_sq" in bound)
+                compute_c_sq = internal_c_sq and (bound is None or "c_sq" in bound)
                 norm_plan = None
                 if compute_x_sq or compute_c_sq:
-                    from ._row_norm import prepare_bf16_pair_row_norm
-
                     norm_plan = prepare_bf16_pair_row_norm(
-                        inputs["x"],
-                        inputs["centroids"],
-                        inputs["x_sq"],
-                        inputs["c_sq"],
+                        x,
+                        centroids,
+                        slot_x_sq,
+                        slot_c_sq,
                         compute_x=compute_x_sq,
                         compute_c=compute_c_sq,
-                        arch=resolved_arch,
-                        stream=resolved_stream,
+                        arch=self.arch,
+                        stream=stream,
                     )
-                norm_compute_fields = tuple(
-                    name for name, enabled in (("x_sq", compute_x_sq), ("c_sq", compute_c_sq)) if enabled
-                )
+                # Capture the signature's stable kernel chain (the fused pair
+                # norm first, then the frozen route launches — the exact hot
+                # submission order) into one CUDA graph. Per-call routes and
+                # launch modes without a validated capture path stay on the
+                # prepared-launch hot path, with the reason recorded; any
+                # other capture failure is an error, not a fallback.
+                graph_plan = None
+                graph_capture_error: str | None = None
+                try:
+                    graph_plan = build_graph_exec_plan(
+                        plan,
+                        support_launches=() if norm_plan is None else (norm_plan.launch_plan,),
+                    )
+                except GraphCaptureUnsupported as unsupported:
+                    graph_capture_error = str(unsupported)
+            norm_compute_fields = tuple(
+                name for name, enabled in (("x_sq", compute_x_sq), ("c_sq", compute_c_sq)) if enabled
+            )
             slot = _RuntimeSlot(
-                inputs=inputs,
-                launch_plan=launch_plan,
+                plan=plan,
+                route=route,
                 norm_plan=norm_plan,
+                x_sq=slot_x_sq,
+                c_sq=slot_c_sq,
                 internal_x_sq=internal_x_sq,
                 internal_c_sq=internal_c_sq,
                 norm_compute_fields=norm_compute_fields,
-                record_each_call_fields=(
-                    "x",
-                    "centroids",
-                    *(("x_sq",) if not internal_x_sq else ()),
-                    *(("c_sq",) if not internal_c_sq else ()),
-                ),
+                default_outputs=default_outputs,
+                graph=graph_plan,
+                graph_capture_error=graph_capture_error,
             )
             slot.lock.acquire()
         except BaseException as error:
@@ -667,7 +695,63 @@ def _get_or_create_slot(
                     pending.event.set()
             slot.lock.release()
             raise
-        return slot, False, True
+        return slot, True
+
+    def clear(self, *, synchronize: bool = True) -> None:
+        """Exclusively release slots after admitted host calls finish.
+
+        The default waits for device completion and destroys the driver graph
+        handles eagerly. With ``synchronize=False``, every plan-held launch
+        argument, slot-owned norm buffer, and pooled default output is tied to
+        its plan's stream via ``record_stream`` before release, keeping tensor
+        storage allocator-safe; graph handles are only dropped (an executing
+        graph must never be destroyed underneath the device) and the caller
+        remains responsible for observing asynchronous completion.
+        """
+        import torch
+
+        with self._lifecycle:
+            while self._clearing:
+                self._lifecycle.wait()
+            try:
+                self._clearing = True
+                while self._active_computes:
+                    self._lifecycle.wait()
+                if synchronize:
+                    with torch.cuda.device(self.device_index):
+                        torch.cuda.synchronize()
+                with self._cache_lock:
+                    if synchronize:
+                        for slot in self._slots.values():
+                            if slot.graph is not None:
+                                slot.graph.destroy()
+                    else:
+                        for slot in self._slots.values():
+                            plan_stream = slot.plan.torch_stream
+                            slot.plan.record_stream(plan_stream)
+                            if slot.norm_plan is not None:
+                                slot.norm_plan.record_stream(plan_stream)
+                            _record_stream(
+                                plan_stream,
+                                slot.x_sq,
+                                slot.c_sq,
+                                *slot.default_outputs,
+                            )
+                    self._slots.clear()
+                    self._hits = 0
+                    self._misses = 0
+            finally:
+                self._clearing = False
+                self._lifecycle.notify_all()
+
+    def warmup(self, *args: Any, synchronize: bool = True, **kwargs: Any):
+        result = self.compute(*args, **kwargs)
+        if synchronize:
+            import torch
+
+            with torch.cuda.device(self.device_index):
+                torch.cuda.synchronize()
+        return result
 
 
 def init(
@@ -706,23 +790,8 @@ def _require_aux_tensor(
 def _record_stream(stream: Any, *tensors: Any) -> None:
     seen: set[int] = set()
     for tensor in tensors:
-        identity = id(tensor)
-        if identity in seen:
+        if tensor is None:
             continue
-        seen.add(identity)
-        record_stream = getattr(tensor, "record_stream", None)
-        if callable(record_stream):
-            record_stream(stream)
-
-
-def _record_stream_inputs(
-    stream: Any,
-    inputs: dict[str, Any],
-    fields: tuple[str, ...],
-) -> None:
-    seen: set[int] = set()
-    for name in fields:
-        tensor = inputs[name]
         identity = id(tensor)
         if identity in seen:
             continue
@@ -732,35 +801,11 @@ def _record_stream_inputs(
             record_stream(stream)
 
 
-def _rebind_stream_bound_norm_inputs(slot: _RuntimeSlot) -> None:
-    """Update one validated slot's prepared norm pointer carriers in place."""
-
-    if not slot.norm_rebind_program:
-        raise RuntimeError("cached KMeans norm launch has no fixed-stream rebind program")
-    pointer_updates = tuple(
-        (carrier, int(slot.inputs[name].data_ptr()))
-        for name, carrier in slot.norm_rebind_program
-    )
-    for carrier, pointer in pointer_updates:
-        carrier.value = pointer
-
+def _tensor_device_index(tensor: Any) -> int:
+    import torch
 
-def _prepare_stream_bound_norm_rebind(slot: _RuntimeSlot) -> None:
-    """Scrub cold norm callers and retain only the slot's dynamic carriers."""
-
-    all_bindings = ((0, "x"), (1, "centroids"), (2, "x_sq"), (3, "c_sq"))
-    full_program = slot.norm_plan.launch_plan._scrub_stream_bound_pointer_keepalives(
-        all_bindings
-    )
-    dynamic_names = {
-        "x",
-        "centroids",
-        *(("x_sq",) if not slot.internal_x_sq else ()),
-        *(("c_sq",) if not slot.internal_c_sq else ()),
-    }
-    slot.norm_rebind_program = tuple(
-        (name, carrier) for name, carrier in full_program if name in dynamic_names
-    )
+    index = tensor.device.index
+    return int(torch.cuda.current_device() if index is None else index)
 
 
 def _prepare_inputs(
@@ -980,6 +1025,23 @@ def flash_kmeans_assign_prepared(
     return prepared.out, info
 
 
+_DEFAULT_RUNTIME_LOCK = RLock()
+_DEFAULT_RUNTIMES: dict[int, FlashKMeansAssignRuntime] = {}
+
+
+def _default_runtime(device_index: int) -> FlashKMeansAssignRuntime:
+    """Return the process-wide per-device runtime backing ``flash_kmeans_assign``."""
+
+    runtime = _DEFAULT_RUNTIMES.get(device_index)
+    if runtime is None:
+        with _DEFAULT_RUNTIME_LOCK:
+            runtime = _DEFAULT_RUNTIMES.get(device_index)
+            if runtime is None:
+                runtime = FlashKMeansAssignRuntime(device=device_index)
+                _DEFAULT_RUNTIMES[device_index] = runtime
+    return runtime
+
+
 def flash_kmeans_assign(
     x: Any,
     centroids: Any,
@@ -992,21 +1054,32 @@ def flash_kmeans_assign(
     timeout_ms: float | None = None,
     return_info: bool = False,
 ):
-    """Assign points to centroids through a cold prepared/direct launch."""
-    timeout_ms = _validate_timeout(timeout_ms)
-    with launch_context(arch=arch, stream=stream, timeout_ms=timeout_ms):
-        prepared = prepare_flash_kmeans_assign(
-            x,
-            centroids,
-            out=out,
-            x_sq=x_sq,
-            c_sq=c_sq,
-            arch=arch,
-            stream=stream,
-            timeout_ms=timeout_ms,
-        )
-        return flash_kmeans_assign_prepared(
-            prepared,
-            stream=prepared.stream,
-            return_info=return_info,
+    """Assign points to centroids through the per-device signature plan cache.
+
+    The first call for a signature runs the frozen guard cascade once to
+    construct its launch plan and CUDA graph; subsequent calls are
+    pointer-overwrite graph replays on the plan's stream. A caller-provided
+    ``out=`` is written through; default outputs come from the signature's
+    plan-owned pool, so a default-output result must be consumed (or cloned)
+    before two further default-output calls of the same signature overwrite
+    its storage.
+    """
+    import torch
+
+    if not isinstance(x, torch.Tensor) or not getattr(x, "is_cuda", False):
+        raise TypeError("x must be a CUDA torch.Tensor")
+    runtime = _default_runtime(_tensor_device_index(x))
+    if arch is not None and str(arch) != runtime.arch:
+        raise ValueError(
+            f"Flash-KMeans launch arch must match the active device: requested {arch}, detected {runtime.arch}"
         )
+    return runtime.compute(
+        x,
+        centroids,
+        out=out,
+        x_sq=x_sq,
+        c_sq=c_sq,
+        stream=stream,
+        timeout_ms=timeout_ms,
+        return_info=return_info,
+    )
diff --git a/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json b/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
index 8983105e..e1fd0bb4 100644
--- a/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
+++ b/cake_exports/kmeans/src/flashlib_cake_kmeans/manifest.json
@@ -25,7 +25,7 @@
       "init": ".interface:init",
       "prepare_flash_kmeans_assign": ".interface:prepare_flash_kmeans_assign"
     },
-    "sha256": "21acf8461227184f0debdf147a5e70a37c52ce2e3b051178b8e906a5316621a2",
+    "sha256": "e5f7cbc5c8b6b666b8c9c546f06e82c94b8dff7049032332ea0b936a5df4eac1",
     "tvm_ffi_exports": {
       "flash_kmeans_assign": ".interface:flash_kmeans_assign"
     },
@@ -65,11 +65,11 @@
         "shared_preprocess": {
           "implementation_entrypoint": "flashlib_cake_kmeans._row_norm:PreparedBF16PairRowNorm",
           "result_source_sha256_field": "preprocess_source_sha256",
-          "source_sha256": "de4410a1b997eaa64847f05e4af5e37f44b001409717c9923b1610d21f2c4104"
+          "source_sha256": "aa67813cf1cc39b8ae96970a737e926f7b3a65dac63dbeb6362f2dacf066e26e"
         }
       },
       "benchmark_registry_baseline_key": "triton_h200_07cf_dual_lane_v1",
-      "benchmark_registry_baseline_sha256": "b0f66fe825e6e1aed7c85dc95c4f3e55c02f762e4251d2a4e21f12c87c5a486c",
+      "benchmark_registry_baseline_sha256": "bdfd30338aa614f09817af1498c1115a0b1732a3340a1acbc172d0e4dd4674c4",
       "benchmark_registry_candidate_entrypoint": "loom.examples.weave.flash_kmeans_assign_dispatcher:launch_for_eval",
       "benchmark_registry_key": "flash_kmeans_assign_dispatch_full_contract",
       "benchmark_registry_shape_labels_sha256": "172741a45af34837224b4005e0b6ba45637a07c7a4cabc88ed85ec95670e6290",
@@ -741,7 +741,7 @@
     }
   },
   "format_version": 1,
-  "generated_at_utc": "2026-07-08T23:26:07.392069+00:00",
+  "generated_at_utc": "2026-07-09T04:26:21.680464+00:00",
   "generator": "loom.export.kernel_repo",
   "kernels": [
     {
@@ -27774,7 +27774,7 @@
     "module_count": 52,
     "route_decision_count": 0
   },
-  "source_commit": "a03428fc8362e2785d2e6a657fd70a74c8ed1c0d",
+  "source_commit": "42070e96d0734cb580854baef60f17625ba33bb5",
   "source_repo": "ssh://git@gitlab-master.nvidia.com:12051/cake/cake.git",
   "tvm_ffi": {
     "adapter": "tvm_ffi.py",